A method of metastability handling for an analog-to-digital converter

Abstract

The application provides a method for processing metastable state of an analog-to-digital converter, and relates to the technical field of processing metastable state of an analog-to-digital converter, and aims to identify and process metastable state without increasing a comparator. A first capacitor array is used to receive a sampling analog signal, a second capacitor array is used to generate a plurality of reference voltages, three comparators are used to compare the sampling analog signal with different reference voltages and output respective comparison results and comparison effective indication bits, and a control module is used to realize a complete approximation period in a single approximation period mode according to the output results of the comparators. The processing method of the metastable state comprises the following steps: encoding the comparison results of the comparators output by the control module in a manner of converting differential encoding into single-ended encoding; the control module is provided with a comparator asynchronous clock and a metastable state processing module, and the metastable state processing module is used to detect and process metastable state events according to the numerical value of the comparison effective indication bits. The application has the advantages of saving power consumption and area.

Description

Technical Field

[0001] This invention relates to the field of metastable processing technology for analog-to-digital converters, and more specifically, to a metastable processing method for analog-to-digital converters. Background Technology

[0002] Metastability in analog-to-digital converters refers to the phenomenon that the comparator cannot latch a valid comparison result within a specific time.

[0003] With the continuous advancement of semiconductor technology, successive approximation analog-to-digital converters (ADCs) with asynchronous clocks are becoming increasingly faster. The metastability problem of comparators during quantization is also becoming more prominent, severely impacting the asynchronous serial logic and performance of the ADC. Therefore, avoiding errors caused by metastability has become a key design consideration. On one hand, it is necessary to improve the 2b / cycle metastability detection mechanism to prevent the asynchronous clock of the successive approximation ADC from stalling and preventing subsequent quantization. On the other hand, it is necessary to design the decoding for metastability scenarios to avoid the impact of metastable output error codes. For high-speed ADCs, metastability detection is typically achieved through a fixed clock delay. If the comparator has not latched a result by the time the delayed clock arrives, a metastability event is considered to have occurred. For traditional successive approximation analog-to-digital converters (ADCs) with a 1-bit / cycle configuration, there is a scheme that uses two comparators working together, allowing each comparator to operate at a different offset voltage set by the user, thus avoiding metastability caused by a single comparator. 2-bit / cycle successive approximation ADCs typically use a three-comparator configuration, employing a similar scheme of adding additional comparators to work together. Compared to 1-bit / cycle, this requires more comparators, resulting in wasted power consumption and area.

[0004] Therefore, it is necessary to optimize the metastability handling method of the 2b / cycle successive approximation analog-to-digital converter to identify and handle metastability without adding comparators, thereby saving power consumption and area. Summary of the Invention

[0005] The purpose of this invention is to provide a metastable state processing method for analog-to-digital converters, which enables the identification and processing of metastable states without adding a comparator.

[0006] This invention is achieved through the following technical solution: A metastable processing method for analog-to-digital converters includes: The first capacitor array receives the sampled analog signal, and the second capacitor array generates multiple reference voltages. The sampled analog signal is compared with different reference voltages using three comparators, and each comparator outputs its own comparison result and comparison validity indicator bit. The control module achieves a complete approximation of the cycle by using a single successive approximation cycle based on the output of the comparator. The encoder encodes the comparison result of the comparator output from the control module in a differential encoding to single-ended manner. The control module is equipped with a comparator asynchronous clock and a metastable state processing module. The metastable state processing module is used to detect and process metastable events based on the comparison valid indicator bit.

[0007] Preferably, the method of comparing the sampled analog signal with different reference voltages using three comparators is as follows: The positive input terminals of the first, second, and third comparators are all input to the quantized and flipped sampled analog signal, and the negative input terminals of the first, second, and third comparators are input to the first reference voltage, the ground signal, and the second reference voltage, respectively.

[0008] Preferably, the first reference voltage and the second reference voltage are opposite voltages.

[0009] Preferably, the comparator asynchronous clock includes multiple MOSFET devices, multiple delay units, and multiple logic gates; The gates of the first MOSFET device, the second MOSFET device, and the third MOSFET device are respectively connected to the comparison valid indicator bits output by the three comparators. The drain of the first MOSFET device is connected to the input terminal of the second delay unit and the drain of the fourth MOSFET device. The source of the first MOSFET device is connected to the drain of the second MOSFET device. The source of the second MOSFET device is connected to the drain of the third MOSFET device. The source of the third MOSFET device is connected to the drain of the fifth MOSFET device. The source of the fifth MOSFET device is connected to the power supply. The source of the fourth MOSFET device is grounded. The gates of the fifth MOSFET device and the fourth MOSFET device are connected, and their common node is connected to the input terminal of the first delay unit and the output terminal of the first NOT gate. The input of the first NOT gate is connected to the drain of the sixth MOSFET device, the source of the sixth MOSFET device is grounded, and the drain of the sixth MOSFET device is connected to the output of the second delay unit. The source of the seventh MOSFET is grounded, the gate of the seventh MOSFET is connected to the output of the second NOT gate, the drain of the seventh MOSFET is connected to the drain of the eighth MOSFET, the source of the eighth MOSFET is grounded, the output of the first delay unit and the input of the second NOT gate are respectively connected to the two inputs of the NAND gate, and the output of the NAND gate is connected to the gate of the eighth MOSFET.

[0010] Preferably, the metastable processing module includes a third delay unit and a ninth MOSFET device; The input of the third delay unit is connected to the common node of the gate of the fifth MOSFET device and the gate of the fourth MOSFET device. The input of the third delay unit is connected to the gate of the ninth MOSFET device. The drain of the ninth MOSFET device is connected to the drain of the first MOSFET device. The source of the ninth MOSFET device is connected to the source of the third MOSFET device.

[0011] Preferably, all of the MOSFET devices are P-type MOSFET devices.

[0012] Preferably, the third delay unit is an adjustable delay unit.

[0013] Preferably, the three comparators have the same structure, each including a differential comparator and an XNOR gate; The positive and inverting outputs of the differential comparator are connected to the two inputs of the XNOR gate, respectively. The output of the XNOR gate outputs a comparison valid indicator bit.

[0014] Preferably, the method for implementing differential encoding to single-ended encoding is as follows: Each digit is weighted and summed in both positive and negative parts:

[0015] ; in, The encoded output, and These are the i-bit values ​​at the positive output terminal and the i-bit values ​​at the inverting output terminal of the differential comparator, respectively. .

[0016] Preferably, the method for the single successive approximation period is as follows: The capacitors of the first capacitor array and the second capacitor array are flipped according to the output of the comparator. The comparator output is re-acquired based on the first and second capacitor arrays after the capacitors are flipped; Repeat the above steps until all successive approximation quantization cycles are completed.

[0017] The technical solution of the present invention has at least the following advantages and beneficial effects: This invention enables metastability detection and correction without adding an additional comparator by jointly processing the output of an existing three comparator and the comparison validity indicator bit, thus avoiding the power consumption and chip area consumption caused by adding a hardware comparator. This invention introduces a metastable state processing module into the control module to detect and respond to metastable events within each successive approximation cycle, thereby ensuring the operational stability and reliability of the successive approximation analog-to-digital converter without adding a comparator. This invention enables real-time determination of whether the comparator has latched the result within a specified time by setting a comparison validity indicator bit. This method has the advantages of high efficiency and low computing power. This invention employs a differential coding to single-ended coding method, which maintains quantization accuracy while reducing coding errors caused by metastability, thereby improving the accuracy of the output codewords. This invention optimizes the metastability handling method for 2b / cycle successive approximation analog-to-digital converters. Compared with the traditional multi-comparator collaborative scheme, it reduces hardware complexity while taking into account the design requirements of high speed and low power consumption. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of the analog-to-digital converter provided in Embodiment 1 of the present invention; Figure 2 This is a schematic diagram of the comparator asynchronous clock and metastability processing module provided in Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the comparator provided in Embodiment 2 of the present invention; Icons: 101-Second capacitor array, 102-First capacitor array, 104-First comparator, 105-Second comparator, 106-Third comparator, 107-Control module, 108-Encoder, 216-NAND gate, 215-Second NOT gate, 214-First NOT gate, 212-Third delay unit, 211-First delay unit, 210-Second delay unit, 301-Differential comparator, 302-XNOR gate, Q1-First MOSFET device, Q2-Second MOSFET device, Q3-Third MOSFET device, Q4-Fourth MOSFET device, Q5-Fifth MOSFET device, Q6-Sixth MOSFET device, Q7-Seventh MOSFET device, Q8-Eighth MOSFET device, Q9-Ninth MOSFET device. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. The components of the embodiments of the present invention described and shown in the accompanying drawings can generally be arranged and designed in various different configurations.

[0020] Example 1 This embodiment provides a metastability handling method for analog-to-digital converters, applied to analog-to-digital converters. See reference [link to relevant documentation]. Figure 1 ,include: The first capacitor array 102 receives the sampled analog signal, and the second capacitor array 101 generates multiple reference voltages. The second capacitor array 101 is similar to a flash analog-to-digital converter structure. Here, it mainly generates two reference voltages for the comparator to use, thereby achieving the purpose of quantizing two bits at a time.

[0021] The sampled analog signal is compared with different reference voltages using three comparators: the first comparator 104, the second comparator 105, and the third comparator 106. Each comparator outputs its own comparison result and a comparison validity indicator bit. The three comparators are a common structure, such as a 2-bit / cycle comparator. The comparison validity indicator bit indicates whether the comparison is valid by means of a numerical value, preferably using 0 and 1.

[0022] The control module 107 achieves a complete approximation cycle through a single successive approximation cycle based on the comparator's output. In an analog-to-digital converter, this single successive approximation cycle method typically involves: The capacitors of the first capacitor array 102 and the second capacitor array 101 are flipped according to the output of the comparator. The comparator output is re-acquired based on the first capacitor array 102 and the second capacitor array 101 after the capacitor flip; Repeat the above steps until all successive approximation quantization cycles are completed.

[0023] The encoder 108 encodes the comparison result of the comparator output by the control module 107 in a differential encoding to single-ended manner, thereby outputting the correct digital codeword result.

[0024] The control module 107 is equipped with a comparator asynchronous clock and a metastable state processing module. The metastable state processing module is used to detect and process metastable events based on the comparison valid indicator bit.

[0025] The above scheme can implement a metastability detection circuit that performs combinational logic judgment on the results of a 2b / cycle three comparator without adding additional comparators, without increasing additional power consumption or area. Simultaneously, it requires almost no processing in the decoding circuit design; weighted codeword processing is sufficient to obtain the correct weighted result even when metastability occurs, without affecting the subsequent normal successive approximation quantization cycle of the analog-to-digital converter. With this design, there is no need to use methods such as direct setting or skipping the entire quantization cycle, making the scheme in this embodiment also applicable to high-precision analog-to-digital converters.

[0026] Example 2 This embodiment is based on the technical solution of Embodiment 1, and further explains the specific implementation of the metastable processing module and the differential encoding to single-end conversion.

[0027] First, the data processing of the metastable processing module is based on the outputs of three comparators. In this embodiment, the method of comparing the sampled analog signal with different reference voltages using three comparators is as follows: The positive input terminals of the first comparator 104, the second comparator 105, and the third comparator 106 are all input to the sampled analog signal after quantization and inversion. The negative input terminals of the first comparator 104, the second comparator 105, and the third comparator 106 are respectively input to the first reference voltage, the ground signal, and the second reference voltage.

[0028] The first reference voltage and the second reference voltage are opposite voltages to each other.

[0029] Based on this, asynchronous timing control of the three comparators is achieved through an asynchronous clock on the comparators. (See [reference]). Figure 2 The comparator asynchronous clock includes multiple MOSFET devices, multiple delay units, and multiple logic gates; The gates of the first MOSFET device Q1, the second MOSFET device Q2, and the third MOSFET device Q3 are respectively connected to the comparison valid indicator bits output by the three comparators. The drain of the first MOSFET device Q1 is connected to the input terminal of the second delay unit 210 and the drain of the fourth MOSFET device Q4. The source of the first MOSFET device Q1 is connected to the drain of the second MOSFET device Q2. The source of the second MOSFET device Q2 is connected to the drain of the third MOSFET device Q3. The source of the third MOSFET device Q3 is connected to the drain of the fifth MOSFET device Q5. The source of the fifth MOSFET device Q5 is connected to the power supply. The source of the fourth MOSFET device Q4 is grounded. The gate of the fifth MOSFET device Q5 and the gate of the fourth MOSFET device Q4 are connected, and their common node is connected to the input terminal of the first delay unit 211 and the output terminal of the first NOT gate 214. The input terminal of the first NOT gate 214 is connected to the drain of the sixth MOSFET device Q6, the source of the sixth MOSFET device Q6 is grounded, and the drain of the sixth MOSFET device Q6 is connected to the output terminal of the second delay unit 210. The source of the seventh MOSFET device Q7 is grounded, the gate of the seventh MOSFET device Q7 is connected to the output of the second NOT gate 215, the drain of the seventh MOSFET device Q7 is connected to the drain of the eighth MOSFET device Q8, the source of the eighth MOSFET device Q8 is grounded, the output of the first delay unit 211 and the input of the second NOT gate 215 are respectively connected to the two inputs of the NAND gate 216, and the output of the NAND gate 216 is connected to the gate of the eighth MOSFET device Q8.

[0030] Under the control of the asynchronous clock of the comparator above, the following signal terminals are first defined: The gates of the first MOSFET device Q1, the second MOSFET device Q2, and the third MOSFET device Q3 are respectively input to the three comparison valid indicator bits OUT0_VAL, OUT1_VAL, and OUT2_VAL of the three comparators. The signal at the drain of the first MOSFET device Q1 is denoted as DETECT, and the signal after passing through the second delay unit 210 is denoted as DETECT_D. The signal at the common node where the gates of the fifth MOSFET device Q5 and the fourth MOSFET device Q4 are connected is COMP_RST, while the signal at the input of the first NOT gate 214 is COMP_RSTN. The gate of the eighth MOSFET device Q8 has a TRG_P signal, and the input of the second NOT gate 215 has a CLK_COMP signal. The output of the first delay unit 211 is COMP_RSTN_D.

[0031] Based on this, the working method is as follows: Assuming the power supply potential is "1" and the ground potential is "0", the comparator is in a reset state by default (i.e., the COMP_RSTN signal is "0"). The dashed box 213 shows the asynchronous operation timing of the comparator. Starting from the CLK_COMP signal being pulled high to "1", the TRG_P signal is pulled low to "0". Because the eighth MOSFET Q8 has a larger width-to-length ratio than the seventh MOSFET Q7, the comparator's COMP_RSTN signal is pulled high to "1" by the eighth MOSFET Q8, and COMP_RST is "0". The comparator is then reset and compared. If all three comparators produce a result (i.e., all comparisons are valid), the three comparators output OUT0_VAL, OUT1_VAL, and OUT2_VAL respectively. When all three valid comparison indicator bits AL are pulled low to "0", the DETECT signal is pulled high to "1". After a delay of the second delay unit 210, DETECT_D becomes "1", turning on the sixth MOSFET Q6. Since COMP_RST_D is "0" after the first delay module from COMP_RST, TRG_P is pulled to "1", and the eighth MOSFET Q8 is turned off. Therefore, the COMP_RSTN signal is pulled low to "0", and COMP_RST is pulled high to "1", and the comparator enters the reset state, thus completing one comparator cycle. Subsequently, COMP_RST_D becomes "1" after a delay of 211 from COMP_RST. At this time, CLK_COMP is still "1", so TRG_P is pulled low. The eighth MOSFET Q8 pulls COMP_RSTN high to "1", COMP_RST becomes "0", the comparator is reset and compares, and the second comparison cycle begins, repeating the cycle. While CLK_COMP is "1", the comparator will operate according to the asynchronous timing of this cycle until the entire successive approximation quantization cycle is completed, at which point CLK_COMP is pulled low to "0" and the asynchronous clock is turned off.

[0032] When a metastable event occurs, one of the three comparators will be in a state where it cannot latch the result. The three valid comparison indicators OUT0_VAL, OUT0_VAL, and OUT0_VAL cannot all be pulled low to "0". Therefore, the path between the first MOSFET device Q1, the second MOSFET device Q2, and the third MOSFET device Q3 within the dashed box 213 is interrupted. DETECT cannot be pulled high to "1" through this path, thus COMP_RSTN cannot be pulled low to reset the comparators, and the normal asynchronous clock cannot continue. Therefore, to solve this problem, as a preferred embodiment, the metastable processing module includes a third delay unit 212 and a ninth MOSFET device Q9. The input terminal of the third delay unit 212 is connected to the common node of the gate of the fifth MOSFET device Q5 and the gate of the fourth MOSFET device Q4. The input terminal of the third delay unit 212 is connected to the gate of the ninth MOSFET device Q9. The drain of the ninth MOSFET device Q9 is connected to the drain of the first MOSFET device Q1. The source of the ninth MOSFET device Q9 is connected to the source of the third MOSFET device Q3.

[0033] The principle of this circuit is as follows: COMP_RST is processed by the third delay unit 212 to obtain DETECT_SYN. If, after the comparator is de-reset, the three valid comparison indicators OUT0_VAL, OUT0_VAL, and OUT0_VAL cannot all be pulled low to "0" at the end of the delay in the third delay unit 212, a metastable event is considered to have occurred. DETECT_SYN is pulled low to "0", and the auxiliary DETECT signal is pulled high to "1", allowing COMP_RSTN to be pulled low through the sixth RSTN to reset the comparator, and the comparator's asynchronous clock continues to operate normally. The third delay unit 212 is an adjustable delay unit. It is particularly important to note that the delay length of the third delay unit 212 should be set reasonably. In order not to interfere with the comparator result prematurely, the delay should be increased as much as possible, but it should be ensured that all successive approximation asynchronous comparison cycles can be completed within one complete quantization cycle of the analog-to-digital converter. The paths of the first MOSFET device Q1, the second MOSFET device Q2, and the third MOSFET device Q3 can be disconnected first, so that all asynchronous clock logic is completed through the loop formed by the ninth MOSFET device Q9. Simulation is then used to determine whether the analog-to-digital converter can complete all successive approximation asynchronous comparison cycles, thereby determining the maximum delay time required by the third delay unit 212. As a preferred embodiment, all MOSFET devices are P-type MOSFET devices.

[0034] Generally speaking, participation Figure 3 The three comparators have the same structure, each including a differential comparator 301 and an XNOR gate 302; The positive output terminal OUT and the inverting output terminal OUTN of the differential comparator 301 are connected to the two input terminals of the XNOR gate 302, respectively. The output terminal of the XNOR gate 302 outputs the comparison valid indicator bit OUT_VAL.

[0035] OUT / OUTN is the comparator's output, which defaults to "0 / 0". When the comparator outputs a correct result, OUT / OUTN is "1 / 0" or "0 / 1", and the OUT_VAL signal is "0". When the comparator is in a metastable state, it cannot latch the result, so OUT / OUTN is "0 / 0".

[0036] In this embodiment, the method for implementing differential encoding to single-ended encoding is as follows: Each digit is weighted and summed in both positive and negative parts:

[0037] ; in, The encoded output, and These are the i-bit values ​​at the positive output terminal and the i-bit values ​​at the inverting output terminal of the differential comparator, respectively. .

[0038] Traditional encoding methods often introduce coarse errors after a metastable event occurs. Therefore, most methods directly set this bit and subsequent output bits to "100..0" or "011…1", effectively ending the entire quantization cycle. However, this approach directly assumes the input is less than 1 LSB when metastability occurs, potentially introducing noise and errors in high-precision analog-to-digital converters (where 1 LSB is relatively small). In this embodiment, when a metastable event occurs, OUT / OUTN is "0 / 0", the weight of this bit in the weighted encoding is 0, and the corresponding capacitor does not flip, waiting for the next successive approximation comparison cycle. Metastability is a very low-probability event. If no new metastable events occur, successive approximation quantization proceeds normally. If another metastable event occurs, the capacitor is not flipped, and the digital weighting result is not affected. This cycle repeats, transferring the smaller input result from the metastable event to subsequent asynchronous cycle comparison processing.

[0039] In summary, the metastability detection scheme designed in this embodiment is applicable to 2b / cycle successive approximation analog-to-digital converters with asynchronous clocks, without increasing additional power consumption or area. It also overcomes the errors caused by traditional direct set-output quantization by transferring the smaller input result during metastability to subsequent asynchronous cycle comparison processing, thus avoiding the noise and error effects of a single metastability event.

[0040] The above are merely preferred embodiments of the present invention and are not intended to limit the present invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A metastable processing method for an analog-to-digital converter (ADC), wherein a sampled analog signal is received through a first capacitor array, multiple reference voltages are generated through a second capacitor array, the sampled analog signal is compared with different reference voltages through three comparators, each comparator outputs its own comparison result and a comparison validity indicator bit, and a control module achieves a complete approximation cycle through a single successive approximation cycle based on the comparator output results, characterized in that, Methods for handling metastable states include: The encoder encodes the comparison result of the comparator output from the control module in a differential encoding to single-ended manner. The control module is equipped with a comparator asynchronous clock and a metastability processing module. The metastability processing module is used to detect and process metastability events based on the value of the comparison valid indicator bit. The comparator asynchronous clock includes 8 MOSFET devices, 2 delay units, a first NOT gate, a second NOT gate, and a NAND gate; The gates of the first MOSFET device, the second MOSFET device, and the third MOSFET device are respectively connected to the comparison valid indicator bits output by the three comparators. The drain of the first MOSFET device is connected to the input terminal of the second delay unit and the drain of the fourth MOSFET device. The source of the first MOSFET device is connected to the drain of the second MOSFET device. The source of the second MOSFET device is connected to the drain of the third MOSFET device. The source of the third MOSFET device is connected to the drain of the fifth MOSFET device. The source of the fifth MOSFET device is connected to the power supply. The source of the fourth MOSFET device is grounded. The gates of the fifth MOSFET device and the fourth MOSFET device are connected, and their common node is connected to the input terminal of the first delay unit and the output terminal of the first NOT gate. The input of the first NOT gate is connected to the drain of the sixth MOSFET device, the source of the sixth MOSFET device is grounded, and the gate of the sixth MOSFET device is connected to the output of the second delay unit. The source of the seventh MOSFET is grounded, the gate of the seventh MOSFET is connected to the output of the second NOT gate, the drain of the seventh MOSFET is connected to the drain of the eighth MOSFET, and the common node of the drains of the seventh and eighth MOSFETs is connected to the drain of the sixth MOSFET. The source of the eighth MOSFET is connected to the power supply. The output of the first delay unit and the input of the second NOT gate are respectively connected to the two inputs of the NAND gate. The input of the second NOT gate is connected to the clock signal of the comparator, and the output of the NAND gate is connected to the gate of the eighth MOSFET. The metastable state processing module includes a third delay unit and a ninth MOSFET device; The input terminal of the third delay unit is connected to the common node of the gate of the fifth MOSFET device and the gate of the fourth MOSFET device. The output terminal of the third delay unit is connected to the gate of the ninth MOSFET device. The drain of the ninth MOSFET device is connected to the drain of the first MOSFET device. The source of the ninth MOSFET device is connected to the source of the third MOSFET device. The three comparators have the same structure, each including a differential comparator and an XNOR gate; The positive and inverting outputs of the differential comparator are connected to the two inputs of the XNOR gate, and the output of the XNOR gate outputs a comparison valid indicator bit. The method for implementing differential encoding to single-ended conversion is as follows: Each digit is weighted and summed in both positive and negative parts: ； in, The encoded output, and These are the i-bit values ​​at the positive output terminal and the i-bit values ​​at the inverting output terminal of the differential comparator, respectively. .

2. The metastable processing method for an analog-to-digital converter according to claim 1, characterized in that, The method of comparing the sampled analog signal with different reference voltages using three comparators is as follows: The positive input terminals of the first comparator, the second comparator, and the third comparator are all input with sampled analog signals, and the negative input terminals of the first comparator, the second comparator, and the third comparator are input with the first reference voltage, the ground signal, and the second reference voltage, respectively.

3. The metastable processing method for an analog-to-digital converter according to claim 2, characterized in that, The first reference voltage and the second reference voltage are opposite voltages to each other.

4. The metastable processing method for an analog-to-digital converter according to claim 1, characterized in that, The third delay unit is an adjustable delay unit.

5. The metastable processing method for an analog-to-digital converter according to claim 1, characterized in that, The method for a single successive approximation period is as follows: The capacitors of the first capacitor array and the second capacitor array are flipped according to the output of the comparator. The comparator output is re-acquired based on the first and second capacitor arrays after the capacitors are flipped; Repeat the above steps until all successive approximation quantization cycles are completed.

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