Buried package substrate and processing method thereof

Abstract

The application discloses a kind of buried containment packaging substrate and its processing method, comprising: on the front surface of substrate, cover capacitor layer, get work board;Work board is made into inner layer circuit, and inner layer circuit is made on the front and back of work board, and positioning structure is formed on at least one of the front and back of work board;Dielectric layer and copper foil are stacked on the front and back of work board respectively, and first intermediate plate is laminated, and dielectric layer and its corresponding positioning structure form mechanical lock;Outer layer circuit is made on the two copper foil of first intermediate plate, and the outer layer circuit of front surface has multiple signal lines;Isolation groove is arranged on a dielectric layer and exposed on the area between every two adjacent signal lines, so that the signal crosstalk between two adjacent signal lines is less than 15dB when working frequency is above 10GHz.The processing method improves the transmission quality of high-frequency signal, and improves the alignment accuracy and stability of the overall structure.

Description

Technical Field

[0001] This invention relates to the field of circuit board technology, and in particular to an embedded capacitor packaging substrate and its processing method. Background Technology

[0002] With the explosive growth of 5G communication, artificial intelligence chips, and high-performance computing (HPC), packaging substrates, as the core carriers of chips and external circuits, are increasingly trending towards higher frequencies and higher densities. Among these technologies, embedded board-level packaging, which directly embeds passive components such as resistors and capacitors into the substrate, significantly improves the integration, electrical performance, and reliability of electronic devices by replacing surface-mount components.

[0003] The core of buried capacitor substrates is the embedding of an ultra-thin dielectric layer (typically 3–12 μm thick) between circuit layers to form a distributed planar capacitor structure. This design utilizes the parallel-plate capacitor principle, increasing the capacitance density per unit area by reducing the dielectric thickness and filling with high-dielectric-constant materials. Vertical vias enable direct interconnection between bare chip electrodes and external circuits, shortening the signal transmission path to the micrometer level and reducing parasitic inductance (which can be <1 nH) and transmission loss. However, the manufacturing process of these buried capacitor substrates is prone to the following problems: ① Because the thermal expansion coefficients of the buried capacitor dielectric material are often not synchronized with those of the copper foil and substrate, thermal stress is easily generated during processing, leading to delamination, cracking, or capacitance drift. ② In achieving high frequency and high density, buried capacitor substrates also face signal crosstalk and signal integrity degradation issues. For example, under high-frequency signal transmission, traditional planar shielding layers fail due to the skin effect, resulting in poor high-frequency signal transmission quality on buried capacitor substrates.

[0004] In view of this, the present invention is hereby proposed. Summary of the Invention

[0005] To overcome the above-mentioned defects, the present invention provides a buried capacitor packaging substrate and its processing method. The processing method has the advantages of being simple, reasonable, easy to operate and implement, and low in processing cost. It effectively improves the signal crosstalk problem, enhances the transmission quality of high-frequency signals, and improves the alignment accuracy and stability of the overall structure of the buried capacitor packaging substrate, thus well meeting the production needs of the buried capacitor packaging substrate.

[0006] The technical solution adopted by this invention to solve its technical problem is: a method for processing a buried capacitor packaging substrate, comprising: A substrate is provided, and a capacitor layer is deposited on the front side of the substrate to obtain a working board; The inner layer circuitry is fabricated on the work board, so that while the inner layer circuitry is fabricated on both the front and back sides of the work board, a positioning structure is also formed on at least one of the front and back sides of the work board. A dielectric layer and a copper foil overlay are stacked on the front and back sides of the work board after the inner layer circuitry is fabricated, and then laminated to obtain the first intermediate board; wherein, the dielectric layer and its corresponding positioning structure form a mechanical lock; The obtained first intermediate board is fabricated with outer layer circuitry, thereby creating outer layer circuitry on the two copper foil layers respectively; wherein, one of the outer layer circuitry located on the side of the front of the working board has multiple signal lines. An isolation groove is provided on the dielectric layer and in the area between each two adjacent signal lines to achieve a signal crosstalk of less than 15dB between two adjacent signal lines when the buried capacitor package substrate is operating at a frequency above 10GHz.

[0007] As a further improvement of the present invention, the positioning structure is a positioning copper pillar with one end fixedly embedded in the substrate and the other end protruding from the capacitor layer, and the positioning structure is arranged on the edge area of ​​the working board. Correspondingly, a positioning hole groove is provided on the edge region of the dielectric layer to be inserted and matched with the positioning structure.

[0008] As a further improvement of the present invention, after performing the following processes on the working board in sequence: laminating a functional copper foil layer, drilling, copper plating, through-hole electroplating, inner layer circuit pattern transfer, pattern electroplating, film removal, and etching, two electrically connected inner layer circuits and multiple positioning structures are produced.

[0009] As a further improvement of the present invention, the height H of the positioning copper column satisfies the following relationship: H=Tc+Tr+Δd, where Tc is the thickness of the functional copper foil layer, Tr is the thickness of the capacitor layer, and Δd is a preset tolerance compensation value.

[0010] As a further improvement of the present invention, the method for fabricating the outer layer circuit of the first intermediate board includes drilling, copper plating, through-hole electroplating, outer layer circuit pattern transfer, pattern electroplating, film removal and etching processes performed sequentially. Correspondingly, the outer layer circuitry located on the same side is electrically connected to the inner layer circuitry.

[0011] As a further improvement of the present invention, one of the outer layer circuits located on the side of the front of the working board also has a grounding pad, and one of the outer layer circuits located on the side of the back of the working board has a heat dissipation pad. The grounding pad and the heat dissipation pad are respectively connected to the two inner layer circuits through connecting copper pillars. The connecting copper pillars are made by drilling, copper plating and through-hole electroplating of the first intermediate board in sequence.

[0012] As a further improvement of the present invention, a dielectric layer located on the side of the front of the working board is defined as a first dielectric layer; The isolation grooves, with a depth of 20–100 μm and a width of 10–50 μm, are respectively processed on the front side of the first dielectric layer and in the area between each pair of adjacent signal lines using a laser ablation process.

[0013] As a further improvement of the present invention, the isolation groove is selectively filled with a thermally conductive material with a thermal conductivity ≤0.5W / m·K.

[0014] As a further improvement of the present invention, a second intermediate plate is defined as follows: after the isolation groove is formed, a second intermediate plate is obtained; The processing method of the embedded capacitor packaging substrate further includes: filling the isolation groove with a water-soluble polymer, then printing a solder resist layer at preset positions on the front and back sides of the second intermediate plate, pre-curing the solder resist layer, washing away the water-soluble polymer with water, and then continuing to cure until the solder resist layer is completely cured and formed.

[0015] The present invention also provides a buried capacitor packaging substrate, which is manufactured using the buried capacitor packaging substrate processing method described in the present invention.

[0016] The beneficial effects of this invention are as follows: Compared with the prior art, the processing method of the embedded capacitor packaging substrate provided by this invention has the following advantages: ① This invention innovatively sets an isolation groove between each pair of adjacent signal lines, which is equivalent to increasing the physical distance between the two adjacent signal lines, thereby reducing parasitic capacitance and effectively improving signal crosstalk between the two adjacent signal lines. At the same time, the presence of the isolation groove also interferes with the electromagnetic field distribution around the signal lines, so that the transmission quality (signal integrity) of high-frequency signals is significantly improved, such as achieving a signal crosstalk of less than 15dB between the two adjacent signal lines when the embedded capacitor packaging substrate is operating at a frequency above 10GHz. ② In the layering process, this invention employs a positioning relationship where "the positioning structure and the dielectric layer form a mechanical lock." This allows for the rapid and precise placement of the dielectric layer on the front side of the intermediate plate B. Furthermore, it ensures a strong mechanical lock between the dielectric layer and the positioning structure after lamination, effectively preventing layer misalignment caused by the difference in thermal expansion coefficients between the dielectric and capacitor layers. This significantly improves the alignment accuracy and stability of the overall structure of the first intermediate plate B2. ③ The processing method provided in this application is reasonable, simple, and easy to implement. Moreover, since no additional outer shielding accessories are required, it significantly reduces production costs. Attached Figure Description

[0017] Figure 1 This is a flowchart of the processing method for the buried capacitor packaging substrate described in Embodiment 1 of the present invention; Figure 2 This is a cross-sectional view of the work board described in Example 1; Figure 3 This is a schematic cross-sectional view of the intermediate board A obtained after laminating a functional copper foil layer and drilling a hole in the working board in Example 1. Figure 4 This is a schematic cross-sectional view of the intermediate board B obtained after the inner layer circuitry of the work board is fabricated in Example 1. Figure 5 This is a schematic cross-sectional view of the dielectric layer described in Example 1; Figure 6 This is a schematic cross-sectional view of the first intermediate plate in Embodiment 1; Figure 7 This is a schematic cross-sectional view of the second intermediate plate in Example 1; Figure 8 This is a schematic cross-sectional view of the embedded capacitor packaging substrate obtained in Example 1.

[0018] Referring to the accompanying drawings, the following explanations are provided: 1. Substrate; 2. Capacitor layer; 3. Inner layer circuitry; 4. Positioning structure; 5. Dielectric layer; 50. Positioning hole / groove; 6. Copper foil overlay; 7. Outer layer circuitry; 71. Signal line; 72. Ground pad; 73. Heat dissipation pad; 8. Isolation groove; 9. Connecting copper pillar; 10. Functional copper foil layer; 11. Solder resist layer; 120. Blind slot; 121. Through hole; B1. Working board; B2. First intermediate board; B3. Second intermediate board. Detailed Implementation

[0019] The preferred embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0020] Example 1:

[0021] Please see the appendix Figure 1 To be continued Figure 8 As shown, this embodiment 1 provides a method for processing a buried capacitor packaging substrate, including the following processing steps: S1: A substrate 1 is provided, and a capacitor layer 2 is deposited on the front side of the substrate 1 to obtain a working board B1; see appendix for details. Figure 2 As shown.

[0022] In this embodiment, the substrate 1 may be, but is not limited to, a copper layer or a core board structure. In the field of circuit board technology, the core board structure is usually composed of two layers of copper foil sandwiching a cured prepreg, which is a well-known technology and will not be described in detail here. The thickness of the substrate 1 is determined according to the product design requirements of the buried capacitor packaging substrate, and this embodiment does not impose any restrictions.

[0023] The capacitor layer 2 is formed on the front side of the substrate 1 by a coating process. The material and thickness of the capacitor layer 2 are determined according to the product design requirements of the embedded capacitor packaging substrate. For example, in order to better meet the functional requirements of the capacitor layer 2 and the manufacturing and functional requirements of the positioning structure 4, the thickness Tr of the capacitor layer 2 is optimally controlled to be 3 to 12 μm.

[0024] S2: The inner layer circuitry is fabricated on the work board B1, so that while the inner layer circuitry 3 is fabricated on both the front and back surfaces of the work board B1, a positioning structure 4 is also formed on at least one of the front and back surfaces of the work board B1; for details, please refer to the appendix. Figure 4 As shown.

[0025] In this embodiment, the specific manufacturing method for the inner layer circuit of the work board B1 is as follows: the work board B1 is sequentially laminated with a functional copper foil layer 10, drilled, copper plating, through-hole electroplating, inner layer circuit pattern transfer, pattern electroplating, film removal and etching.

[0026] The aforementioned processing of the laminated functional copper foil layer 10 refers to the application of a lamination process to the front and back surfaces of the work board B1, with details provided in the appendix. Figure 3 As shown.

[0027] To ensure the symmetry of the product structure, the two functional copper foil layers 10 have the same thickness. Furthermore, to better meet the fabrication requirements of the inner circuitry 3 and the positioning structure 4, the thickness Tc of the functional copper foil layer 10 is optimally controlled to 3 μm. The lamination process is a commonly used technique in circuit board manufacturing, and therefore will not be described in detail here. However, specifically, this embodiment preferably employs an electric heating lamination process.

[0028] The aforementioned drilling process refers to using laser technology (specifically including windowing and slotting / or hole burning processes) to process multiple blind slots 120 and multiple through holes 121 on the board. The blind slots 120 have a portion of the substrate 1 as their bottom and open into one of the functional copper foil layers 10 (this functional copper foil layer 10 is adjacent to the capacitor layer 2). The through holes 121 penetrate two of the functional copper foil layers 10. For details, please refer to the appendix. Figure 3 As shown.

[0029] In addition, for ease of description, this embodiment defines the board obtained after the above drilling operation on the working board B1 as the intermediate board A.

[0030] The aforementioned copper plating and through-hole electroplating process refers to first depositing a seed layer on the surface, inner wall of the hole, and inner wall of the tank of the intermediate board A through a copper plating process, and then plating a copper layer in the blind tank 120 and the through hole 121 through a through-hole electroplating process. Furthermore, the copper layer in the blind tank 120 and the through hole 121 extends to be flush with the copper layer on the surface of the intermediate board A, so as to facilitate the precision fabrication of the inner layer circuit 3.

[0031] The aforementioned inner layer circuit pattern transfer process refers to the sequential processing of the intermediate board A after the above-mentioned through-hole electroplating process, including pre-coating treatment (including cleaning and drying processes, but depending on the processing requirements, a copper reduction process may also be provided before cleaning), coating with photosensitive dry film (which can be operated using a vacuum film laminator), exposure (which can be operated using an LDI exposure machine), and development, thereby transferring the pattern data of the inner layer circuit 3 and the pattern data of the positioning structure 4 onto the intermediate board A.

[0032] The aforementioned pattern electroplating process refers to plating a copper layer of a predetermined thickness onto the copper layer exposed outside the resist photosensitive dry film using a pattern electroplating process. It is understood that the copper thickness of the pattern electroplated layer is determined based on the predetermined copper thickness of the inner layer circuit 3, the thickness of the functional copper foil layer 10, and the aforementioned copper plating and via electroplating processing parameters. Since the predetermined copper thickness of the inner layer circuit 3 is not the focus of this application, no limitations are imposed on the processing parameters of the pattern electroplating.

[0033] The aforementioned stripping and etching process refers to completely removing the resist photosensitive dry film using a stripping solution, followed by etching away the copper layer previously covered by the resist photosensitive dry film using a flash etching process. This process yields the inner layer circuitry 3 and multiple positioning structures 4. For details, please refer to the appendix. Figure 4 As shown.

[0034] Furthermore, based on the aforementioned inner layer circuit fabrication method and appendix... Figure 4 It can be concluded that: ① If the board obtained after completing the inner layer circuit fabrication of the working board B1 is defined as the intermediate board B, the two inner layer circuits 3 respectively located on the front and back sides of the intermediate board B are electrically connected to each other. ② Multiple positioning structures 4 are respectively arranged on the edge area of ​​the intermediate board B, that is, multiple positioning structures 4 are respectively arranged on the edge area of ​​the working board B1, and each positioning structure 4 is a positioning copper pillar with one end fixedly embedded in the substrate 1 and the other end protruding from the capacitor layer 2.

[0035] Furthermore, in this embodiment, the height H of the positioning copper pillar is optimized to satisfy the following relationship: H=Tc+Tr+Δd, where Tc is the thickness of the functional copper foil layer 10 (e.g., 3μm), Tr is the thickness of the capacitor layer 2 (optimized to be 3~12μm), and Δd is the preset groove depth tolerance compensation value (optimized to be 5~10μm).

[0036] In addition, after the inner layer circuit is fabricated, AOI optical inspection is required on the inner layer circuit 3 and the positioning structure 4 to determine whether the inner layer circuit 3 and the positioning structure 4 meet the design requirements; any abnormalities should be dealt with in a timely manner to avoid omissions.

[0037] S3: A dielectric layer 5 and a copper foil reinforcement layer 6 are stacked on both the front and back surfaces of the intermediate plate B, respectively, and then laminated to obtain the first intermediate plate B2. See the appendix for details. Figure 6 As shown; wherein, the dielectric layer 5 and its corresponding positioning structure 4 form a mechanical lock.

[0038] In this embodiment, there are no restrictions on the material and thickness of the dielectric layer 5 or the thickness of the copper foil reinforcement layer 6; these are determined based on the product design requirements of the buried capacitor packaging substrate. However, it is understood that to ensure the symmetry of the product structure, the two dielectric layers 5 are made of the same material and have the same thickness, and the two copper foil reinforcement layers 6 are also made of the same thickness.

[0039] In addition, it should be emphasized that, in order to cooperate with the positioning structure 4, this embodiment also provides a positioning slot 50 on the edge region of one of the dielectric layers 5, which is inserted and cooperates with the positioning structure 4 (see Appendix for details). Figure 5 (As shown). Understandably, by designing the positioning copper pillars to interlock with the positioning slots 50, the dielectric layer 5 can be quickly and accurately stacked on the front side of the intermediate plate B. Furthermore, after lamination, a strong mechanical lock is formed between the dielectric layer 5 and the positioning structure 4, i.e., a strong mechanical lock is formed between the dielectric layer 5 and the front side of the intermediate plate B. This effectively prevents layer misalignment caused by the difference in thermal expansion coefficients between the dielectric layer 5 and the capacitor layer 2, thereby significantly improving the overall structural accuracy and stability of the first intermediate plate B2.

[0040] In addition, the lamination process in this step is preferably carried out using an electric heating pressing process.

[0041] S4: Fabricate the outer layer circuitry on the obtained first intermediate board B2, thereby fabricating the outer layer circuitry 7 on both copper foil layers 6; see appendix for details. Figure 7 As shown.

[0042] In this embodiment, the method for fabricating the outer layer circuit of the first intermediate board B2 is as follows: the first intermediate board B2 is sequentially subjected to drilling, copper plating, through-hole electroplating, outer layer circuit pattern transfer, pattern electroplating, film removal and etching.

[0043] Understandably, ① the above-described outer layer circuit fabrication method can refer to the inner layer circuit fabrication method described in S2 above, so it will not be repeated here. ② After drilling, copper plating, and through-hole electroplating are performed on the first intermediate board B2 in sequence, a plurality of connecting copper pillars 9 are obtained, which can electrically connect each copper foil layer 6 to its adjacent inner layer circuit 3. That is, the outer layer circuit 7 and the inner layer circuit 3 located on the same side are electrically connected through a plurality of connecting copper pillars 9. ③ Depending on the thickness of the copper foil layer 6, the outer layer circuit 7 can also be fabricated by a subtractive method.

[0044] In addition, in this embodiment, according to the product design requirements of the buried capacitor packaging substrate, the structures of the two outer layer lines 7 are designed as follows: one outer layer line 7 located on the side of the front of the working board B1 has multiple signal lines 71 and a ground pad 72, and the other outer layer line 7 located on the side of the back of the working board B1 has a heat dissipation pad 73. Specifically, the ground pad 72 and the heat dissipation pad 73 are respectively connected to the two inner layer lines 3 via connecting copper pillars 9. It is understood that the connecting copper pillars 9, while providing electrical connection, also provide excellent heat dissipation, improving the heat dissipation efficiency of the buried capacitor packaging substrate by more than 30%, significantly improving the working performance and reliability of the buried capacitor packaging substrate. Furthermore, the connecting copper pillars 9 connecting the ground pad 72 and the inner layer lines 3 can also promote a better signal return path and more stable grounding, thereby improving the overall signal integrity (including noise level and timing stability).

[0045] In addition, after the outer layer circuit 7 is fabricated, it is necessary to perform AOI optical inspection on the outer layer circuit 7 to detect and determine whether the outer layer circuit 7 meets the design requirements; if any abnormality is found, it should be dealt with in a timely manner to avoid any omissions.

[0046] S5: For ease of description, the dielectric layer 5 located next to the front side of the working board B1 is defined as the first dielectric layer. Isolation grooves 8 are respectively formed on the front side of the first dielectric layer, exposed in the area between each pair of adjacent signal lines 71, using a laser ablation process. This ensures that when the buried capacitor packaging substrate operates at a frequency above 10GHz, the signal crosstalk between two adjacent signal lines 71 is less than 15dB. See the appendix for details. Figure 7 As shown.

[0047] Understandably, this embodiment, by providing the isolation groove 8 between each pair of adjacent signal lines 71, effectively increases the physical distance between them, thereby reducing parasitic capacitance and improving signal crosstalk between adjacent signal lines 71. Simultaneously, the presence of the isolation groove 8 also interferes with the electromagnetic field distribution around the signal lines 71, significantly improving the transmission quality (signal integrity) of high-frequency signals. For example, when the embedded capacitor packaging substrate operates at a frequency above 10 GHz, the signal crosstalk between two adjacent signal lines 71 is less than 15 dB. That is, the isolation groove 8 acts as an "embedded waveguide isolator" within the embedded capacitor packaging substrate, belonging to a functional microstructure integrated inside the embedded capacitor packaging substrate.

[0048] Furthermore, based on the product design requirements of the buried capacitor packaging substrate, the specific structure of the isolation groove 8 is optimized as follows: the overall shape of the isolation groove 8 may be, but is not limited to, a rectangular groove structure (see Appendix). Figure 7 (as shown) or an inverted trapezoidal groove structure; the groove depth of the isolation groove 8 is determined according to the performance of the first dielectric layer, such as it can be designed to be 20-100μm, and further optimized to be 20-60μm; the groove width of the isolation groove 8 is determined according to the line spacing between two adjacent signal lines 71, such as it can be designed to be 10-50μm; and the ratio between the groove depth and the groove width of the isolation groove 8 is not less than 1:1.

[0049] Furthermore, depending on the product design requirements of the buried capacitor packaging substrate, the isolation groove 8 can be selectively filled with a thermally conductive material with a thermal conductivity of ≤0.5W / m·K (such as, but not limited to, aerogel) to improve the thermal conductivity and operational reliability of the buried capacitor packaging substrate.

[0050] In addition, for ease of description, this embodiment also defines the plate obtained after the isolation groove 8 is made as the second intermediate plate B3.

[0051] S6: Since the isolation groove 8 is not filled with thermally conductive material, a water-soluble polymer (such as, but not limited to, polyvinyl alcohol PVA) is filled into the isolation groove 8; then, a solder resist layer 11 (such as solder resist ink) is screen-printed at predetermined positions on both the front and back sides of the second intermediate plate B3. After the solder resist layer 11 is pre-cured at a low temperature (generally 70℃~80℃), the water-soluble polymer is washed away with water, and then high-temperature curing (generally 150℃~160℃) continues until the solder resist layer 11 is completely cured and formed. See the appendix for details. Figure 8 As shown.

[0052] Understandably, the water-soluble polymer, as a temporary filler, mainly serves to protect the isolation groove 8 structure, prevent the solder resist layer from penetrating, maintain surface flatness, and facilitate subsequent removal.

[0053] S7: After completing the above solder mask operation, the board obtained is subjected to routine surface treatment, finished product testing and other processing in sequence to complete the production of the subsequent embedded capacitor packaging substrate.

[0054] As can be seen from the above, compared with the prior art, the processing method of the buried capacitor packaging substrate provided in this application has the following advantages: ① This application innovatively provides the isolation groove 8 between each pair of adjacent signal lines 71, which is equivalent to increasing the physical distance between the two adjacent signal lines 71, thereby reducing parasitic capacitance and effectively improving signal crosstalk between the two adjacent signal lines 71. At the same time, the presence of the isolation groove 8 also interferes with the electromagnetic field distribution around the signal line 71, so that the transmission quality (signal integrity) of high-frequency signals is significantly improved, such as achieving: when the buried capacitor packaging substrate is at a working frequency above 10GHz, the signal crosstalk between the two adjacent signal lines 71 is less than 15dB. ② In the layer addition operation, this application adopts a positioning relationship of "the positioning copper pillar and the positioning hole slot 50 are inserted and matched". On the one hand, the dielectric layer 5 can be quickly and accurately stacked on the front side of the intermediate plate B. On the other hand, after lamination, a firm mechanical lock is formed between the dielectric layer 5 and the positioning structure 4. That is, a firm mechanical lock is formed between the dielectric layer 5 and the front side of the intermediate plate B. This can effectively prevent the layer misalignment problem caused by the difference in thermal expansion coefficients of the dielectric layer 5 and the capacitor layer 2, thereby significantly improving the alignment accuracy and stability of the overall structure of the first intermediate plate B2. ③ This application designs the grounding pad 72 and the heat dissipation pad 73 in the outer layer circuit 7 to be connected to the two inner layer circuits 3 respectively via connecting copper pillars 9. On the one hand, the connecting copper pillars 9 not only provide electrical connection but also have a good heat dissipation effect, improving the heat dissipation efficiency of the buried capacitor packaging substrate by more than 30%, significantly improving the working performance and reliability of the buried capacitor packaging substrate. On the other hand, the connecting copper pillars 9 connecting the grounding pad 72 and the inner layer circuit 3 can also promote a better signal return path and a more stable grounding, thereby improving the overall signal integrity (including noise level and timing stability). ④ The processing method provided by this application is reasonable, simple, and easy to operate and implement. Furthermore, since no additional outer shielding or heat dissipation accessories are required, production costs are significantly reduced.

[0055] Example 2:

[0056] This embodiment 2 provides an embedded capacitor packaging substrate, which is manufactured using the embedded capacitor packaging substrate processing method provided in embodiment 1 above.

[0057] Specifically, the structure of the buried capacitor packaging substrate is as follows: Please refer to the appendix. Figure 8 As shown, the work board includes a working board composed of a substrate 1 and a capacitor layer 2 stacked together, two sets of inner layer circuits 3 respectively disposed on the front and back sides of the work board, a positioning structure 4 disposed on the work board with one end fixedly embedded in the substrate 1 and the other end protruding from the capacitor layer 2, two sets of dielectric layers 5 respectively stacked on the two inner layer circuits 3, and two sets of outer layer circuits 7 respectively disposed on the two dielectric layers 5. The two sets of inner layer circuits 3 are electrically connected, and the positioning structure 4 and its corresponding dielectric layer 5 form a mechanical lock. One of the outer layer circuits 7 located beside the front side of the work board has multiple signal... The outer layer 7, located on the side of the back of the work board, has a heat dissipation pad 73, and the ground pad 72 and the heat dissipation pad 73 are respectively connected to the two inner layer 3 via connecting copper pillars 9. In addition, if the dielectric layer 5 located on the side of the front of the work board is defined as the first dielectric layer, isolation grooves 8 are respectively provided on the front of the first dielectric layer and in the area between each two adjacent signal lines 71, so as to achieve that when the buried capacitor package substrate is at an operating frequency of 10 GHz or higher, the signal crosstalk between two adjacent signal lines 71 is less than 15 dB.

[0058] As can be seen from the above, the embedded capacitor packaging substrate obtained in this embodiment 2 has the advantages of simple and reasonable structure, high alignment accuracy, high stability, good transmission quality of high frequency signals, and good heat dissipation performance, which well meet the market demand.

[0059] Finally, the prefixes "first," "second," etc. (such as first intermediate plate, second intermediate plate, etc.) in the component names of this invention patent specification, as well as the suffixes "A," "B," etc. (such as intermediate plate A, intermediate plate B, etc.) in the component names, are only for ease of description and are not intended to limit the scope of implementation of this invention patent.

[0060] Many specific details have been set forth in the foregoing description to provide a thorough understanding of the present invention. However, the above description is merely a preferred embodiment of the present invention, and the present invention can be implemented in many other ways different from those described herein. Therefore, the present invention is not limited to the specific embodiments disclosed above. Furthermore, any person skilled in the art can make many possible variations and modifications to the technical solutions of the present invention, or modify them into equivalent embodiments, using the methods and techniques disclosed above, without departing from the scope of the present invention. Any simple modifications, equivalent changes, and modifications made to the above embodiments based on the technical essence of the present invention, without departing from the content of the present invention, shall still fall within the protection scope of the present invention.

Claims

1. A method for processing a buried capacitor packaging substrate, characterized in that: include: A substrate (1) is provided, and a capacitor layer (2) is deposited on the front side of the substrate (1) to obtain a working board; The inner layer circuit is fabricated on the work board, so that the inner layer circuit (3) is fabricated on both the front and back sides of the work board, and a positioning structure (4) is formed on at least one of the front and back sides of the work board. A dielectric layer (5) and a copper foil layer (6) are stacked on the front and back sides of the work board after the inner layer circuit is fabricated, and then laminated to obtain the first intermediate board; wherein, the dielectric layer (5) and its corresponding positioning structure (4) form a mechanical lock; The obtained first intermediate board is fabricated with outer layer circuitry to create outer layer circuitry (7) on the two copper foil layers (6); wherein, one of the outer layer circuitry (7) located on the side of the front of the working board has multiple signal lines (71). An isolation groove (8) is provided on a dielectric layer (5) and exposed in the area between each two adjacent signal lines (71) to achieve that the signal crosstalk between two adjacent signal lines (71) is less than 15dB when the buried capacitor package substrate is operating at a frequency above 10GHz.

2. The processing method of the embedded capacitor packaging substrate according to claim 1, characterized in that: The positioning structure (4) is a positioning copper pillar with one end fixedly embedded in the substrate (1) and the other end protruding from the capacitor layer (2), and the positioning structure (4) is arranged on the edge area of ​​the working board. Correspondingly, a positioning hole (50) is provided on the edge region of the dielectric layer (5) to be inserted and engaged with the positioning structure (4).

3. The processing method of the embedded capacitor packaging substrate according to claim 2, characterized in that: After sequentially performing the following processes on the work board: laminating functional copper foil, drilling, copper plating, through-hole electroplating, inner layer circuit pattern transfer, pattern electroplating, film removal, and etching, two electrically connected inner layer circuits (3) and multiple positioning structures (4) are produced.

4. The processing method of the embedded capacitor packaging substrate according to claim 3, characterized in that: The height H of the positioning copper column satisfies the following relationship: H=Tc+Tr+Δd, where Tc is the thickness of the functional copper foil layer, Tr is the thickness of the capacitor layer (2), and Δd is the preset tolerance compensation value.

5. The processing method of the embedded capacitor packaging substrate according to claim 1, characterized in that: The method for fabricating the outer layer circuitry on the first intermediate board includes sequentially performing drilling, copper plating, through-hole plating, outer layer circuitry pattern transfer, pattern plating, film removal, and etching. Correspondingly, the outer layer circuit (7) located on the same side is electrically connected to the inner layer circuit (3).

6. The processing method of the embedded capacitor packaging substrate according to claim 5, characterized in that: An outer layer circuit (7) located on the side of the front of the working board also has a grounding pad (72), and an outer layer circuit (7) located on the side of the back of the working board has a heat dissipation pad (73). The grounding pad (72) and the heat dissipation pad (73) are respectively connected to the two inner layer circuits (3) through connecting copper pillars (9). The connecting copper pillars (9) are made by drilling, copper plating and through-hole electroplating of the first intermediate board in sequence.

7. The processing method of the embedded capacitor packaging substrate according to claim 1, characterized in that: The dielectric layer (5) located on the side of the front of the working board is defined as the first dielectric layer; The isolation grooves (8) with a depth of 20 to 100 μm and a width of 10 to 50 μm are respectively processed on the front side of the first dielectric layer and in the area between each two adjacent signal lines (71) by laser ablation process.

8. The processing method of the embedded capacitor packaging substrate according to claim 1, characterized in that: The isolation groove (8) is selectively filled with a thermally conductive material with a thermal conductivity of ≤0.5W / m·K.

9. The method for processing a buried capacitor packaging substrate according to claim 1, characterized in that: after the isolation groove (8) is formed, a second intermediate plate is obtained; The processing method for this embedded capacitor packaging substrate also includes: A water-soluble polymer is filled into the isolation groove (8), and then a solder resist layer (11) is printed on the preset positions on the front and back sides of the second intermediate plate. After the solder resist layer (11) is pre-cured, the water-soluble polymer is washed away with water, and then curing continues until the solder resist layer (11) is completely cured and formed.

10. A buried capacitor packaging substrate, characterized in that: It is manufactured using the processing method of any one of claims 1-9 for embedded capacitor packaging substrate.

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