一种基于FPGA的SPI时序控制方法及控制器
By using FPGA clock multiplication and three-channel independent timing control, combined with instruction awareness and intelligent write enable management, the timing control problem of SPI bus in rail transit system was solved, achieving efficient and reliable data transmission and breaking through the frequency bottleneck.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- CASCO SIGNAL LTD
- Filing Date
- 2025-10-23
- Publication Date
- 2026-07-17
AI Technical Summary
In rail transit systems, the timing control of the SPI bus relies on the clock accuracy of the main controller, which leads to substandard data transmission frequency, severe clock jitter and PCB delay issues, affecting the reliability and efficiency of data transmission.
An FPGA-based timing control method is adopted, which accurately compensates for PCB delay and clock jitter through clock multiplication and three-way independent timing control. Combined with instruction awareness and intelligent write enable management, the communication process is optimized, and closed-loop verification ensures the reliability of data writing.
This enables the SPI bus to operate stably at the highest nominal frequency of the slave device chip in complex hardware environments, improving data transmission efficiency and reliability while reducing hardware design complexity and cost.
Smart Images
Figure CN121478084B_ABST