Memory module and data processing method thereof

Abstract

The present disclosure provides a memory module and a data processing method thereof. The memory module comprises a memory controller and a memory; the memory comprises a plurality of memory banks; the memory controller comprises a control module, a first and a second input / output interface; when the capacity of the memory is less than or equal to a first threshold value, all the memory banks are connected to the control module through the first input / output interface and form a first memory group; when the capacity is greater than the first threshold value, part of the memory banks are connected to the control module through the first input / output interface and form the first memory group, and the other part of the memory banks are connected to the control module through the second input / output interface and form a second memory group; the control module is configured to map continuous memory addresses to different memory banks by using an address interleaving technology, and independently access memory cells in the first memory group and / or the second memory group according to a memory access task. The present disclosure can increase data access bandwidth, reduce memory access conflicts, and improve memory access efficiency.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, memory technology, and more specifically, to a memory module and a data processing method thereof. Background Technology

[0002] With the rapid development of deep learning and large-scale pre-trained models in the field of Artificial Intelligence (AI), the computing power demand for large-scale model chips is experiencing explosive growth. Against this backdrop, memory architecture based on Dynamic Random Access Memory (DRAM) has become a key component supporting the efficient operation of chips.

[0003] In AI chip design, the use of DRAM is a key element in balancing computing performance, energy efficiency, and cost. Because AI workloads are characterized by high parallelism, large memory footprint, and memory-intensive operations, a new DRAM memory access design is needed. Summary of the Invention

[0004] This disclosure provides a memory module, including a memory controller and a memory; The memory includes multiple memory banks, and each memory bank includes multiple memory units; The memory controller includes a control module, a first input / output interface, and a second input / output interface. When the capacity of the memory is less than or equal to a first threshold, all memory cells are connected to the control module through the first input / output interface to form a first memory group. When the capacity of the memory is greater than the first threshold, some memory cells are connected to the control module through the first input / output interface to form a first memory group, and another part of the memory cells are connected to the control module through the second input / output interface to form a second memory group. The control module is configured to: use address interleaving technology to map consecutive memory addresses to different memory banks, and independently access memory cells in the first memory group and / or the second memory group according to the memory access task; wherein, the memory access task includes: memory read task or memory write task.

[0005] This disclosure provides a data processing method for a memory module, including: The memory controller's control module uses address interleaving technology to map consecutive memory addresses to different memory banks; The control module of the memory controller independently accesses the memory cells in the first memory group and / or the second memory group according to the memory access task; wherein, the memory access task includes: memory read task or memory write task; The memory module includes a memory controller and a memory; the memory includes multiple memory banks, and each memory bank includes multiple memory cells. The memory controller includes a control module, a first input / output interface, and a second input / output interface. When the capacity of the memory is less than or equal to a first threshold, all memory cells are connected to the control module through the first input / output interface to form a first memory group. When the capacity of the memory is greater than the first threshold, some memory cells are connected to the control module through the first input / output interface to form the first memory group, and another part of the memory cells are connected to the control module through the second input / output interface to form a second memory group.

[0006] The memory module and data processing method disclosed herein include a memory module comprising multiple memory banks, each memory bank comprising multiple memory cells. The memory controller includes two sets of input / output interfaces to adapt to memories of different capacities. When the memory capacity is less than or equal to a first threshold, all memory banks are connected to the control module through the first input / output interface to form a first memory group. When the memory capacity is greater than the first threshold, some memory banks are connected to the control module through the first input / output interface to form the first memory group, and another portion of memory banks are connected to the control module through the second input / output interface to form a second memory group. Since the memory clock is slower than the host's logical clock, setting two sets of input / output interfaces can increase data access bandwidth and accelerate data transmission. By employing address interleaving technology to map consecutive memory addresses to different memory banks, and independently accessing memory cells in the first and / or second memory groups according to memory access tasks, contention for the same memory bank can be reduced, thereby reducing memory access conflicts and improving memory access efficiency.

[0007] Other features and advantages of this disclosure will be set forth in the following description, and will be apparent in part from the description, or may be learned by practicing the disclosure. Other advantages of this disclosure may be realized and obtained by means of the methods described in the description and the accompanying drawings. Attached Figure Description

[0008] The accompanying drawings are used to provide an understanding of the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure.

[0009] Figure 1 A schematic diagram of a memory module provided in an embodiment of this disclosure; Figure 2 A schematic diagram of the first and second storage groups provided in the embodiments of this disclosure; Figure 3aA schematic diagram illustrating the encoding of memory addresses when the memory provided in this embodiment is an 8-layer DRAM memory chip stacked package; Figure 3b A schematic diagram illustrating the encoding of memory addresses when the memory provided in this embodiment is a stacked package of 4-layer DRAM memory chips; Figure 3c This is a schematic diagram illustrating the encoding of memory addresses when the memory provided in this embodiment is a single-layer DRAM memory chip package; Figure 4 This is a schematic diagram of the structure of a control module provided in an embodiment of the present disclosure; Figure 5 A flowchart illustrating a data processing method for a memory module provided in an embodiment of this disclosure. Detailed Implementation

[0010] This disclosure describes several embodiments, but these descriptions are exemplary and not limiting, and it will be apparent to those skilled in the art that many more embodiments and implementations are possible within the scope of the embodiments described herein. Although many possible combinations of features are shown in the drawings and discussed in the detailed description, many other combinations of the disclosed features are also possible. Unless specifically limited, any feature or element of any embodiment may be used in combination with, or may replace, any feature or element of any other embodiment.

[0011] This disclosure includes and contemplates combinations of features and elements known to those skilled in the art. The embodiments, features, and elements disclosed in this disclosure may also be combined with any conventional features or elements to form unique inventive solutions. Any feature or element of any embodiment may also be combined with features or elements from other inventive solutions to form another unique inventive solution. Therefore, it should be understood that any feature shown and / or discussed in this disclosure may be implemented individually or in any suitable combination. Therefore, the embodiments are not limited except by the limitations imposed by the appended claims and their equivalents. Furthermore, various modifications and changes may be made within the scope of the appended claims.

[0012] Furthermore, in describing representative embodiments, the specification may have presented methods and / or processes as a specific sequence of steps. However, the method or process should not be limited to the specific order of steps described herein, to the extent that the method or process does not depend on the specific order of steps described herein. As will be understood by those skilled in the art, other sequences of steps are also possible. Therefore, the specific order of steps set forth in the specification should not be construed as a limitation of the claims. Moreover, the claims relating to the method and / or process should not be limited to the steps performed in the order written, and those skilled in the art will readily understand that these orders can be varied and still remain within the spirit and scope of the embodiments disclosed herein.

[0013] This disclosure provides a memory module. For example... Figure 1 As shown, a memory module includes a memory controller and a memory; The memory includes multiple memory banks, and each memory bank includes multiple memory units; The memory controller includes a control module, a first input / output interface, and a second input / output interface. When the capacity of the memory is less than or equal to a first threshold, all memory cells are connected to the control module through the first input / output interface to form a first memory group. When the capacity of the memory is greater than the first threshold, some memory cells are connected to the control module through the first input / output interface to form a first memory group, and another part of the memory cells are connected to the control module through the second input / output interface to form a second memory group. The control module is configured to: use address interleaving technology to map consecutive memory addresses to different memory banks, and independently access memory cells in the first memory group and / or the second memory group according to the memory access task; wherein, the memory access task includes: memory read task or memory write task.

[0014] The memory module provided in this disclosure includes multiple memory banks, each containing multiple memory cells. The memory controller includes two sets of input / output interfaces to adapt to memories of different capacities. When the memory capacity is less than or equal to a first threshold, all memory banks are connected to the control module through the first input / output interface to form a first memory group. When the memory capacity is greater than the first threshold, some memory banks are connected to the control module through the first input / output interface to form the first memory group, and another portion of memory banks are connected to the control module through the second input / output interface to form a second memory group. Since the memory clock is slower than the host's logical clock, setting two sets of input / output interfaces can increase the bandwidth for data access and accelerate data transmission. By employing address interleaving technology to map consecutive memory addresses to different memory banks, and independently accessing memory cells in the first and / or second memory groups according to memory access tasks, contention for the same memory bank can be reduced, thereby reducing memory access conflicts and improving memory access efficiency.

[0015] In one exemplary embodiment of this disclosure, the memory includes a memory packaged with multi-layer DRAM (Dynamic Random-Access Memory) storage dies stacked together, or a memory packaged with a single-layer DRAM storage die. The first threshold is the capacity of a single-layer dynamic random access memory (DRAM) storage chip.

[0016] Figure 2 A schematic diagram of a first storage group and a second storage group is shown. (See diagram below.) Figure 2 As shown, the memory includes N banks. The first N / 2 banks form the first storage group, namely Bank(0) to Bank(N / 2-1); the last N / 2 banks form the second storage group, namely Bank(N / 2) to Bank(N-1). For example, when N=32, the first 16 banks (Bank0, Bank1, ..., Bank15) form the first storage group, and the last 16 banks (Bank16, Bank17, ..., Bank31) form the second storage group.

[0017] In an exemplary embodiment of this disclosure, the memory address of the memory includes the following four parts from high to low bits: row address, column address, memory bank address, and cell address; Wherein, the number of bits 'a' occupied by the unit address portion of the memory address is determined according to the smallest granularity 'b' of the data block accessed in the memory: The unit of the smallest granularity is the byte. When the memory includes a first memory group and a second memory group, the highest bit of the memory address portion is also used to distinguish between the first memory group and the second memory group.

[0018] Figure 3a This diagram illustrates the memory address encoding of a multi-layer (8-layer) DRAM (Dynamic Random-Access Memory) memory chip (die) stacked package. The memory is divided into 32 memory banks. The memory controller includes two sets of input / output interfaces; the first 16 memory banks are connected to the first set of input / output interfaces, and the last 16 memory banks are connected to the second set of input / output interfaces. The 8-layer memory has a capacity of 4GB, and the memory address encoding is 32 bits. The lowest 5 bits (bit[4]~bit[0]) are the unit address part, indicating that the smallest granularity of the data block accessed in memory is 256 bits (32 bytes); bits[9]~bit[5] are the bank address part, indicating the offset address of 32 banks, where bit[9] is also used to distinguish between the first and second banks. The bank addresses of the 16 banks in the first bank are 00000 to 01111, and the bank addresses of the 16 banks in the second bank are 10000 to 11111; bits

[15] ~bit

[10] are the column address part, indicating that each row of each bank includes 64 columns, which corresponds to 64 column addresses; the highest 16 bits (bit

[31] ~bit

[16] ) are the row address part, indicating that each bank includes (65536) rows, that is, 65536 row addresses.

[0019] Figure 3bThis diagram illustrates the memory address encoding of a memory device that is a multi-layer (4-layer) DRAM memory chip (die) stacked package. The memory is divided into 32 memory banks. The memory controller includes two sets of input / output interfaces. The first 16 memory banks are connected to the first set of input / output interfaces, and the last 16 memory banks are connected to the second set of input / output interfaces. The 4-layer memory has a capacity of 2GB, and the memory address encoding is 31 bits. The lowest 5 bits (bit[4]~bit[0]) are the unit address part, indicating that the smallest granularity of the data block accessed in memory is 256 bits (32 bytes); bits[9]~bit[5] are the bank address part, indicating the offset address of 32 banks, where bit[9] is also used to distinguish between the first and second banks. The bank addresses of the 16 banks in the first bank are 00000 to 01111, and the bank addresses of the 16 banks in the second bank are 10000 to 11111; bits

[15] ~bit

[10] are the column address part, indicating that each row of each bank includes 64 columns, which corresponds to 64 column addresses; the highest 15 bits (bit

[30] ~bit

[16] ) are the row address part, indicating that each bank includes (32768) rows, that is, 32768 row addresses.

[0020] Figure 3c A schematic diagram of the memory address encoding of a memory packaged as a single-layer DRAM memory chip (Die) is shown. The memory is divided into 16 memory banks. The memory controller includes two sets of input / output interfaces. The second set of input / output interfaces is disabled, and the 16 memory banks are connected to the first set of input / output interfaces. The capacity of the single-layer memory is 0.5GB, and the memory address encoding is 29 bits in total. Among them, the lowest 5 bits (bit[4]~bit[0]) are the cell address part, indicating that the smallest granularity of the data block accessed by the memory is 256 bits (32 bytes); bits[8]~bit[5] are the bank address part, indicating the offset address of the 16 banks. The 16 banks are the first storage group, and the bank address is from 0000 to 1111; bits

[14] ~bit[9] are the column address part, indicating that each row of each bank includes 64 columns, that is, corresponding to 64 column addresses; the highest 15 bits (bit

[28] ~bit

[15] are the row address part, indicating that each bank includes (16384) rows, that is, 16384 row addresses.

[0021] against Figure 3a and Figure 3bThe memory has a minimum data block size of 256 bits (32 bytes) for memory access. Address interleaving is based on 32 DRAM banks. The first 16 banks form the first memory bank, and the data blocks of the first memory bank form a 4Kbit (0.5K byte) first data block group. The last 16 banks form the second memory bank, and the data blocks of the second memory bank form a 4Kbit (0.5K byte) second data block group. Each memory access is in 4Kbit (0.5K byte) units, that is, memory read and write are aligned to 4Kbit (0.5K byte). For a 4Kbit*8 DRAM read task, the first memory bank and the second memory bank alternately execute the 4Kbit DRAM read task, and each memory bank is executed 4 times.

[0022] against Figure 3c The memory has a minimum data block size of 256 bits (32 bytes) for memory access. Address interleaving is based on 16 DRAM banks. The 16 banks form the first memory group. The data blocks of the first memory group form a 4Kbit (0.5K byte) first data block group. Each memory access is based on a 4Kbit (0.5K byte) unit. That is, memory read and write are aligned to 4Kbit (0.5K byte). Therefore, for a 4Kbit*8 DRAM read task, the first memory group will execute 8 consecutive 4Kbit DRAM read tasks.

[0023] In an exemplary embodiment of this disclosure, independently accessing storage cells in a first storage group and / or a second storage group according to a memory access task includes: When a memory access task involves either reading a first data block of K bytes consecutively from a destination address in memory or writing a first data block of K bytes to a destination address in memory, the number of accesses n is determined. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. If the memory includes a first storage group and a second storage group, the storage cells in the first and second storage groups are accessed alternately according to the destination address corresponding to each second data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to each second data block. When n=1, if the memory includes a first storage group and a second storage group, the storage cells in either the first or second storage group are accessed according to the destination address corresponding to the first data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to the first data block. Where P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P.

[0024] In one example of this disclosure, assuming the data width of each input / output interface is 4096 bits (4Kbit), then P = 0.5. A single memory group access is aligned to 4Kbit. When a memory access transaction requires accessing a data block of size 4Kbit * 8, it can be completed through 8 4Kbit accesses. Assuming the target memory group is determined to be the first memory group based on the starting address of the data block to be accessed, the access sequence is as follows: First access: 1st row, 1st column of all memory blocks in the first memory group; Second access: 1st row, 1st column of all memory blocks in the second memory group; Third access: 1st row, 2nd column of all memory blocks in the first memory group; Fourth access: 1st row, 2nd column of all memory blocks in the second memory group; Fifth access: 1st row, 3rd column of all memory blocks in the first memory group; Sixth access: 1st row, 3rd column of all memory blocks in the second memory group; Seventh access: 1st row, 4th column of all memory blocks in the first memory group; Eighth access: 1st row, 4th column of all memory blocks in the second memory group. Assuming the target storage group is determined to be the second storage group based on the starting address of the data block to be accessed, the process is as follows: first access: the first row and first column of all storage blocks in the second storage group; second access: the first row and second column of all storage blocks in the first storage group; third access: the first row and second column of all storage blocks in the second storage group; fourth access: the first row and third column of all storage blocks in the first storage group; fifth access: the first row and third column of all storage blocks in the second storage group; sixth access: the first row and fourth column of all storage blocks in the first storage group; seventh access: the first row and fourth column of all storage blocks in the second storage group; and eighth access: the first row and fifth column of all storage blocks in the first storage group.

[0025] In one exemplary embodiment of this disclosure, such as Figure 4 As shown, the control module includes: a read task grouping module, a first read task processing module, and a second read task processing module; The read task grouping module is configured to determine the number of reads, n, when a memory access task reads the first data block of K bytes consecutively from the destination address of memory. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. The memory access task is split into n read data subtasks, each reading one of the n second data blocks. If the memory only includes the first storage group, the n read data subtasks are consecutively assigned to the first read task processing module. If the memory includes both the first and second storage groups, the n read data subtasks are alternately assigned to the first and second read task processing modules. When n=1, if the memory only includes the first storage group, the memory access task is assigned to the first read task processing module. If the memory includes both the first and second storage groups, the memory access task is assigned to either the first or second read task processing module based on its destination address. Here, P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P. The first read task processing module is configured to: split the read data subtask or memory access task into m unit tasks, access the corresponding memory bank in the first memory group in parallel according to the destination address of the m unit tasks, and after reading the unit data of the m memory banks, output the m units of data in parallel to the read task grouping module through the first input / output interface. The second read task processing module is configured to: split the read data subtask or memory access task into m unit tasks, access the corresponding memory bank in the second memory group in parallel according to the destination address of the m unit tasks, and after reading the unit data of the m memory banks, output the m units of data in parallel to the read task grouping module through the first input / output interface.

[0026] In one exemplary embodiment of this disclosure, such as Figure 4 As shown, the control module further includes: a write task grouping module, a first write task processing module, and a second write task processing module; The write task grouping module is configured to determine the number of writes, n, when a memory access task involves writing a first data block of K bytes to the destination address of memory. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. The memory access task is split into n write data subtasks, each corresponding to one of the n second data blocks. If the memory only includes the first memory group, the n write data subtasks are consecutively assigned to the first write task processing module. If the memory includes both the first and second memory groups, the n write data subtasks are alternately assigned to the first and second write task processing modules. When n=1, if the memory only includes the first memory group, the memory access task is assigned to the first write task processing module. If the memory includes both the first and second memory groups, the memory access task is assigned to either the first or second write task processing module based on its destination address. Here, P is the amount of data accessed in a single access to all memory banks of a memory group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P. The first write task processing module is configured to: divide the write data subtask or memory access task into m unit tasks, and write the data of the m unit tasks in parallel to the storage units of the m memory banks through the first input / output interface according to the destination address of the m unit tasks; The second write task processing module is configured to: split the write data subtask or memory access task into m unit tasks, and write the data of the m unit tasks in parallel to the storage units of the m memory banks through the second input / output interface according to the destination address of the m unit tasks.

[0027] This disclosure provides a data processing method for a memory module, such as... Figure 5 As shown, the method includes: In step S10, the control module of the memory controller uses address interleaving technology to map consecutive memory addresses to different memory banks; Step S20: The control module of the memory controller independently accesses the memory cells in the first memory group and / or the second memory group according to the memory access task; wherein, the memory access task includes: memory read task or memory write task; The memory module includes a memory controller and a memory; the memory includes multiple memory banks, and each memory bank includes multiple memory cells. The memory controller includes a control module, a first input / output interface, and a second input / output interface. When the capacity of the memory is less than or equal to a first threshold, all memory cells are connected to the control module through the first input / output interface to form a first memory group. When the capacity of the memory is greater than the first threshold, some memory cells are connected to the control module through the first input / output interface to form the first memory group, and another part of the memory cells are connected to the control module through the second input / output interface to form a second memory group.

[0028] The memory module provided in this disclosure includes multiple memory banks, each containing multiple memory cells. The memory controller includes two sets of input / output interfaces to adapt to memories of different capacities. When the memory capacity is less than or equal to a first threshold, all memory banks are connected to the control module through the first input / output interface to form a first memory group. When the memory capacity is greater than the first threshold, some memory banks are connected to the control module through the first input / output interface to form the first memory group, and another portion of memory banks are connected to the control module through the second input / output interface to form a second memory group. Since the memory clock is slower than the host's logical clock, setting two sets of input / output interfaces can increase the bandwidth for data access and accelerate data transmission. By employing address interleaving technology to map consecutive memory addresses to different memory banks, and independently accessing memory cells in the first and / or second memory groups according to memory access tasks, contention for the same memory bank can be reduced, thereby reducing memory access conflicts and improving memory access efficiency.

[0029] In one exemplary embodiment of this disclosure, the memory includes a memory packaged with multi-layer DRAM (Dynamic Random-Access Memory) storage dies stacked together, or a memory packaged with a single-layer DRAM storage die. The first threshold is the capacity of a single-layer dynamic random access memory (DRAM) storage chip.

[0030] In an exemplary embodiment of this disclosure, the memory address of the memory includes the following four parts from high to low bits: row address, column address, memory bank address, and cell address; Wherein, the number of bits 'a' occupied by the unit address portion of the memory address is determined according to the smallest granularity 'b' of the data block accessed in the memory: The unit of the smallest granularity is the byte. When the memory includes a first memory group and a second memory group, the highest bit of the memory address portion is also used to distinguish between the first memory group and the second memory group.

[0031] In an exemplary embodiment of this disclosure, the control module of the memory controller independently accesses memory cells in a first memory group and / or a second memory group according to a memory access task, including: When a memory access task involves either reading a first data block of K bytes consecutively from a destination address in memory or writing a first data block of K bytes to a destination address in memory, the memory controller's control module determines the access count n. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. If the memory includes a first storage group and a second storage group, the storage cells in the first and second storage groups are accessed alternately according to the destination address corresponding to each second data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to each second data block. When n=1, if the memory includes a first storage group and a second storage group, the storage cells in either the first or second storage group are accessed according to the destination address corresponding to the first data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to the first data block. Where P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of memory bodies included in a memory group, and K is an integer multiple of P. In an exemplary embodiment of this disclosure, the control module includes: a read task grouping module, a first read task processing module, and a second read task processing module; The control module of the memory controller independently accesses memory cells in the first memory group and / or the second memory group according to the memory access task, including: When a memory access task involves continuously reading K bytes from the destination address of memory, the read task grouping module determines the number of reads, n. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. The memory access task is split into n read data subtasks, each reading one of the n second data blocks. If the memory only includes the first storage group, the n read data subtasks are consecutively assigned to the first read task processing module. If the memory includes both the first and second storage groups, the n read data subtasks are alternately assigned to the first and second read task processing modules. When n=1, if the memory only includes the first storage group, the memory access task is assigned to the first read task processing module. If the memory includes both the first and second storage groups, the memory access task is assigned to either the first or second read task processing module based on its destination address. Here, P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P. The first read task processing module divides the read data subtask or memory access task into m unit tasks. Based on the destination addresses of the m unit tasks, it accesses the corresponding memory banks in the first memory group in parallel. After reading the unit data of the m memory banks, it outputs the m units of data to the read task grouping module in parallel through the first input / output interface. The second read task processing module divides the read data subtask or memory access task into m unit tasks. Based on the destination addresses of the m unit tasks, it accesses the corresponding memory banks in the second memory group in parallel. After reading the unit data of the m memory banks, it outputs the m units of data to the read task grouping module in parallel through the first input / output interface.

[0032] In an exemplary embodiment of this disclosure, the control module further includes: a write task grouping module, a first write task processing module, and a second write task processing module; The control module of the memory controller independently accesses memory cells in the first memory group and / or the second memory group according to the memory access task, including: When the write task grouping module writes a memory access task that involves writing a first data block of K bytes to the destination address of memory, it determines the number of writes, n. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. The memory access task is split into n write data subtasks, each corresponding to one of the n second data blocks. If the memory only includes the first memory group, the n write data subtasks are consecutively assigned to the first write task processing module. If the memory includes both the first and second memory groups, the n write data subtasks are alternately assigned to the first and second write task processing modules. When n=1, if the memory only includes the first memory group, the memory access task is assigned to the first write task processing module. If the memory includes both the first and second memory groups, the memory access task is assigned to either the first or second write task processing module based on its destination address. Here, P is the amount of data accessed in a single access to all memory banks of a memory group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P. The first write task processing module divides the write data subtask or memory access task into m unit tasks, and writes the data of the m unit tasks in parallel to the storage units of the m memory banks through the first input / output interface according to the destination address of the m unit tasks; the second write task processing module divides the write data subtask or memory access task into m unit tasks, and writes the data of the m unit tasks in parallel to the storage units of the m memory banks through the second input / output interface according to the destination address of the m unit tasks.

[0033] It will be understood by those skilled in the art that all or some of the steps, systems, or apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all components may be implemented as software executed by a processor, such as a digital signal processor or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software may be distributed on a computer-readable medium, which may include computer storage media (or non-transitory media) and communication media (or transient media). As is known to those skilled in the art, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storing information (such as computer-readable instructions, data structures, program modules, or other data). Computer storage media include, but are not limited to, RAM, ROM, EEPROM, flash memory or other memory technologies, CD-ROM, digital versatile disc (DVD) or other optical disc storage, magnetic cartridges, magnetic tape, disk storage or other magnetic storage devices, or any other medium that can be used to store desired information and can be accessed by a computer. Furthermore, it is well known to those skilled in the art that communication media typically contain computer-readable instructions, data structures, program modules, or other data in modulated data signals such as carrier waves or other transmission mechanisms, and may include any information delivery medium.

[0034] Furthermore, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined with "first," "second," etc., may explicitly or implicitly include at least one of that feature. In the description of this disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise explicitly specified.

[0035] In the description of this specification, the references to terms such as "one embodiment," "some embodiments," "example," "specific example," or "some examples," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this disclosure. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in any suitable manner in one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

Claims

1. A memory module, comprising a memory controller and a memory; The memory includes multiple memory banks, and each memory bank includes multiple memory units; The memory controller includes a control module, a first input / output interface, and a second input / output interface. When the capacity of the memory is less than or equal to a first threshold, all memory cells are connected to the control module through the first input / output interface to form a first memory group. When the capacity of the memory is greater than the first threshold, some memory cells are connected to the control module through the first input / output interface to form a first memory group, and another part of the memory cells are connected to the control module through the second input / output interface to form a second memory group. The control module is configured to: map consecutive memory addresses to different memory banks using address interleaving technology, and independently access memory cells in the first memory group and / or the second memory group according to the memory access task; wherein, The memory access task includes a memory read task or a memory write task; the memory address of the memory includes the following four parts from the high bit to the low bit: row address, column address, bank address and cell address; when the memory includes a first bank and a second bank, the highest bit of the bank address part is also used to distinguish between the first bank and the second bank.

2. The memory module according to claim 1, characterized in that: The number of bits 'a' in the unit address portion of the memory address is determined based on the smallest granularity 'b' of the data block accessed from the memory: The unit of the smallest granularity is the byte.

3. The memory module according to claim 1, characterized in that: The memory includes a memory packaged with stacked multilayer dynamic random access memory (DRAM) chips, or a memory packaged with a single-layer DRAM chip. The first threshold is the capacity of a single-layer DRAM memory chip.

4. The memory module according to claim 2, characterized in that: Independently accessing memory cells in the first and / or second memory groups according to a memory access task includes: When a memory access task involves either reading a first data block of K bytes consecutively from a destination address in memory or writing a first data block of K bytes to a destination address in memory, the number of accesses n is determined. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. If the memory includes a first storage group and a second storage group, the storage cells in the first and second storage groups are accessed alternately according to the destination address corresponding to each second data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to each second data block. When n=1, if the memory includes a first storage group and a second storage group, the storage cells in either the first or second storage group are accessed according to the destination address corresponding to the first data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to the first data block. Where P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P.

5. The memory module according to claim 2, characterized in that: The control module includes: a read task grouping module, a first read task processing module, and a second read task processing module; The read task grouping module is configured to determine the number of reads, n, when a memory access task reads the first data block of K bytes consecutively from the destination address of memory. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. The memory access task is split into n read data subtasks, each reading one of the n second data blocks. If the memory only includes the first storage group, the n read data subtasks are consecutively assigned to the first read task processing module. If the memory includes both the first and second storage groups, the n read data subtasks are alternately assigned to the first and second read task processing modules. When n=1, if the memory only includes the first storage group, the memory access task is assigned to the first read task processing module. If the memory includes both the first and second storage groups, the memory access task is assigned to either the first or second read task processing module based on its destination address. Here, P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P. The first read task processing module is configured to: split the read data subtask or memory access task into m unit tasks, access the corresponding memory bank in the first memory group in parallel according to the destination address of the m unit tasks, and after reading the unit data of the m memory banks, output the m units of data in parallel to the read task grouping module through the first input / output interface. The second read task processing module is configured to: split the read data subtask or memory access task into m unit tasks, access the corresponding memory bank in the second memory group in parallel according to the destination address of the m unit tasks, and after reading the unit data of the m memory banks, output the m units of data in parallel to the read task grouping module through the first input / output interface.

6. The memory module according to claim 5, characterized in that: The control module further includes: a write task grouping module, a first write task processing module, and a second write task processing module; The write task grouping module is configured to determine the number of writes, n, when a memory access task involves writing a first data block of K bytes to the destination address of memory. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. The memory access task is split into n write data subtasks, each corresponding to one of the n second data blocks. If the memory only includes the first memory group, the n write data subtasks are consecutively assigned to the first write task processing module. If the memory includes both the first and second memory groups, the n write data subtasks are alternately assigned to the first and second write task processing modules. When n=1, if the memory only includes the first memory group, the memory access task is assigned to the first write task processing module. If the memory includes both the first and second memory groups, the memory access task is assigned to either the first or second write task processing module based on its destination address. Here, P is the amount of data accessed in a single access to all memory banks of a memory group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P. The first write task processing module is configured to: divide the write data subtask or memory access task into m unit tasks, and write the data of the m unit tasks in parallel to the storage units of the m memory banks through the first input / output interface according to the destination address of the m unit tasks; The second write task processing module is configured to: split the write data subtask or memory access task into m unit tasks, and write the data of the m unit tasks in parallel to the storage units of the m memory banks through the second input / output interface according to the destination address of the m unit tasks.

7. A data processing method for a memory module, comprising: The memory controller's control module uses address interleaving technology to map consecutive memory addresses to different memory banks. The memory address, from most significant bit to least significant bit, consists of four parts: row address, column address, memory bank address, and cell address. When the memory includes a first memory bank and a second memory bank, the most significant bit of the memory bank address is also used to distinguish between the first memory bank and the second memory bank. The control module of the memory controller independently accesses the memory cells in the first memory group and / or the second memory group according to the memory access task; wherein, the memory access task includes: memory read task or memory write task; The memory module includes a memory controller and a memory; the memory includes multiple memory banks, and each memory bank includes multiple memory cells. The memory controller includes a control module, a first input / output interface, and a second input / output interface. When the capacity of the memory is less than or equal to a first threshold, all memory cells are connected to the control module through the first input / output interface to form a first memory group. When the capacity of the memory is greater than the first threshold, some memory cells are connected to the control module through the first input / output interface to form the first memory group, and another part of the memory cells are connected to the control module through the second input / output interface to form a second memory group.

8. The method according to claim 7, characterized in that: The number of bits 'a' in the unit address portion of the memory address is determined based on the smallest granularity 'b' of the data block accessed from the memory: The unit of the smallest granularity is the byte.

9. The method according to claim 8, characterized in that: The control module of the memory controller independently accesses memory cells in the first memory group and / or the second memory group according to the memory access task, including: When a memory access task involves either reading a first data block of K bytes consecutively from a destination address in memory or writing a first data block of K bytes to a destination address in memory, the memory controller's control module determines the access count n. When n>1, the first data block is split into n second data blocks, each containing P bytes of data with consecutive addresses. If the memory includes a first storage group and a second storage group, the storage cells in the first and second storage groups are accessed alternately according to the destination address corresponding to each second data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to each second data block. When n=1, if the memory includes a first storage group and a second storage group, the storage cells in either the first or second storage group are accessed according to the destination address corresponding to the first data block. If the memory only includes the first storage group, the storage cells in the first storage group are accessed according to the destination address corresponding to the first data block. Where P is the amount of data accessed in a single access to all storage banks of a storage group. b is the smallest granularity of the data block accessed in memory, m is the total number of storage units included in a storage group, and K is an integer multiple of P.

10. The method according to claim 7, characterized in that: The memory includes a memory packaged with stacked multilayer dynamic random access memory (DRAM) chips, or a memory packaged with a single-layer DRAM chip. The first threshold is the capacity of a single-layer DRAM memory chip.

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