FPGA-based CANFD communication expansion system with embedded RISCV processor

Abstract

The application provides a CANFD communication expansion system based on an FPGA and an embedded RISCV processor, which comprises an external CAN / CANFD isolation interface configured to receive a data frame of an external device; a first CANFD IP core connected with the external CAN / CANFD isolation interface, configured to receive the data frame, perform analysis and CRC check, and write first data in the data frame into a corresponding process FIFO; a channel mapping module configured to determine a first logical channel corresponding to the external CAN / CANFD isolation interface; a protocol conversion module configured to convert the first data of the first logical channel into second data; an arbitration switching module configured to determine the state of the first logical channel and a second logical channel redundant to the first logical channel, determine a target logical channel for transmitting the second data, and store the second data in the process FIFO; and a second CANFD IP core connected with an internal CAN / CANFD isolation interface, configured to read the second data from the process FIFO and transmit the second data through the internal CAN / CANFD isolation interface.

Description

Technical Field

[0001] This application relates to the field of electronic digital data processing technology, and in particular to a CANFD communication extension system and system based on FPGA with embedded RISCV processor. Background Technology

[0002] With the rapid growth in demand and expansion of business in the rail transit industry, various control systems, such as braking, traction, and signal control, require a large amount of data transmission between and within systems, including data such as speed, temperature, and pressure. The traditional 8-byte data frame of CAN can no longer meet bandwidth requirements. CANFD communication, which can transmit more information per frame and has a higher transmission rate, is increasingly popular in the industry, leading to the development of many CANFD communication and protocol conversion devices. Among these, CANFD relay or communication extension devices serve as important nodes for cross-system and cross-signal domain communication, playing roles such as communication rate conversion, protocol conversion, and signal conditioning and enhancement. However, the CANFD relay or communication extension devices commonly used in the rail transit industry currently suffer from the following problems:

[0003] Poor configurability and reusability; most are non-standard products that need to be developed separately according to the specific needs of different projects, resulting in poor flexibility.

[0004] Insufficient real-time performance or excessive cost. Mainstream CANFD communication solutions can be basically divided into two types: low-end MCU + SPI CANFD chip and high-end MCU with built-in CANFD controller. Although the former solves the problem of low-end MCUs accessing CANFD networks, the low processor performance and SPI interface relay cause a large delay in CANFD communication, resulting in insufficient real-time performance. Although the latter has a built-in CANFD controller to reduce bus communication delay to some extent, various data forwarding and protocol conversion logics still need to be operated in conjunction with the chip's DMA controller and logic design. Essentially, it is still a serial execution, and its performance is limited by the chip's real-time logic operation volume. Moreover, the introduction of high-end MCUs generally results in higher costs.

[0005] The degree of self-reliance and control is not high. In mainstream product solutions, whether it is a standalone SPI to CANFD controller chip or an MCU chip with a built-in CANFD controller, most of them are foreign products. Troubleshooting and problem localization are not timely and effective, and the supply of products is easily affected or restricted by various unstable factors.

[0006] Cross-platform porting is quite challenging. Different MCUs have different development environments, CANFD controller register configurations, or SPI-to-CANFD chip configuration logics. Even the most basic CANFD baud rate parameter configuration methods differ, leading to increased development time during new design development or migration of existing designs.

[0007] The isolation level of each CANFD trunk or expansion interface is insufficient, and the logical isolation of the communication interfaces of some products is poor. Simple forwarding without flow control and communication monitoring can easily lead to problems such as mutual interference between channels and communication blockage. Some products even lack basic physical isolation between different channels, causing the failure of one interface to affect other channels and even the failure of the entire trunk or expansion system. Summary of the Invention

[0008] The purpose of this application is to address the deficiencies in the existing technology by providing a CANFD communication extension system and system based on FPGA and embedded RISCV processor, so as to solve the problems existing in the prior art.

[0009] To achieve the above objectives, this application provides a CANFD communication extension system based on an FPGA and an embedded RISC-V processor, the method comprising:

[0010] External CAN / CANFD isolated interface for receiving data frames from external devices;

[0011] The first CANFD IP core, which is connected to the external CAN / CANFD isolation interface, receives the data frame, performs parsing and CRC verification, and writes the first data in the data frame into the corresponding process FIFO.

[0012] The channel mapping module determines the first logical channel corresponding to the external CAN / CANFD isolation interface;

[0013] The protocol conversion module converts the first data of the first logical channel into the second data.

[0014] The arbitration switching module determines the status of the first logical channel and its redundant second logical channel, determines the target logical channel for transmitting the second data, and stores the second data in the process FIFO.

[0015] The second CANFD IP core, connected to the internal CAN / CANFD isolation interface, reads the second data from the process FIFO and sends it through the internal CAN / CANFD isolation interface.

[0016] In one possible implementation, during the system initialization and configuration phase, when the configuration information is loaded, the RISC V core obtains system configuration parameters through an external maintenance interface. These configuration parameters include channel mapping relationships, protocol conversion rules, arbitration switching strategies, and operating parameters for each CANFD IP core. The channel mapping relationships define the correspondence between physical interfaces and logical channels. The protocol conversion rules include channels requiring mutual conversion between CAN and CANFD, as well as data packet assembly / disassembly rules. The arbitration switching strategy includes monitoring objects for redundant channels, fault judgment conditions, and switching logic. The operating parameters for each CANFD IP core include baud rate, receive filter ID, and frame type.

[0017] The RISCV core writes configuration parameters into the shared memory area on the FPGA logic side through the MCU interaction module. The shared memory area refers to a dual-port RAM generated by logic resources inside the FPGA. Port A of the dual-port RAM is connected to the APB bus of the RISCV core, and Port B of the dual-port RAM is connected to the logic circuit on the FPGA side. The logic circuit includes the control state machine in the MCU interaction module.

[0018] The FPGA's channel mapping module, protocol conversion module, arbitration switching module, status monitoring module, and each CANFDIP core read their respective parameters from the shared memory area and perform their own configurations.

[0019] The status monitoring module monitors the bus status of all interfaces.

[0020] In one possible implementation, the external CAN / CANFD isolation interface and the CANFD IP core correspond one-to-one;

[0021] When the external CAN / CANFD isolation interface receives a data frame from an external device, the CANFD IP core corresponding to the external CAN / CANFD isolation interface receives the data frame.

[0022] In one possible implementation, the channel mapping module queries and determines the logical channel corresponding to the external CAN / CANFD isolation interface according to the channel mapping relationship, and determines the first logical channel as the corresponding logical channel.

[0023] In one possible implementation, the configuration rules include the correspondence between the external CAN / CANFD isolation interface and the internal CAN / CANFD isolation interface, and include the conversion relationship between CAN frames and CANFD frames;

[0024] The protocol conversion module performs frame forced conversion, data packet assembly, and baud rate switching according to the configuration rules. The frame forced conversion includes converting standard CAN frames into CANFD frame format. The data packet assembly includes concatenating data segments from multiple consecutively received CAN frames into a single CANFD frame. The baud rate switching includes adjusting the baud rate of the frame to the rate of the corresponding internal CAN / CANFD isolation interface.

[0025] In one possible implementation, the system further includes: a status monitoring module;

[0026] The status monitoring module feeds back the status of the redundant channels to the arbitration switching module; the status includes whether the received frame timed out and whether the bus error count exceeded the limit.

[0027] The arbitration switching module determines the target logical channel for transmitting the second data based on the status of the first and second logical channels, which are redundant channels, and a preset strategy; the preset strategy includes a default trusted channel.

[0028] In one possible implementation, the status monitoring module monitors the bus error status, bus load rate, error frame count, response frame delay statistics, and the timestamp and reason of the most recent switching event of the arbitration switching module for each first CANFD IP core and each second CANFD IP core.

[0029] When a bus error is detected and the system enters an offline state, a fast reset or slow reset is automatically triggered on the corresponding first CANFD IP core and / or second CANFD IP core.

[0030] The bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module are updated to the shared memory area through the MCU interaction module so that the RISC-CV core can read them.

[0031] In one possible implementation, the RISCV core periodically reads bus error faults, bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module from the shared memory area through the MCU interaction module, and sends them to the host computer through the maintenance interface; or dynamically adjusts the switching strategy of the arbitration switching module or the parameters of the protocol conversion module through the MCU interaction module.

[0032] In one possible implementation, the RISCV core analyzes bus load rate, error frame count, response frame delay statistics, and the timestamp and cause of the most recent switching event of the arbitration switching module according to a preset algorithm to determine a new switching strategy or dynamically adjust protocol conversion parameters. The determination of the new switching strategy includes fault determination delay and switching hysteresis. The fault determination delay is the time for determining bus delay anomalies. The switching hysteresis includes introducing a back-switch condition: when the quality of the backup channel is better than the primary channel for more than a preset duration, the primary channel is switched back to. The dynamic adjustment of protocol conversion parameters includes updating the number of packets from CAN to CANFD to decrease under congested conditions and increasing the number of packets when the link is stable and high throughput is required.

[0033] The CANFD communication extension system based on FPGA and embedded RI SCV processor provided in this application has the following technical effects:

[0034] 1. High flexibility and strong configurability; configuration parameters can be easily modified to achieve board reuse according to different project requirements. Supports expansion of multiple communication structures and supports the design of redundant communication mechanisms related to functional safety in the rail transit field.

[0035] 2. Low communication latency and low cost. The system architecture design ensures that only a single ordinary FPGA chip is needed to achieve the high-speed, low-latency communication that previously required high-end MCUs or complex chip combinations, significantly reducing costs. The FPGA handles real-time demanding functions such as CAN / CANFD communication forwarding. The FPGA's parallel processing capabilities ensure that each communication interface operates independently during forwarding, guaranteeing real-time performance. The MCU implemented with the RISC core handles frequently modified, less real-time-critical communication configuration and status maintenance functions. The clear division of labor between the FPGA and the RISC core ensures rich functionality while maintaining high real-time performance.

[0036] 3. High degree of autonomy and controllability. It adopts independently controllable CANFD IP core, R ISCV core and self-developed IDE development environment. Different configuration modifications can be made according to project and development needs. It gets rid of dependence on various CANFD controllers and MCU cores and is not affected by various external unstable factors and technical bottlenecks.

[0037] 4. Simplified cross-platform portability. The underlying key IP cores are designed using RTL code, without complex IP core nesting. This significantly reduces the difficulty of porting the technical solution to mainstream FPGA chips on the market, and avoids problems such as driver redevelopment and simulation caused by differences in tools and IP cores of different FPGA chips, greatly shortening development time. At the same time, because the new design can flexibly configure the instruction set, data / instruction cache space, CAN / CANFD data buffer space, etc. of the entire RISCCV core, it can achieve flexible adaptability design between FPGAs with different resources.

[0038] The different interfaces have a high degree of isolation and high fault tolerance. The communication expansion board not only achieves physical isolation between internal and external channels (including level isolation, etc.), but also ensures timely bus exit and recording of abnormal information when internal or external buses malfunction through intermediate plug-in arbitration switching, process FIFO, or status monitoring, thus avoiding the impact of a single bus node on the entire communication link. Attached Figure Description

[0039] Figure 1 This application provides a schematic diagram of the CANFD communication extension system architecture based on an FPGA and an embedded R ISCV processor, as shown in the embodiments of this application.

[0040] Figure 2 This is the handshake logic between the R ISCV core and the original FPGA in the shared area of ​​the dual-port RAM;

[0041] Figure 3 One of the switching strategies for redundant communication configurations consisting of the internal CANFD1 / 2 and the external CANFD1 / 2 of the arbitration switching module;

[0042] Figure 4 The second switching strategy for redundant communication configuration consisting of CANFD1 / 2 inside and outside the arbitration switching module;

[0043] Figure 5 This invention provides an application architecture for the CANFD communication extension system based on FPGA and embedded RISCV processor in a brake controller. Detailed Implementation

[0044] To make the objectives, technical solutions, and advantages of this application clearer, the application will be further described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0045] The technical solution of this application will be further described in detail below with reference to the accompanying drawings and embodiments.

[0046] Figure 1 The CANFD communication extension system architecture diagram provided for the embodiments of this application is as follows: Figure 1 As shown, a CANFD communication expansion system based on an FPGA and an embedded R ISCV processor can connect to up to four external CAN / CANFD isolated interfaces via a front panel connector, enabling communication with the controller or external devices facing long distances and strong interference. Similarly, up to four internal CAN / CANFD isolated interfaces can be connected via a back panel connector, enabling communication with internal controller boards. The system can also obtain its own configuration through simple communication interfaces such as serial port and SPI communication, allowing for different communication structures and protocol conversions.

[0047] The entire system comprises a RISC-V core and FPGA communication extension logic, primarily designed on the FPGA main chip. The FPGA communication extension logic includes an MCU interaction module, a status monitoring module, a protocol conversion module, an arbitration switching module, a channel mapping module, and a CANFD IP. The CANFD IP connects to external CAN / CANFD isolation interfaces, including an external CAN / CANFD isolation interface connected to the front panel and an internal CAN / CANFD isolation interface connected to the back panel. The RISC-V core connects to the external maintenance interface, which interfaces with the RISC-V core's software development environment.

[0048] The FPGA main chip can be Xilinx's Spantan7 series XC7S100FGGA484-2. The high-speed parallel capability of the FPGA allows data transmission and reception, logic conversion, etc., between channels to run independently and in parallel, ensuring maximum real-time performance.

[0049] The RISCV core is a 32-bit RISCV architecture processor core built on FPGA RTL code. It supports instruction set extensions such as IMVF, instruction / data buffer extensions, and a standard JTAG debugging interface. It also extends this processor core with basic peripherals such as serial ports, SPI, and GPIO for external communication to obtain configuration information and upload fault or status information. The processor core instruction set can be continuously adjusted and expanded according to actual needs, and the instruction / data buffer can be widened. The flexible secondary development interfaces and space provide possibilities for product iteration and upgrades.

[0050] The RISC-CV core's operating logic is developed through an IDE environment. The IDE is equipped with a standard RISC-CV compilation toolchain, providing compilation, debugging, and download functions. It also provides application design use cases for the RISC-CV core and underlying peripherals, and provides a C language environment to support the development of communication configuration logic for the communication expansion board. Designers can achieve different communication configurations through simple porting and modification, thus improving project development efficiency.

[0051] The CANFD IP core is built on FPGA RTL code and features a configurable data receive buffer with a maximum depth of 4096. It can implement flexible CAN / CANFD configurations according to application requirements, including receive frame filtering, transmit priority control, and failure retransmission count.

[0052] During the system initialization and configuration phase, when loading configuration information, the RISC V core obtains system configuration parameters through an external maintenance interface. These parameters include channel mapping relationships, protocol conversion rules, arbitration switching strategies, and operating parameters for each CANFD IP core. The channel mapping relationships define the correspondence between physical interfaces and logical channels. The protocol conversion rules include channels requiring mutual conversion between CAN and CANFD, as well as data packet assembly / disassembly rules. The arbitration switching strategy includes monitoring objects for redundant channels, fault judgment conditions, and switching logic. The operating parameters for each CANFD IP core include baud rate, receive filter ID, and frame type.

[0053] The RISCV core writes configuration parameters to the shared memory area on the FPGA logic side through the MCU interaction module. The shared memory area refers to a dual-port RAM generated by logic resources inside the FPGA. Port A of the dual-port RAM is connected to the APB bus of the RISCV core, and Port B of the dual-port RAM is connected to the logic circuit on the FPGA side. The logic circuit includes the control state machine in the MCU interaction module.

[0054] Specifically, the MCU interaction module maps a dual-port RAM to the APB bus of the RISC-V core, allowing the FPGA and RISC-V core to share the same memory area for data exchange. Data communication between the two is achieved by instantiating a dual-port RAM and mapping it to the APB bus used for communication with the RISC-V core. The FPGA acts as a slave device on the RISC-V core's APB bus, converting APB bus address and enable signals into the dual-port RAM's A port signals. The dual-port RAM's B port is directly driven for reading and writing by the FPGA. All exchanged addresses are read and written sequentially after a handshake. The handshake logic is as follows: when reading or writing to a target address, both the FPGA and MCU notify each other of their read or write request before starting the corresponding action. If the other party is currently operating on the target address, they wait for the operation to finish before taking action, preventing data concatenation errors caused by both parties operating on the same address simultaneously. See [link to details] for more information. Figure 3 .

[0055] The FPGA's channel mapping module, protocol conversion module, arbitration switching module, status monitoring module, and each CANFDIP core read their respective parameters from the shared memory area and perform their own configurations.

[0056] The status monitoring module monitors the bus status of all interfaces.

[0057] After the system initialization and configuration phase is completed, the data interaction phase begins. Taking the reception of data frames from external devices via the external CAN / CANFD isolation interface as an example, this application may include:

[0058] External CAN / CANFD isolated interface for receiving data frames from external devices;

[0059] Specifically, the external CAN / CANFD isolation interface and the CANFD IP core are in one-to-one correspondence; when the external CAN / CANFD isolation interface receives a data frame from an external device, the CANFD IP core corresponding to the external CAN / CANFD isolation interface receives the data frame.

[0060] Correspondingly, this application can also receive data frames through an internal CAN / CANFD isolation interface and then perform a similar subsequent processing procedure. The subsequent processing procedure is similar to that of receiving data frames through an external CAN / CANFD isolation interface, and will not be described in detail here.

[0061] The first CANFD IP core, which is connected to the external CAN / CANFD isolation interface, receives the data frame, performs parsing and CRC verification, and writes the first data in the data frame into the corresponding process FIFO for buffering.

[0062] Specifically, the first data is the valid data frame in the data frame after parsing and CRC verification.

[0063] The channel mapping module determines the first logical channel corresponding to the external CAN / CANFD isolation interface;

[0064] The channel mapping module, based on the channel mapping relationship, queries and determines the logical channel corresponding to the external CAN / CANFD isolation interface, and identifies the first logical channel as the corresponding logical channel. The mapping relationship is stored in a mapping table during the initialization phase. In the mapping table, the module queries the logical channel corresponding to the physical interface, such as CAN1, and designates that logical channel as the first logical channel.

[0065] Specifically, the channel mapping module supports the exchange of the mapping relationship between the CAN / CANFD interfaces of different connectors and their internal configuration logic, matching the currently pre-designed channel logic with the actual external connector channels. In the event of errors or replacements in the controller hardware design or connector wiring, channel matching can be quickly achieved by modifying the channel mapping relationship. This provides great flexibility for product designs with tight project timelines and complex communication logic, significantly improving the fault tolerance rate of product development.

[0066] The protocol conversion module converts the first data of the first logical channel into the second data.

[0067] Specifically, the configuration rules include the correspondence between the external CAN / CANFD isolation interface and the internal CAN / CANFD isolation interface, and the conversion relationship between CAN frames and CANFD frames. The protocol conversion module, according to the configuration rules, performs forced frame conversion, data packetization, and baud rate switching. Forced frame conversion includes converting standard CAN frames to CANFD frame format. Data packetization includes concatenating data segments from multiple consecutively received CAN frames into a single CANFD frame. Baud rate switching includes adjusting the frame's baud rate to the rate of the corresponding internal CAN / CANFD isolation interface. The protocol conversion module determines whether the data of the logical channel needs conversion based on the configuration rules. For example, if the configuration rule is external CAN1-internal CANFD1, and CAN frames need to be converted to CANFD frames, the module will perform forced frame conversion, data packetization, and baud rate switching.

[0068] Specifically, the protocol conversion module performs protocol conversion on transmitted or received frames according to configuration requirements, including frame forced conversion, data packet assembly / depacketization, and baud rate switching. Frame forced conversion: When converting from CAN to CANFD, the data frame content is automatically padded with zeros; when converting from CANFD to CAN, the least significant byte is truncated, and the most significant byte is automatically discarded. Data packet assembly / depacketization: When converting from CAN to CANFD, the data segments of multiple CAN frames are sequentially concatenated to form a CANFD frame according to the configuration; when converting from CANFD to CAN frame, the CANFD frame data segments are sequentially disassembled and distributed to different CAN frames. Baud rate switching: Received CAN / CANFD frames are converted to the target configured baud rate and inserted into the receive or transmit FIFO to ensure that frame loss due to inconsistent transmit and receive speeds does not occur before and after baud rate switching.

[0069] The arbitration switching module determines the status of the first logical channel and its redundant second logical channel, determines the target logical channel for transmitting the second data, and stores the second data in the process FIFO.

[0070] The system further includes: a status monitoring module; the status monitoring module feeds back the status of the redundant channels to the arbitration switching module; the status includes whether the received frame timed out and whether the bus error count exceeded the limit. The arbitration switching module determines the target logical channel for transmitting the second data based on the status of the first and second logical channels, which are redundant channels, and a preset strategy; the preset strategy includes a default trusted channel. For example, if the default trusted channel is the first logical channel and the first logical channel is in a normal state, then the first logical channel is determined as the target logical channel; if the first logical channel is in an abnormal state, then the system switches to the second logical channel and uses the second logical channel as the target logical channel, and vice versa.

[0071] Specifically, such as Figure 4 and Figure 5 As shown, the arbitration switching module allows for automatic arbitration switching of redundant channels based on application configuration under multi-channel redundant communication requirements. For example, if the inner CANFD1 / 2 and outer CANFD1 / 2 are configured as a redundant communication pair, the configuration status monitoring module can automatically monitor the communication data and bus status of the two interfaces of the inner CANFD1 / 2. If a communication anomaly is detected on the current channel for a certain period of time, the arbitration switching module is notified to switch the trusted redundant channel data and forward the data of that channel as valid data to the outer CANFD1 / 2. The forwarding from outer CANFD1 / 2 to inner CANFD1 / 2 is designed similarly, and will not be elaborated here.

[0072] The second CANFD IP core, connected to the internal CAN / CANFD isolation interface, reads the second data from the process FIFO and sends it through the internal CAN / CANFD isolation interface.

[0073] Specifically, if the inner CAN / CANFD1 is bound to the second CANFD IP core, the second CANFD IP core will retrieve the second data from the FIFO and send it out according to the CAN or CANFD protocol specification. The second data will eventually be sent out through the inner CAN / CANFD1, thus completing the forwarding from the outside to the inside.

[0074] Furthermore, in an optional implementation, the status monitoring module of this application monitors the bus error status, bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module for each first CANFD IP core and each second CANFD IP core.

[0075] When a bus error is detected and the system enters an offline state, a fast reset or slow reset is automatically triggered on the corresponding first CANFD IP core and / or second CANFD IP core.

[0076] The bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module are updated to the shared memory area through the MCU interaction module so that the RISC-CV core can read them.

[0077] Furthermore, in an optional implementation, the RISCV core of this application periodically reads bus error faults, bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module in the shared memory area through the MCU interaction module, and sends them to the host computer through the maintenance interface; or dynamically adjusts the switching strategy of the arbitration switching module or the parameters of the protocol conversion module through the MCU interaction module, thereby realizing fine-tuning during operation.

[0078] Furthermore, in an optional implementation, the RISCV core of this application analyzes the bus load rate, error frame count, response frame delay statistics, and the timestamp and cause of the most recent switching event of the arbitration switching module according to a preset algorithm to determine a new switching strategy or dynamically adjust the protocol conversion parameters. The determination of the new switching strategy includes fault determination delay and switching hysteresis. The fault determination delay is the time for determining bus delay anomalies. The switching hysteresis includes introducing a back-switch condition: when the quality of the backup channel is better than that of the primary channel for more than a preset duration, the primary channel is switched back. The dynamic adjustment of the protocol conversion parameters includes updating the number of packet frames from CAN to CANFD to decrease under congested conditions and increasing the number of packet frames when the link is stable and high throughput is required. The preset algorithm is a built-in algorithm and can be a commonly used algorithm in the prior art; this application is not limited to it.

[0079] The following is a typical implementation example to illustrate how each module is implemented.

[0080] This application presents a typical communication architecture for a brake controller. The remote external device, primarily the caliper, is responsible for actual braking and status acquisition. It communicates with the controller's internal safety board or anti-slip plate card via a CAN / CANFD bus. The controller's internal components include a communication expansion board, a safety board, an anti-slip plate card, a CPU board, and other I / O boards. The safety board handles functional safety-related design, performing DO control and DI acquisition of key braking signals. The anti-slip plate card is responsible for acquiring external sensor signals and implementing anti-slip algorithms, transmitting anti-slip parameters to the external caliper device via the backplane CANFD. The CPU board handles external network communication and vehicle logic control, and configures the communication logic of the communication expansion board according to the design. Other CAN / CANFD communication nodes are for data logging or power monitoring, and their specifics vary depending on the project and are not detailed here. The communication expansion board, which is the core of this invention, is responsible for communication forwarding and protocol conversion between internal and external CAN / CANFD devices. The communication expansion board achieves physical and logical isolation between the controller's internal and external CAN / CANFD communication, ensuring the stability and integrity of internal CAN / CANFD communication while providing communication capabilities between the caliper and internal devices.

[0081] The first channel uses a forced conversion to pad the internal CAN frame data frame content with 0s and then fills it into the CANFD before sending it to the external CANFD interface. It also extracts the lower 8 bytes of valid data from the externally received CANFD frame and fills them into the CAN frame before sending it to the internal CAN interface.

[0082] The second channel sequentially decomposes the data segment of the internal CANFD frame into 8 CAN data frames through packet assembly / depacketization, and sends them to the external CAN interface through the 8 target CAN frames. At the same time, it sequentially splices the 8 CAN data frames from the external CAN interface according to the transmission and reception rules to form the CANFD data frame content and sends it to the internal CANFD interface.

[0083] The external CANFD on channels 3 and 4 features redundant communication, interfacing with redundant interfaces on the clamps, with each interface supporting four clamp devices. The internal CANFD 3.4 communicates with both the safety control board and the skid plate, transmitting their respective control and algorithm commands. The communication expansion board simultaneously forwards data frames from the internal CANFD 3.4 to the external CANFD 3.4. Each clamp, upon receiving two sets of redundant data, also returns a response data frame through these two CANFD interfaces. The communication expansion board monitors the communication status and feedback data frames of the two CANFD interfaces. If the current trusted clamp response times out or malfunctions, it switches to the redundant path and sends the feedback data frame from the redundant path back to the internal CANFD.

[0084] The above communication structure is just one implementation of the communication expansion board; more topologies can be developed according to project requirements.

[0085] The CANFD communication extension system based on FPGA and embedded RISC-V processor provided in this application has the following technical advantages:

[0086] 1. High flexibility and strong configurability; configuration parameters can be easily modified to achieve board reuse according to different project requirements. Supports expansion of multiple communication structures and supports the design of redundant communication mechanisms related to functional safety in the rail transit field.

[0087] 2. Low communication latency and low cost. The system architecture design ensures that only a single ordinary FPGA chip is needed to achieve the high-speed, low-latency communication that previously required high-end MCUs or complex chip combinations, significantly reducing costs. The FPGA handles real-time demanding functions such as CAN / CANFD communication forwarding. The FPGA's parallel processing capabilities ensure that each communication interface operates independently during forwarding, guaranteeing real-time performance. The MCU implemented with the RISC core handles frequently modified, less real-time-critical communication configuration and status maintenance functions. The clear division of labor between the FPGA and the RISC core ensures rich functionality while maintaining high real-time performance.

[0088] 3. High degree of autonomy and controllability. It adopts independently controllable CANFD IP core, RISC-V core and self-developed IDE development environment. Different configuration modifications can be made according to project and development needs. It gets rid of dependence on various CANFD controllers and MCU cores and is not affected by various external unstable factors and technical bottlenecks.

[0089] 4. Simplified cross-platform portability. The underlying key IP cores are designed using RTL code, without complex IP core nesting. This significantly reduces the difficulty of porting the technical solution to mainstream FPGA chips on the market, and avoids problems such as driver redevelopment and simulation caused by differences in tools and IP cores of different FPGA chips, greatly shortening development time. At the same time, because the new design can flexibly configure the instruction set, data / instruction cache space, CAN / CANFD data buffer space, etc. of the entire RISCCV core, it can achieve flexible adaptability design between FPGAs with different resources.

[0090] 5. High degree of isolation and high fault tolerance between different interfaces. The communication expansion board not only achieves physical isolation between internal and external channels (including level isolation, etc.), but also ensures timely exit from the bus and recording of abnormal information when internal or external buses malfunction through intermediate plug-in arbitration switching, process FIFO, or status monitoring, thus avoiding the impact of a single bus node on the entire communication link.

[0091] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0092] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented in hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0093] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of this application. It should be understood that the above description is only a specific embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application should be included within the scope of protection of this application.

Claims

1. A CANFD communication extension system based on an FPGA and an embedded RISC-V processor, characterized in that, The FPGA has an embedded RISC-V core, and the system includes: External CAN / CANFD isolated interface for receiving data frames from external devices; The first CANFD IP core, which is connected to the external CAN / CANFD isolation interface, receives the data frame, performs parsing and CRC verification, and writes the first data in the data frame into the corresponding process FIFO. The channel mapping module determines the first logical channel corresponding to the external CAN / CANFD isolation interface; The protocol conversion module converts the first data of the first logical channel into the second data. The arbitration switching module determines the status of the first logical channel and its redundant second logical channel, determines the target logical channel for transmitting the second data, and stores the second data in the process FIFO. The second CANFD IP core, connected to the internal CAN / CANFD isolation interface, reads the second data from the process FIFO and sends it through the internal CAN / CANFD isolation interface; During the system initialization and configuration phase, when loading configuration information, the RISC V core obtains system configuration parameters through an external maintenance interface. These parameters include channel mapping relationships, protocol conversion rules, arbitration switching strategies, and operating parameters for each CANFD IP core. The channel mapping relationships define the correspondence between physical interfaces and logical channels. The protocol conversion rules include channels requiring mutual conversion between CAN and CANFD, as well as data packet assembly / disassembly rules. The arbitration switching strategy includes monitoring objects for redundant channels, fault judgment conditions, and switching logic. The operating parameters for each CANFD IP core include baud rate, receive filter ID, and frame type. The RISCV core writes configuration parameters into the shared memory area on the FPGA logic side through the MCU interaction module. The shared memory area refers to a dual-port RAM generated by logic resources inside the FPGA. Port A of the dual-port RAM is connected to the APB bus of the RISCV core, and Port B of the dual-port RAM is connected to the logic circuit on the FPGA side. The logic circuit includes the control state machine in the MCU interaction module. The FPGA's channel mapping module, protocol conversion module, arbitration switching module, status monitoring module, and each CANFD IP core read their respective parameters from the shared memory area and perform their own configurations. The status monitoring module monitors the bus status of all interfaces.

2. The system according to claim 1, characterized in that, Each of the external CAN / CANFD isolation interfaces corresponds one-to-one with each of the first CANFD IP cores; When the external CAN / CANFD isolation interface receives a data frame from an external device, the first CANFD IP core corresponding to the external CAN / CANFD isolation interface receives the data frame.

3. The system according to claim 1, characterized in that, The channel mapping module queries and determines the logical channel corresponding to the external CAN / CANFD isolation interface according to the channel mapping relationship, and determines the first logical channel as the corresponding logical channel.

4. The system according to claim 1, characterized in that, The configuration parameters also include the correspondence between the external CAN / CANFD isolation interface and the internal CAN / CANFD isolation interface, and include the conversion relationship between CAN frames and CANFD frames; The protocol conversion module performs frame forced conversion, data packet assembly, and baud rate switching according to the configuration parameters. The frame forced conversion includes converting a standard CAN frame into a CANFD frame format. The data packet assembly includes concatenating the data segments of multiple consecutively received CAN frames into a single CANFD frame. The baud rate switching includes adjusting the baud rate of the frame to the rate of the corresponding internal CAN / CANFD isolation interface.

5. The system according to claim 1, characterized in that, The system also includes: a status monitoring module; The status monitoring module feeds back the status of the redundant channels to the arbitration switching module; the status includes whether the received frame timed out and whether the bus error count exceeded the limit. The arbitration switching module determines the target logical channel for transmitting the second data based on the status of the first and second logical channels, which are redundant channels, and a preset strategy; the preset strategy includes a default trusted channel.

6. The system according to claim 5, characterized in that, The status monitoring module monitors the bus error status, bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module for each first CANFD IP core and each second CANFD IP core. When a bus error is detected and the system enters an offline state, a fast reset or slow reset is automatically triggered on the corresponding first CANFD IP core and / or second CANFD IP core. The bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module are updated to the shared memory area through the MCU interaction module so that the RISC-CV core can read them.

7. The system according to claim 1, characterized in that, The RISCV core periodically reads bus error faults, bus load rate, error frame count, response frame delay statistics, timestamp and reason of the most recent switching event of the arbitration switching module from the shared memory area through the MCU interaction module, and sends them to the host computer through the maintenance interface; or dynamically adjusts the switching strategy of the arbitration switching module or the parameters of the protocol conversion module through the MCU interaction module.

8. The system according to claim 7, characterized in that, The RISCV core analyzes the bus load rate, error frame count, response frame delay statistics, and the timestamp and cause of the most recent switching event of the arbitration switching module according to a preset algorithm to determine a new switching strategy or dynamically adjust the protocol conversion parameters. The determination of the new switching strategy includes fault determination delay and switching hysteresis. The fault determination delay is the time to determine the bus delay anomaly. The switching hysteresis includes introducing a back-switch condition. When the quality of the backup channel is better than that of the primary channel for more than a preset duration, the primary channel is switched back. The dynamic adjustment of protocol conversion parameters includes updating the number of packet frames from CAN to CANFD to decrease in congested conditions and increasing the number of packet frames when the link is stable and high throughput is required.

9. The system according to claim 1, characterized in that, The CANFD communication extension system based on FPGA and embedded RISCV processor includes: RISCV core and FPGA communication extension logic; the FPGA communication extension logic includes MCU interaction module, status monitoring module, protocol conversion module, arbitration switching module, channel mapping module, first CANFD IP core and second CANFD IP core.

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