Method and system for reading and writing data based on corelet interconnect interface address allocation
By mapping the core interconnect structure to a directed graph and simplifying it into a subgraph, allocating addresses, and using the interconnect interface controller for address translation and routing, the problem of read/write data errors caused by address confusion between cores is solved, improving product design freedom and data processing performance.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING XINLI TECH INNOVATION CENT CO LTD
- Filing Date
- 2025-10-29
- Publication Date
- 2026-07-31
AI Technical Summary
In the interconnection interface between cores, address confusion or misinterpretation can lead to errors in reading and writing data, affecting product design freedom and data processing performance.
The core-particle interconnect structure is mapped as a directed graph, which is then simplified into subgraphs and addresses are assigned. The interconnect interface controller is used for address translation and routing to ensure correct data transmission.
It increases product design freedom and data processing performance, reduces development and verification workload, and improves system efficiency.
Smart Images
Figure CN121478709B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of semiconductor manufacturing technology, and in particular relates to a read / write data processing method and system based on chip interconnect interface address allocation. Background Technology
[0002] The interconnect interface uses the AXI protocol to interconnect memory modules, which has an excellent application feature: direct memory access at source addresses. However, each memory module has its own memory layout, and address mapping and routing are required to enable direct memory access between modules. For IP developers, this means allocating address space to each module; for software developers, system drivers and applications also depend on these software addresses to start their corresponding functions.
[0003] If different dynamic random access memories have different addresses, the CPU may not be able to find the address or may mistakenly send data to a device on the AXI that has the same address, causing malfunctions. Summary of the Invention
[0004] The present invention was completed in view of the above-mentioned problems. The purpose of the present invention is to solve the problems of read and write data processing errors caused by address confusion or mixing among multiple chips in the interconnect interface chip structure, thereby improving product design freedom and product data processing performance.
[0005] A read / write data processing method based on chip interconnect interface address allocation according to an embodiment of the present invention includes:
[0006] The interconnected structure of multiple interconnected cores is mapped to a directed graph, which includes at least: an AXI bus controller, described as a node; and an interconnect interface controller, described as an edge, wherein the direction of the edge is: from the end of the interconnect interface controller as an AXI Slave to the end of the interconnect interface controller as an AXI Master.
[0007] Based on the chip product design requirements, the data flow between multiple chips is determined. Based on the data flow, the directed graph is simplified into a subgraph. The process of reducing the directed graph into a subgraph includes: first, reducing the directed graph to remove loops; then, based on the control flow and data flow direction of the chip system, a suitable root node is selected, and a subgraph is constructed starting from the root node so that this subgraph covers all nodes. Among them, multiple root nodes represent the initiators of data read and write requests in the chip system.
[0008] Starting from the root node of the subgraph, each interconnect interface controller is assigned an address. If a node has multiple edges, then the child nodes connected to this edge are all assigned address segments from their corresponding parent nodes.
[0009] Each interconnect interface controller, based on its assigned address, determines whether a received read / write request should be forwarded to a device on the current bus or routed to another interconnect interface controller.
[0010] The first core is connected to the second core via a first interconnect interface controller, and the second core is connected to the third core via a second interconnect interface controller.
[0011] Enter the address of the interconnect interface controller in the AXI command of the first chip;
[0012] When the first interconnect interface controller identifies that the address corresponds to the second dynamic random access memory according to the algorithm of the preset value, it generates a read / write command on the second bus corresponding to the second dynamic random access memory and pushes the data and address to the second dynamic random access memory.
[0013] When the first interconnect interface controller identifies that the address corresponds to the third dynamic random access memory according to the algorithm of the preset value, the first interconnect interface controller sends the data to the second interconnect interface controller; when the second interconnect interface controller identifies that the address corresponds to the third dynamic random access memory according to the algorithm of the preset value, the third bus corresponding to the third dynamic random access memory generates a read / write command and pushes the data and address to the third dynamic random access memory.
[0014] Furthermore, preferably, in the read / write data processing method based on chip interconnect interface address allocation according to an embodiment of the present invention, the interconnect interface controller also provides a routing function: the addresses of the second dynamic random access memory and the third dynamic random access memory where the second bus and the third bus are respectively located are both allocated in [1G, 5G). When it is planned to write to the second dynamic random access memory, the data is actually sent to the second interconnect interface controller; when the write address is an address between [15G, 19G), the second interconnect interface controller sends the data to the second dynamic random access memory; when the write address is an address between [10G, 14G), the second interconnect interface controller sends the data to the third interconnect interface controller, and the third interconnect interface controller identifies and sends the data to the third dynamic random access memory according to a preset algorithm, generating a corresponding data write request.
[0015] Furthermore, preferably, in the read / write data processing method based on the address allocation of the chip interconnect interface according to an embodiment of the present invention, if a node has multiple edges, then the child nodes connected to this edge all divide the address segment from the corresponding parent node.
[0016] Furthermore, preferably, in the read / write data processing method based on the address allocation of the core interconnect interface according to an embodiment of the present invention, for devices inside the AXI bus, the address inside the core is still used. When communication with other cores is required, the address range of the other core is used, plus the address inside the core, as the address to be accessed.
[0017] Furthermore, preferably, the present invention also provides a read / write data processing system based on the address allocation of the chip interconnect interface, which employs any of the read / write data processing methods described in the present invention to implement its read / write data processing.
[0018] Using this invention, chip architecture designers can determine the number and direction of access to other devices by the master device of each subsystem according to actual product development needs, which greatly improves the freedom of product design and the data processing efficiency of the product. Attached Figure Description
[0019] Figure 1 This is a schematic diagram illustrating a scenario in which multiple modules within a System-on-a-Chip (SOC) access each other via pre-allocated addresses in a data read / write processing method according to an embodiment of the present invention.
[0020] Figure 2 This is a schematic diagram illustrating a case where address translation is required in the chip interconnect structure during the read / write data processing method according to an embodiment of the present invention.
[0021] Figure 3 This is a schematic diagram illustrating a case where the interconnect interface controller in the chip interconnect structure of a read / write data processing method according to an embodiment of the present invention also provides routing functionality.
[0022] Figure 4 This is a schematic diagram illustrating a case where the core assembly in the core interconnect structure of a read / write data processing method according to an embodiment of the present invention includes complex structures such as loops and branches.
[0023] Figure 5 This is a schematic diagram illustrating the use of an address allocation algorithm in the chip interconnect structure of a read / write data processing method according to an embodiment of the present invention.
[0024] Figure 6 This is a schematic diagram illustrating a directed graph in a data reading and writing method according to an embodiment of the present invention.
[0025] Figure 7 This is a schematic diagram illustrating a sub-diagram of a data reading and writing method according to an embodiment of the present invention.
[0026] Figure 8This is a schematic diagram illustrating a sub-diagram of a data reading and writing method according to an embodiment of the present invention. Detailed Implementation
[0027] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.
[0028] The interconnect interface is based on the AXI protocol for interconnecting between memory chips. This has an excellent application feature: it allows direct in-place memory access. Specifically, the UCIe interconnect standard only supports packaged data access. If data at a specific memory address is needed, the corresponding controller must package the data at that address and send it to the receiver, which then unpacks it to access the data content. AXI, on the other hand, allows direct reading or writing using memory addresses, achieving zero-copy memory access and significantly improving system efficiency. However, each memory chip has its own memory layout. To enable direct memory access between memory chips, address mapping and routing are required. The details are described below.
[0029] If we disregard chip interconnects, multiple modules within a single SoC access each other through pre-assigned addresses, such as... Figure 1 As shown.
[0030] When the CPU needs to access DRAM (assuming the system allocates an address range of [1G, 5G] to DRAM), it needs to send a read or write command on the AXI bus, passing the address (e.g., 1G + 0x100) to the command field. The bus controller then notifies the DRAM to update or provide data. For IP developers, this means allocating address space for each module. For software developers, system drivers and applications also rely on these software addresses to start their corresponding functions.
[0031] When using chip interconnect, address access requires translation, such as... Figure 2 As shown.
[0032] The chip consists of two "die chips". The AXI bus controllers of these two dies have already assigned address ranges to the devices on the bus. DRAM1 and DRAM2 are assigned the same address in their respective independent AXI address systems, which is [1G, 5G].
[0033] When CPU1 needs to access DRAM1, it still uses DRAM1's address to send AXI commands. However, when CPU1 needs to access DRAM2, it cannot use DRAM2's address because the AXI1 bus actually sends CPU commands to the interconnect interface controller (named Interconnect Interface 1_2). If the address of DRAM2 (a 1G to 5G address space) is entered, the bus controller will send this data to DRAM1 instead of DRAM2. In the above example, DRAM1 and DRAM2 are assumed to have the same address. Even without this assumption, DRAM2 has a different address than DRAM1. If the CPU uses DRAM2's address to send data, it will either not find the address or send the data to a device on AXI1 with the same address, causing a misoperation.
[0034] Therefore, CPU1 needs to fill in the address of the interconnect interface controller in the AXI command (in the example above, it is an address between 10G and 14G). The interconnect interface controller, based on the algorithm of the preset value, recognizes that this address corresponds to DRAM2, and then actively generates a read / write command on the AXI2 bus to push the data and address to DRAM2. Therefore, an address translation process is required on the interconnect interface controller.
[0035] In addition to address translation, the interconnect interface controller also needs to provide routing functionality, as described below. Figure 3 As shown, CPU1 prepares to write data to DRAM2 and DRAM3. DRAM2 and DRAM3 both have addresses [1G, 5G] on their respective AXI buses. When CPU1 plans to write to DRAM2, the data is actually sent to the interconnect interface controller (named Interconnect Interface 1_2). According to a pre-set algorithm, when the address CPU1 writes to is between [15G, 19G), Interconnect Interface 1_2 sends the data to DRAM2; when the address CPU1 writes to is between [10G, 14G), Interconnect Interface 1_2 sends the data to another interconnect interface controller, HIP2_3. Then, after receiving the data, Interconnect Interface 2_3, according to a pre-set algorithm, identifies that the data is destined for DRAM3 and generates the corresponding write request.
[0036] In more complex topologies, address routing and mapping require clever design, such as... Figure 4 As shown, the core assembly includes structures such as loops and branches.
[0037] The problems with the memory address mapping model can be described in the following table:
[0038] The changes to the subsystems can be summarized in the following table:
[0039] This chapter describes the algorithm for address allocation. A chip system is used as an example. Figure 5 As shown.
[0040] For the sake of generality, devices1 / 2 / 3 / 4 are all assumed to be both master and slave devices, and the interconnect interface controller is also a master / slave device that can send requests in both directions.
[0041] Chip architects first determine the number and direction of accesses from the master to other devices for each subsystem.
[0042] In the example above, it is assumed that each master device needs to access all other slave devices.
[0043] The connections between the core particles are represented by a directed graph, with the following specific rules:
[0044] ① An AXI bus controller is described using nodes.
[0045] ② An interconnect interface controller is described by one edge.
[0046] ③ The direction of the edge is from one end of the interconnect interface controller acting as an AXI Slave to the other end of the interconnect interface controller acting as an AXI Master.
[0047] The directed graph in the above example is as follows Figure 6 As shown.
[0048] If a node has only incoming edges and no outgoing edges, then this node acts only as a slave device. After address mapping by the interconnect interface controller, the hardware and software of this leaf node can be completely unchanged, reducing the workload of development and verification.
[0049] The directed graph is reduced to a subgraph. First, the directed graph is reduced to remove loops. Then, a suitable root node is selected based on the control flow and data flow direction of the core system. A subgraph is constructed starting from the root node, ensuring that this subgraph covers all nodes. There can be multiple root nodes. This represents the initiator of data read / write requests in the core system.
[0050] The subgraphs in the above examples are as follows Figure 7 As shown.
[0051] Assign an address to each node.
[0052] First, estimate the granularity of address allocation. Evaluate the address range of each kernel and determine the maximum value of the address range for all kernels. For example, AXI0 might use an address space of [0, 32G), and AXI1 might use an address space of [256, 512G). Therefore, we can select the largest value across all address ranges, i.e., 512G, as the granularity. Since the 64-bit address bus range is extremely large, we can choose 1T as the address unit for one kernel.
[0053] If a node has multiple edges, then the child nodes connected to that edge all share address ranges from their corresponding parent nodes. For example, ... Figure 8 As shown, if AXI2 is allocated a space of 3T to 4T, then AXI5 and AXI6 can only use a certain address range within 3T to 4T, and cannot use addresses in the range [0, 3T) and [4T, ∞). This is because if there is only one interconnect interface controller between AXI1 and AXI2, and if it can send discrete addresses to AXI2, AXI5, and AXI6, it requires an address translation module such as an MMU within the core particle system. If the address range can be allocated continuously, this dependence on the MMU can be reduced.
[0054] Addresses are assigned starting from the root node (instead of from the leaf nodes, to avoid address discretization). For the initial example, the range of addresses that can be assigned is shown in the table below.
[0055] For devices within the AXI bus, the internal address of the core is still used. When communication with other cores is required, the address range of the other core is used, plus the internal address of the core, as the address to be accessed.
[0056] According to an embodiment of the present invention, the core idea is to map the chip structure as a directed graph; the chip developer determines the data flow and simplifies the directed graph into a subgraph; addresses are allocated starting from the root node; each interconnect interface controller needs to identify whether the received read / write request is forwarded to the device on the current bus or routed to other interconnect interface controllers.
[0057] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.
[0058] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.
[0059] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.
[0060] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.
Claims
1. A read-write data processing method based on a core particle interconnection interface address allocation, characterized in that, include: A core-particle interconnection structure formed by interconnecting multiple core particles is mapped to a directed graph, wherein the directed graph includes at least: An AXI bus controller, described as a node; An interconnect interface controller is described as an edge, wherein the direction of the edge is: from the end of the interconnect interface controller that is an AXI Slave, to the end of the interconnect interface controller that is an AXI Master; Based on the chip product design requirements, the data flow between multiple chips is determined. Based on the data flow, the directed graph is simplified into a subgraph. The process of reducing the directed graph into a subgraph includes: first, reducing the directed graph to remove loops; then, based on the control flow and data flow direction of the chip system, a suitable root node is selected, and a subgraph is constructed starting from the root node so that this subgraph covers all nodes. Among them, multiple root nodes represent the initiators of data read and write requests in the chip system. Starting from the root node of the subgraph, each interconnect interface controller is assigned an address. If a node has multiple edges, then the child nodes connected to this edge are all assigned address segments from their corresponding parent nodes. Each interconnect interface controller, based on its assigned address, identifies whether a received read / write request should be forwarded to a device on the current bus or routed to another interconnect interface controller, including: The first core is connected to the second core via a first interconnect interface controller, and the second core is connected to the third core via a second interconnect interface controller. Enter the address of the interconnect interface controller in the AXI command of the first chip; When the first interconnect interface controller identifies that the address corresponds to the second dynamic random access memory according to the algorithm of the preset value, it generates a read / write command on the second bus corresponding to the second dynamic random access memory and pushes the data and address to the second dynamic random access memory. When the first interconnect interface controller identifies that the address corresponds to the third dynamic random access memory according to the algorithm of the preset value, the first interconnect interface controller sends the data to the second interconnect interface controller; when the second interconnect interface controller identifies that the address corresponds to the third dynamic random access memory according to the algorithm of the preset value, it generates a read / write command on the third bus corresponding to the third dynamic random access memory and pushes the data and address to the third dynamic random access memory.
2. The data reading and writing method according to claim 1, characterized in that, The interconnect interface controller also provides routing functionality: it allocates addresses in the second and third dynamic random access memory (DRAMs) where the second and third buses reside, respectively, to the range [1G, 5G). When data is planned to be written to the second DRAM, it is actually sent to the second interconnect interface controller. When the write address is between [15G, 19G), the second interconnect interface controller sends the data to the second DRAM. When the write address is between [10G, 14G), the second interconnect interface controller sends the data to the third interconnect interface controller. The third interconnect interface controller identifies the data according to a pre-set algorithm and sends it to the third DRAM, generating a corresponding data write request.
3. The data reading and writing processing method according to claim 2, characterized in that, For devices within the AXI bus, the internal address of the core is still used. When communication with other cores is required, the address range of the other core is used, plus the internal address of the core, as the address to be accessed.
4. A read / write data processing system based on the address allocation of the chip interconnect interface, which adopts the read / write data processing method according to any one of claims 1 to 3 to realize its read / write data processing.