D2D type core particle interface interconnection system

Abstract

The application provides a D2D type core particle interface interconnection system, wherein a core particle CPU delivers the work of D2D type core particle interface interconnection IP to a plurality of MCUs, the plurality of MCUs manage the D2D type core particle interface interconnection IP respectively, the core particle CPU manages other work except the D2D type core particle interface interconnection, when the link establishment of the D2D type core particle interface IP subsystem succeeds or fails, the current state is informed to the core particle CPU, the core particle CPU reports the state to a user application layer after recording the state, and the state is cleared, when a certain MCU for managing the D2D type core particle interface interconnection IP fails, the core particle CPU takes over the management work of the failed MCU. By using the application, the start time of the core particle-die can be accelerated, the software development workload is reduced, the power consumption can be greatly reduced, the development cost of the CPU IP is saved, and the overall yield of the core particle chip is improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor manufacturing technology, and particularly relates to a D2D type chip interface interconnect system. Background Technology

[0002] In common interconnection methods of existing die-to-die interconnect structures, the die-to-die interconnection is implemented by a D2D die-to-die interface IP. The CPU performs initialization, link training, low-power management, debug & trace, and exception handling for the modules within the D2D die-to-die interface IP, while also managing the entire die-to-die system. The D2D die-to-die interface IP subsystem consists of die-to-die interface interconnection control, die-to-die interface PHY, and AXI and APB buses. After the system starts with the D2D die-to-die interface IP, the die CPU must perform initialization, link training, or exception handling operations on it. Especially when initializing each D2D die-to-die interface IP individually, this is a serial operation, and the total time spent is N times the time spent on a single D2D die-to-die interface IP, which is quite time-consuming.

[0003] The heavy workload on the system CPU leads to increased die-to-die costs. Most operations are serial, resulting in excessively long die-to-die startup times. Firmware adjustments impose a significant workload on system software development. When supporting multiple D2D die-to-die interconnect IPs, the CPU allocates most of its resources to handling the D2D die-to-die interface subsystem, leading to low overall die-to-die system efficiency and high power consumption. Summary of the Invention

[0004] In view of the above-mentioned problems existing in the prior art, the present invention provides a D2D type chip-to-chip interface interconnection system, wherein the chip CPU delivers the D2D type chip-to-chip interface interconnection IP work to multiple MCUs, with each MCU managing its own D2D type chip-to-chip interface interconnection IP, and the chip CPU managing other work besides the D2D type chip-to-chip interface interconnection; when the link of the D2D type chip-to-chip interface IP subsystem is successfully or unsuccessfully established, the current status is notified to the chip CPU, which records the status and reports it to the user application layer, while simultaneously clearing the status; when one of the MCUs managing the D2D type chip-to-chip interface interconnection IP fails, the chip CPU takes over the management work of the failed MCU, wherein the D2D type chip-to-chip interface interconnection work delivered by the chip CPU to the MCUs... The core-to-core interface interconnect (CTI) IP functions include: initializing the D2D type CTI IP, link training, handling exceptions with the D2D type CTI IP, and managing the low-power D2D type CTI IP; sending interrupt commands to the MCU for interrupt handling when interrupts occur in the CTI IP control and PHY; reporting the successful or failed establishment of the inter-die link to the CTI CPU and informing it of its working status; and managing other tasks besides the D2D type CTI IP, including: receiving status flags indicating successful and / or failed link establishment initiated by the D2D type CTI IP; recording the current link status flags and reporting them to the application layer; and clearing the status flags after reporting. The D2D type CTI IP includes: MCU, AHB decoder, APB decoder, APB mux, AHB to APB protocol, ROM, CTI IP control, and CTI interface PHY.

[0005] Furthermore, preferably, in the D2D type chip interface interconnect system of the present invention, the ROM stores the MCU boot program. After the MCU starts up, the program in the chip memory is read through the AHB master to complete the initialization of the D2D type chip interface IP, link training, low power management and exception handling.

[0006] Furthermore, preferably, in the D2D type chip-to-die interface interconnect system of the present invention, when the chip-to-die is under CP testing, if a fault is found in the MCU, the flag bit of eFuse is written to make sel 0. When sel is 0, it indicates that the MCU is faulty and the CPU takes over the work of the MCU. In the default state, sel is 1, which makes the MCU active.

[0007] Furthermore, preferably, in the D2D type chip-to-chip interface interconnect system of the present invention, the MCU's operation includes: initialization and link training of the D2D type chip-to-chip interface interconnect IP, exception handling and low-power management of the D2D type chip-to-chip interface interconnect IP, interrupt handling of chip-to-chip interface interconnect control and PHY, and reporting the success or failure of the inter-die link establishment to the chip system.

[0008] Furthermore, preferably, in the D2D type chip interface interconnect system of the present invention, there are N+1 D2D type chip interface interconnect IPs between D2D type chip interfaces 0 and N, where N is any positive integer.

[0009] Furthermore, preferably, in the D2D type chip-to-chip interface interconnect system of the present invention, when the D2D type chip-to-chip interface interconnect IP is an independent system, its initialization, link training and anomaly handling are not handled by the chip CPU. Only when the link between the bare dies is successfully established or fails, the CPU is notified. The CPU records the status of each link node, clears the current status of the D2D type chip-to-chip interface interconnect IP, and reports it to the user system for handling by the user system itself.

[0010] Using this invention, the startup time of the chip to the die can be accelerated, the software development workload can be reduced, power consumption can be greatly reduced, the development cost of CPU IP can be saved, and the overall yield of the chip can be improved. Attached Figure Description

[0011] Figure 1 This is a schematic diagram illustrating a chiplet-die interconnect structure in the prior art.

[0012] Figure 2 This is a schematic diagram illustrating the architecture of a D2D type chip interface IP in the prior art.

[0013] Figure 3 This is a schematic diagram illustrating the relationship between a chip CPU and various D2D type chip interface IP subsystems in the prior art.

[0014] Figure 4 This is a schematic diagram illustrating the structure of a chip interconnect system according to an embodiment of the present invention.

[0015] Figure 5 This is a schematic diagram illustrating the interaction process between a chip CPU and a D2D type chip interface interconnect IP according to an embodiment of the present invention.

[0016] Figure 6 This is a schematic diagram illustrating the architecture of a D2D type chip interface interconnect IP according to an embodiment of the present invention. Detailed Implementation

[0017] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Other embodiments or modifications obtained by those skilled in the art based on the embodiments of this application without creative effort are all within the scope of protection of this application.

[0018] Existing chip interconnect architectures such as Figure 1 As shown. Figure 1 This is a schematic diagram illustrating the existing chiplet-die interconnect structure.

[0019] Figure 1 The existing die-to-die interconnect structure shown is a common interconnect method. The interconnect between dies is implemented by a D2D die interface IP. The CPU completes the initialization of the modules within the D2D die interface IP, link training, low-power management, debug & trace, and exception handling, while managing the entire die-to-die system.

[0020] The implementation method of the existing architecture between internal modules of D2D type chip interface IP is as follows. Figure 2 This is a schematic diagram illustrating the architecture of an existing D2D type chip interface IP. The D2D type chip interface IP subsystem consists of chip interface interconnect control, chip interface PHY, and AXI and APB buses. The modules within the D2D type chip interface IP are performed by the chip CPU in the following aspects:

[0021] 1) Initialize the D2D type core interface IP subsystem;

[0022] 2) Training of the D2D type core interface IP subsystem link;

[0023] 3) An anomaly occurred in the D2D type core interface IP subsystem, generating an interrupt and reporting it to the system. Anomaly handling is required.

[0024] 4) Low-power management of the D2D chip interface IP subsystem;

[0025] 5) The chip interface interconnection control and chip interface PHY have completed their current tasks and have initiated an interrupt reporting to the system, which requires interrupt handling.

[0026] 6) After the D2D type chip interface IP generates an interrupt and reports it to the system, the CPU should clear the current state after processing the interrupt program.

[0027] Figure 3 This is a schematic diagram illustrating the relationship between the chip CPU and the various D2D chip interface IP subsystems in the prior art.

[0028] like Figure 3 The diagram shows a flowchart of how the chip CPU manages each D2D chip interface IP subsystem. After the system starts the D2D chip interface IP, the chip CPU needs to perform operations such as initialization, link training, or exception handling. In particular, when initializing each one, it is a serial operation process, and the total time spent is N times the time spent on a single D2D chip interface IP, which takes a long time.

[0029] Based on the above analysis, it is easy to see that existing chip-to-chip interconnect systems have many problems, the main ones being the following:

[0030] 1) The die-to-die system is centrally managed by the CPU. The initialization, training, low-power management, and exception handling of the D2D interconnect subsystem are all completed by the CPU, which makes the CPU task heavy and puts high demands on CPU performance, thus increasing the cost of the die-to-die system.

[0031] 2) Since the CPU needs to perform initialization, link training, and exception handling for each D2D type chip interconnect interface IP one by one, most of its operations are serial and the process is very long. Therefore, the chip-die startup time is too long. When users have a low tolerance for startup time, they may abandon this system.

[0032] 3) The firmware of the D2D type chip interface interconnection IP is strongly coupled with the chip system OS. The firmware needs to be adapted to the OS. Therefore, when the OS changes, the firmware also needs to be greatly adjusted, which will bring a lot of workload to the system software development.

[0033] 4) When the die-to-die interface supports many D2D type die-to-die interconnection interface IPs, the CPU has to allocate most of its resources to handle the work of the D2D type die-to-die interface subsystem, resulting in low overall die-to-die system execution efficiency and wasted resources.

[0034] 5) Because the CPU operates at a high frequency (≥1GHz) for a long time, the system power consumption is very high.

[0035] Therefore, one of the objectives of this invention is to solve the problems of existing chip interconnect systems, and it has the following prominent advantages:

[0036] 1) The chip system implements a distributed management D2D interconnect system, where each D2D works independently and with high parallelism, which can accelerate the startup time of the chip-to-die.

[0037] 2) Since the D2D interconnect system is an independent system and is weakly coupled with the core system, it is not affected by the core system's OS (operating system), which reduces the workload of software development and provides a user-friendly experience.

[0038] 3) Since the D2D interconnect system is an independent system and is managed independently by the MCU, it is more efficient and can use a lightweight MCU, thus reducing the development cost of the MCU. At the same time, the MCU operating frequency can be reduced to below 100MHz, and its power consumption can be greatly reduced.

[0039] 4) Since the CPU of the chip system does not manage the D2D interconnect system, the management resources of the D2D interconnect system are offloaded, and the overall CPU load is reduced, allowing it to focus more on managing tasks outside of the D2D interconnect. The CPU performance requirements can be appropriately reduced, thus saving the development cost (or IP license cost) of CPU IP.

[0040] 5) Because the CPU's performance requirements have been reduced, its operating frequency has also been reduced, thus reducing system power consumption.

[0041] 6) Due to the consideration of redundancy mechanism, when the MCU in the D2D IP fails, it can be a bypass MCU, and the CPU takes over the management of the D2D chip interface IP, thereby improving the overall yield of the chip.

[0042] A chip interconnect architecture according to one embodiment of the present invention is described below.

[0043] Figure 4 This is a schematic diagram illustrating the structure of a chip interconnect system according to an embodiment of the present invention. Figure 4 The diagram shows the interconnect system of the chip-die architecture. The number of chips / dies and interconnect nodes are assumed values ​​for ease of explanation. Each chip / die consists of a CPU, a D2D interconnect system, and other modules (not shown in this design). The CPU manages all systems except for the D2D chip-die interface interconnect. Each D2D chip-die interface IP has an embedded lightweight MCU for management. Only when a link in a D2D chip-die interface IP subsystem is successfully established or fails does it notify the CPU of its current status. The CPU records the status, reports it to the user application layer, and simultaneously clears the status. When the MCU within the D2D chip-die interface interconnect IP fails, the CPU can take over the MCU's work, ensuring normal system operation.

[0044] The following explains the working mode of CPU and D2D type chip interface interconnection.

[0045] Figure 5 This is a schematic diagram illustrating the interaction process between a chip CPU and a D2D type chip interface interconnect IP according to an embodiment of the present invention.

[0046] The chip CPU delegates the D2D chip interface interconnection IP work to the MCU, which mainly includes:

[0047] Initialize the D2D type chip interface interconnect IP;

[0048] Link training;

[0049] Anomaly handling D2D type chip interface interconnect IP;

[0050] Low-power managed D2D chip interface interconnect IP;

[0051] When there is an interrupt in the chip interface interconnection control and PHY, an interrupt is sent to the MCU, and the MCU handles the interrupt.

[0052] When the inter-die link is successfully established or fails, the system reports the status to the chip CPU.

[0053] The main functions of a CPU core include:

[0054] Receive link establishment success and failure flags initiated by D2D type core interface interconnection IP, record the current link status and report it to the application layer;

[0055] Clear the status flags.

[0056] Therefore, it is easy to see that the D2D type chip interface interconnect IPs are unrelated, independent, do not require CPU management, and are highly parallel.

[0057] The following is an explanation of the D2D type chip interface interconnect IP.

[0058] Figure 6 This is a schematic diagram illustrating the architecture of a D2D type chip interface interconnect IP according to an embodiment of the present invention.

[0059] The D2D type chip interface interconnect IP mainly consists of the following modules:

[0060] MCU;

[0061] AHB decoding;

[0062] APB decoding;

[0063] APB mux;

[0064] AHB to APB protocol (AHB2APB);

[0065] ROM;

[0066] Core interface interconnection control;

[0067] Chip-to-chip interface interconnect PHY.

[0068] The ROM stores the MCU boot program. After the MCU starts up, it reads the program in the chip memory through the AHB master to complete the initialization of the D2D chip interface IP, link training, low power management, and exception handling.

[0069] When the die is tested by CP, if the MCU is found to be faulty, the sel flag is written to 0. When sel is 0, it means that the MCU is faulty and the CPU takes over the work of the MCU. In the default state, sel is 1, which makes the MCU active.

[0070] The main tasks of an MCU include:

[0071] Initialization of D2D type chip interface interconnect IP;

[0072] Link training;

[0073] D2D type chip interface interconnection IP anomaly handling;

[0074] Low power management;

[0075] Core interface interconnection control and PHY interrupt handling;

[0076] The success or failure of establishing a link between dies is reported to the chip system.

[0077] D2D type chip interface 0~N is N+1 interconnected IPs of D2D type chip interface, where N can be any value.

[0078] When the D2D type chip-to-chip interface interconnect IP is an independent system, its initialization, link training and exception handling are not handled by the CPU. Only when the link between the bare dies is successfully established or fails, the CPU is notified. The CPU records the status of each link node, clears the current status of the D2D type chip-to-chip interface interconnect IP, and reports it to the user system for handling.

[0079] The various advantages and beneficial effects of this invention include:

[0080] 1. A distributed management approach is adopted, where the CPU manages tasks other than the D2D chip-to-die interface interconnection, offloading the CPU's management resources for the D2D chip-to-die interface interconnection subsystem. The CPU is only informed of the current D2D link status when the D2D chip-to-die IP link is successfully established or fails. This significantly reduces the CPU's load, thereby accelerating the chip-to-die processing speed. At the same time, it lowers the CPU's performance requirements, saves system costs, and reduces system power consumption.

[0081] 2. Since each D2D type chip interface has a lightweight MCU embedded in its interface IP, forming an independent system, its D2D type chip interface IP initialization, link training, exception handling, low power management and other operations can be completed independently, with higher utilization and high parallelism, which can greatly improve the system startup speed.

[0082] 3. Since the interface IP of the D2D chip interface is an independent system, its firmware is fixed and will not be adjusted with changes in the OS of the chip-die, which reduces the workload of system software development and improves user-friendliness.

[0083] 4. Since the MCU only performs basic configuration and exception handling, it can operate at a very low frequency (≤100MHz) and consumes very little power.

[0084] 5. When the MCU fails, an external CPU takes over the MCU's work, preventing the current D2D chip interface node from becoming obsolete. This improves the chip-to-die yield and saves costs.

[0085] Note: Since MCUs are lightweight, their area is less than 0.015 mm2 under SMIC's 12nm process; while the area of ​​a high-performance CPU is >5 mm2. If the performance requirements of the CPU are reduced, the area can be reduced by more than 1 mm2. Overall, it is not difficult to see that the advantages of reducing the performance requirements of the CPU far outweigh the advantages of increasing the cost of the MCU.

[0086] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0087] The various embodiments in this specification are described in a related manner. The same or similar parts between the various embodiments can be referred to each other. Each embodiment focuses on describing the differences from other embodiments.

[0088] The above description is merely a specific embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

[0089] The above embodiments of the present invention are merely examples for clearly illustrating the present invention and are not intended to limit the implementation of the present invention. Those skilled in the art will recognize that other variations or modifications can be made based on the above description. It is neither necessary nor possible to exhaustively describe all possible implementations here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A D2D type chip-to-chip interface interconnection system, characterized in that, The chip CPU delegates the D2D chip interface interconnection IP work to multiple MCUs, with each MCU managing the D2D chip interface interconnection IP, and the chip CPU managing other work besides the D2D chip interface interconnection. When the link of the D2D type core interface IP subsystem is successfully established or fails, the current status is notified to the core CPU. After recording the status, the core CPU reports it to the user application layer and clears the status. When a MCU managing the D2D type chip interface interconnect IP fails, the chip CPU takes over the management duties of the failed MCU. The D2D chip interface interconnect IP work delivered from the chip CPU to the MCU includes: Initialize D2D type chip interface interconnection IP, link training, exception handling D2D type chip interface interconnection IP, and low power management D2D type chip interface interconnection IP; When an interrupt occurs in the chip interface interconnect control and PHY, an interrupt command is sent to the MCU for interrupt handling. When the inter-die link is successfully established or fails, the system reports to the chip CPU and informs it of its working status. In addition to managing the D2D type chip interface interconnect, other tasks performed by the chip CPU include: Receive status flags indicating success and / or failure of link establishment initiated by D2D type core interface interconnect IP; Record the current link status flags and report them to the application layer; Clear the status flag after reporting. The D2D type chip interface interconnection IP includes: MCU, AHB decoder, APB decoder, APB mux, AHB to APB protocol, ROM, chip interface interconnection control, and chip interface PHY.

2. The D2D type chip-to-chip interface interconnection system according to claim 1, characterized in that, The ROM stores the MCU boot program. After the MCU starts up, the program in the chip memory is read through the AHB master to complete the initialization of the D2D chip interface IP, link training, low power management and exception handling.

3. The D2D type chip-to-chip interface interconnection system according to claim 2, characterized in that, When the die is tested by CP, if the MCU is found to be faulty, the sel is set to 0 by writing the eFuse flag. When sel is 0, it means that the MCU is faulty and the CPU takes over the work of the MCU. By default, sel is 1, which enables the MCU.

4. The D2D type chip-to-chip interface interconnection system according to claim 1, characterized in that, The MCU's operation includes: Initialization and link training of D2D type chip interface interconnection IP. D2D type chip interface interconnect IP anomaly handling and low power management Chip interface interconnection control and PHY interrupt handling, and Report the success or failure of establishing the link between dies to the chip system.

5. The D2D type core-to-particle interface interconnection system according to claim 4, characterized in that, There are N+1 D2D type chip interface interconnect IPs between 0 and N, where N is any positive integer.

6. The D2D type chip-to-chip interface interconnection system according to claim 1, characterized in that, When the D2D type chip interface interconnect IP is an independent system, its initialization, link training and anomaly handling are not handled by the chip CPU. The CPU is only notified when the link between the bare dies is successfully established or fails. The CPU records the status of each link node, clears the current status of the D2D type chip interface interconnect IP, and reports it to the user system for handling.

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