Cross-stage chip design hardware security link analysis method, apparatus, and media

Abstract

The present application relates to the technical field of chip, especially to a cross-stage chip design hardware security link analysis method, device and medium, the method comprises the following steps: S1, obtaining an interface mapping relationship table; S2, obtaining hardware security point information corresponding to a logical layer chip design, and generating a hardware security point information table of the logical layer chip design; S3, obtaining hardware security point information corresponding to a physical layer chip design of RTL, and generating a hardware security point information record table of the physical layer chip design of RTL based on the interface mapping relationship table, which has the same structure as the hardware security point information table of the logical layer chip design; S4, obtaining target A m a first target security link is constructed, and target A m corresponding target B m a second target security link is constructed, and hardware security analysis is performed. The present application realizes hardware security analysis of a target security link of a cross-stage chip design, and improves the development efficiency of the chip.

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