Driving circuit and display device

Abstract

The application provides a driving circuit and a display device. The driving circuit comprises a compensation circuit and a timing controller. The compensation circuit is electrically connected with a first pixel electrode and a second pixel electrode in the same column of sub-pixels, respectively. The first pixel electrode and the second pixel electrode are pixel electrodes of a sub-pixel located in an Mth row and a sub-pixel located in an M-1th row, respectively. The timing controller is electrically connected with the compensation circuit. When the display panel operates in a hardware super-resolution mode, the timing controller is configured to output a compensation start signal to the compensation circuit in a vertical blanking stage of a current frame picture. The compensation circuit is configured to detect a first voltage of the first pixel electrode and a second voltage of the second pixel electrode in response to the compensation start signal, and compensate the first pixel electrode based on the first voltage and the second voltage. The driving circuit can improve the tail row dark line problem of the display panel in the HSR mode.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to driving circuits and display devices. Background Technology

[0002] In recent years, with the rapid development of display technology, the market demand for high-resolution and high-refresh-rate display devices has been growing. Although new display technologies such as OLED (Organic Light-Emitting Diode) have achieved large-scale application and demonstrated advantages in high refresh rates and high resolutions, under the constraints of current chip computing power and hardware parameters, the industry has proposed various frequency doubling refresh technologies to further improve refresh rates. Among them, HSR (Hard Super Resolution) frequency doubling display technology is an important high refresh rate algorithm solution.

[0003] The basic principle of HSR (High-Refresh-Rate) technology is to shorten the frame refresh time by reducing the number of pixels actually rendered per unit time, thereby doubling the refresh rate without changing the hardware. For example, for a native 4K 60Hz display, the goal of applying HSR technology is to increase the perceived refresh rate of the screen to 120Hz. Its typical implementation involves reducing the precision of pixel rendering vertically, usually using an interlaced rendering strategy. For example, only odd-numbered rows of pixels are fully rendered, while even-numbered rows are dynamically fused with the image information of their adjacent upper and lower rows through an algorithm, and displayed in a time-sharing manner (e.g., displaying the data of the previous row for half the time and the data of the next row for half the time) to simulate additional frames. This "algorithm fusion, time-sharing display" mechanism effectively avoids hardware performance bottlenecks, achieving both data load reduction and refresh rate improvement.

[0004] However, this technology has a significant and common technical problem in practical applications: the display panel will show a trailing dark line in HSR mode. Summary of the Invention

[0005] In view of this, the main purpose of this application is to propose a driving circuit and a display device, which aims to solve the problem that existing display panels will show trailing dark lines in HSR mode.

[0006] To achieve the above objectives, a first aspect of this application provides a driving circuit for driving a display panel to display, the display panel including a plurality of sub-pixels arranged in an array of M rows and N columns, each sub-pixel including a pixel electrode, M being an even number greater than 1 and N being an integer greater than 1, the driving circuit including a compensation circuit and a timing controller. The compensation circuit is electrically connected to the first pixel electrode and the second pixel electrode in the same column of sub-pixels, respectively; wherein, the first pixel electrode is the pixel electrode of the sub-pixel located in the Mth row, and the second pixel electrode is the pixel electrode of the sub-pixel located in the (M-1)th row; the timing controller is electrically connected to the compensation circuit, and the timing controller is used to output a compensation start signal to the compensation circuit during the vertical blanking stage of the current frame when the display panel is running in hardware super-resolution mode; wherein, in response to the compensation start signal output by the timing controller, the compensation circuit performs voltage detection on the first pixel electrode to obtain a first voltage, performs voltage detection on the second pixel electrode to obtain a second voltage, and performs voltage compensation on the first pixel electrode based on the first voltage and the second voltage, so that the difference between the voltage of the first pixel electrode and the voltage of the second pixel electrode is less than or equal to a preset voltage value.

[0007] The driving circuit provided in this application, through a timing controller, controls the compensation circuit to activate the voltage compensation function during the vertical blanking phase of the current frame when the display panel is running in hardware super-resolution mode. The compensation circuit detects the voltage of the first pixel electrode located in the last row of the same column of sub-pixels to obtain a first voltage, and detects the voltage of the second pixel electrode located in the second-to-last row of the same column of sub-pixels to obtain a second voltage. Based on the first and second voltages, voltage compensation is performed on the first pixel electrode so that the difference between the voltage of the first pixel electrode and the voltage of the second pixel electrode is less than or equal to a preset voltage value. In this way, the voltage of the pixel electrode in the last row of sub-pixels can be compensated based on the charging voltage of the pixel electrode in the second-to-last row of sub-pixels. This can improve the brightness of the last row of sub-pixels and reduce the brightness difference between the last row of sub-pixels and other rows of sub-pixels, thereby improving the problem of dark lines at the tail of the display panel in HSR mode.

[0008] In some embodiments of this application, the timing controller is used to output a compensation start signal to the compensation circuit during the vertical blanking phase of the current frame when the display panel is running in hardware super-resolution mode and the number of non-zero grayscale sub-pixels in the (M-1)th row of sub-pixels is greater than or equal to a preset number based on the image data of the current frame; wherein, the non-zero grayscale sub-pixels are sub-pixels whose target grayscale is not zero.

[0009] In some embodiments of this application, the compensation circuit includes a control circuit, a switching circuit, and an amplification circuit. The switching circuit is electrically connected to the control circuit, the first pixel electrode, the second pixel electrode, and the timing controller, respectively. Responding to a compensation start signal output by the timing controller, the switching circuit connects the control circuit to the first pixel electrode and the second pixel electrode. The amplification circuit is electrically connected to the switching circuit, the first pixel electrode, and the control circuit, respectively. The control circuit detects a voltage at the first pixel electrode to obtain a first voltage, detects a voltage at the second pixel electrode to obtain a second voltage, and, based on the first and second voltages, controls the amplification circuit to amplify the first voltage to obtain a third voltage, and outputs the third voltage to the first pixel electrode to achieve voltage compensation for the first pixel electrode.

[0010] In some embodiments of this application, the amplification circuit includes an operational amplifier, a first resistor, and a second resistor. The operational amplifier includes a non-inverting input, an inverting input, and an output. The non-inverting input is electrically connected to the switching circuit, and the output is electrically connected to the first pixel electrode. The first resistor is electrically connected between the inverting input of the operational amplifier and ground. The second resistor is electrically connected between the inverting input and the output of the operational amplifier, and is an adjustable resistor. The control circuit is electrically connected to the second resistor. The control circuit determines a target resistance value for the second resistor based on the first voltage and the second voltage, and adjusts the resistance value of the second resistor to the target resistance value. This allows the operational amplifier, in conjunction with the first and second resistors, to amplify the first voltage to obtain the third voltage and output the third voltage to the first pixel electrode.

[0011] In some embodiments of this application, the control circuit is used to calculate the target resistance value of the second resistor using the following formula: V2 / V1=1+R2 / R1; where V1 is the first voltage, V2 is the second voltage, R1 is the resistance value of the first resistor, and R2 is the target resistance value of the second resistor.

[0012] In some embodiments of this application, the driving circuit includes N compensation circuits, each of which corresponds to one of the N columns of sub-pixels; wherein the i-th compensation circuit of the N compensation circuits is electrically connected to the first pixel electrode and the second pixel electrode of the i-th column of the N columns of sub-pixels, respectively; wherein 1≤i≤N.

[0013] In some embodiments of this application, the switching circuit includes a first switching transistor and a second switching transistor. The first switching transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the first switching transistor is electrically connected to the first pixel electrode, the second connection terminal of the first switching transistor is electrically connected to the control circuit, and the control terminal of the first switching transistor is electrically connected to the timing controller. The first switching transistor conducts the electrical connection between the first pixel electrode and the control circuit in response to the compensation start signal output by the timing controller. The second switching transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the second switching transistor is electrically connected to the second pixel electrode, the second connection terminal of the second switching transistor is electrically connected to the control circuit, and the control terminal of the second switching transistor is electrically connected to the timing controller. The second switching transistor conducts the electrical connection between the second pixel electrode and the control circuit in response to the compensation start signal output by the timing controller.

[0014] In some embodiments of this application, the display panel includes M scan lines and N data lines; the M scan lines are electrically connected to M rows of sub-pixels in a one-to-one correspondence, and the N data lines are electrically connected to N columns of sub-pixels in a one-to-one correspondence; the driving circuit further includes a scan driver, a data driver, and a power management chip. The scan driver is electrically connected to each of the M scan lines. During the effective display phase of the current frame, the scan driver outputs a corresponding scan signal to the M scan lines to sequentially scan the M rows of sub-pixels. The data driver is electrically connected to each of the N data lines. The power management chip is electrically connected to the data driver and the timing controller. The timing controller is further configured to output a corresponding voltage adjustment signal to the power management chip when the display panel is running in hardware super-resolution mode, and when the scan driver finishes scanning the (M-1)th row of sub-pixels in the display panel. This causes the power management chip to output a first analog power supply voltage to the data driver. The power management chip is also configured to output a second analog power supply voltage to the data driver when it does not receive the voltage adjustment signal. The first analog power supply voltage is higher than the second analog power supply voltage. The data driver receives the analog power supply voltage output by the power management chip and outputs a corresponding data voltage to the N data lines based on the received analog power supply voltage to charge the scanned sub-pixels. The analog power supply voltage includes both the first and second analog power supply voltages.

[0015] In some embodiments of this application, the first analog power supply voltage and the second analog power supply voltage satisfy the following relationship: AVDD1=K×AVDD2; where AVDD1 is the first analog power supply voltage, AVDD2 is the second analog power supply voltage, and K≥2.

[0016] A second aspect of this application also provides a display device, the display device including a display panel and a driving circuit as described in the first aspect above, the driving circuit being electrically connected to the display panel and used to drive the display panel to perform a display.

[0017] Additional aspects and advantages of this application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of this application. Attached Figure Description

[0018] Figure 1 This is a schematic diagram of a first structure of a display device provided in an embodiment of this application; Figure 2 for Figure 1 The diagram shows the charging timing of the display device in normal mode; Figure 3 for Figure 1 The diagram shows the charging timing of the display device in hardware super-resolution mode. Figure 4 This is a second structural schematic diagram of the display device provided in the embodiments of this application; Figure 5 for Figure 4 The timing diagram of the driving signals for the sub-pixels in the (M-1)th and Mth rows of the display device is shown.

[0019] The annotations in the attached figures are explained as follows: 100 - Display device; 10 - Display panel; 20 - Driving circuit; 221 - Switching circuit; 222 - Control circuit; 223 - Amplification circuit; 2221 - Detection and calculation module; 2222 - Adjustment module; 21 - Timing controller; 22 - Compensation circuit; 23 - Power management chip; 24 - Data driver; 25 - Scan driver; 26 - Counter; 11 - Scan line; G1 - Scan line; G2 - Scan line; G3 - Scan line; G4 - Scan line; G5 - Scan line; G6 - Scan line; G7 - Scan line; G8 - Scan line; 12 - Data line; P - Sub-pixel; T1 - First switch transistor; T2 - Second switch transistor; T3 - Third switch transistor; R1 - First resistor; R2 - Second resistor; R3 - Third resistor; C1 - First capacitor; V1 - Data voltage; V2 - Data voltage; S1 - Data voltage; S2 - Data voltage; S3 - Data voltage; t1 - Interval time; t2 - Charging time; U1 - Operational amplifier.

[0020] The following detailed description, in conjunction with the accompanying drawings, will further illustrate this application. Detailed Implementation

[0021] In the description of the embodiments of this application, the terminology used in the following embodiments is for the purpose of describing specific embodiments only and is not intended to be a limitation of this application. As used in the specification and appended claims of this application, the singular expressions "a," "the," "the," "the," and "this" are intended to also include expressions such as "one or more," unless the context clearly indicates otherwise. It should also be understood that in the following embodiments of this application, "at least one" and "one or more" refer to one or more (including two). The term "and / or" is used to describe the relationship between related objects, indicating that three relationships can exist; for example, A and / or B can indicate: A alone, A and B simultaneously, or B alone, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship.

[0022] References to "one embodiment" or "some embodiments" in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized. The term "connection" includes direct connections and indirect connections, unless otherwise stated. "First" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated.

[0023] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0024] The various embodiments of this application can be combined arbitrarily to achieve different technical effects.

[0025] In recent years, with the rapid development of display technology, the market demand for high-resolution and high-refresh-rate display devices has been growing. Although new display technologies such as OLED have achieved widespread application and demonstrated advantages in high refresh rates and high resolutions, under the constraints of current chip computing power and hardware parameters, the industry has proposed various frequency doubling refresh technologies to further improve refresh rates. Among them, HSR frequency doubling display technology is an important high refresh rate algorithm solution.

[0026] The basic principle of HSR (High-Refresh-Rate) technology is to shorten the frame refresh time by reducing the number of pixels actually rendered per unit time, thereby doubling the refresh rate without changing the hardware. For example, for a native 4K 60Hz display, the goal of applying HSR technology is to increase the perceived refresh rate of the screen to 120Hz. Its typical implementation involves reducing the precision of pixel rendering vertically, usually using an interlaced rendering strategy. For example, only odd-numbered rows of pixels are fully rendered, while even-numbered rows are dynamically fused with the image information of their adjacent upper and lower rows through an algorithm, and displayed in a time-sharing manner (e.g., displaying the data of the previous row for half the time and the data of the next row for half the time) to simulate additional frames. This "algorithm fusion, time-sharing display" mechanism effectively avoids hardware performance bottlenecks, achieving both data load reduction and refresh rate improvement.

[0027] Please refer to the following for details. Figures 1-3 , Figure 1 This is a schematic diagram of a first structure of a display device provided in an embodiment of this application; Figure 2 for Figure 1 The diagram shows the charging timing of the display device in normal mode; Figure 3 for Figure 1 The diagram shows the charging timing of the display device in hardware super-resolution mode.

[0028] like Figure 1 As shown, the display panel 10 includes multiple sub-pixels P, M scan lines 11, and N data lines 12. The multiple sub-pixels P are arranged in an array of M rows and N columns. The M scan lines 11 are electrically connected to each of the M rows of sub-pixels P, that is, each scan line 11 is electrically connected to each sub-pixel P in the corresponding row of sub-pixels P. The N data lines 12 are electrically connected to each of the N columns of sub-pixels P, that is, each data line is electrically connected to each sub-pixel P in the corresponding column of sub-pixels P. Where M>1 and N>1.

[0029] In normal mode, during the activation period of the nth row scan line 11, each column data line 12 outputs a corresponding data voltage. This means the signal source provides data with a resolution of M×N, and the image is displayed normally. The M scan lines 11 are activated sequentially from the 1st scan line 11 to the Mth scan line 11, scanning their respective connected sub-pixels P in turn. Each sub-pixel P connected to each scan line 11 has a corresponding data voltage for charging, such as... Figure 2 As shown, for a column of sub-pixels P in the display panel 10, the data voltage corresponding to the sub-pixel P electrically connected to the first scan line G1 is S1, the data voltage corresponding to the sub-pixel P electrically connected to the second scan line G2 is S2, the data voltage corresponding to the sub-pixel P electrically connected to the third scan line G3 is S3, and so on.

[0030] In HSR mode, only the sub-pixels P connected to the odd-numbered scan lines 11 have corresponding data voltages, while the sub-pixels P connected to the even-numbered scan lines 11 can only charge themselves using the data voltages of the sub-pixels in the same column preceding and following rows. Figure 3 As shown, only the sub-pixels P connected to the odd-numbered scan lines, such as the 1st scan line G1, the 3rd scan line G3, and the 5th scan line G5, have corresponding data voltages, while the sub-pixels P connected to the even-numbered scan lines, such as the 2nd scan line G2, the 4th scan line G4, and the 6th scan line G6, do not have corresponding data voltages.

[0031] It is not difficult to understand, such as Figure 2 As shown, in normal mode, only one row of subpixels P is effectively charged at any given time, while... Figure 3 As shown, in HSR mode, two rows of sub-pixels P can be effectively charged at the same time. Therefore, for a frame, the charging time required in HSR mode is only half that in normal mode. Thus, in the same amount of time, the frame refresh rate in HSR mode is twice that in normal mode.

[0032] However, this technology has a significant and common technical problem in practical applications: the display panel will show a trailing dark line in HSR mode.

[0033] Research revealed the following reason why display panels exhibit a dark trailing line in HSR mode: In HSR mode, for the even-numbered row at the very end of the panel display area (i.e., the trailing row, or the Mth row), there is no subsequent pixel row data below it for fusion (i.e., no data voltage to fuse in the next row). This causes the row to be unable to obtain complete and symmetrical upward and downward data voltages for interpolation compensation, unlike the middle rows. This lack of data source significantly reduces the charging rate or effective light-emitting time of the trailing pixels compared to normal rows, ultimately appearing visually as a dark line with lower brightness.

[0034] This problem is particularly prominent in large-size display panels. Because large-size panels have relatively large pixel sizes, and the overall area makes it easier to magnify local non-uniformity, trailing dark line defects are more noticeable to the human eye. This severely affects the overall uniformity and visual appeal of the displayed image, often resulting in a substandard viewing experience and hindering the widespread application of HSR technology in high-quality display products. Currently, the trailing dark line problem in HSR mode is widely recognized in the industry as a common technical bottleneck that urgently needs to be overcome in this technological approach.

[0035] Therefore, there is an urgent need for an innovative circuit design and driving method that can provide effective and accurate brightness compensation for the characteristics of HSR technology, especially for the tail of the display panel 10, so as to ensure the uniformity of brightness of the entire display area while achieving a high refresh rate and improve the visual quality of the final product.

[0036] In view of this, this application provides a driving circuit 20, which is used to drive the display panel 10 for display. Please refer to [link to relevant documentation]. Figure 4 , Figure 4 This is a second structural schematic diagram of the display device provided in an embodiment of this application. The display panel 10 includes a plurality of sub-pixels P arranged in an array of M rows and N columns. Each sub-pixel P includes a pixel electrode (not shown in the figure), where M is an even number greater than 1 and N is an integer greater than 1. The driving circuit 20 includes a timing controller 21 and a compensation circuit 22.

[0037] The compensation circuit 22 corresponds to a column of sub-pixels P, and is electrically connected to the first pixel electrode and the second pixel electrode in the corresponding column of sub-pixels P. The first pixel electrode is the pixel electrode of the sub-pixel P located in the Mth row (i.e., the last row), and the second pixel electrode is the pixel electrode of the sub-pixel P located in the (M-1)th row (i.e., the second to last row).

[0038] The timing controller 21 is electrically connected to the compensation circuit 22. The timing controller 21 is used to output a compensation start signal to the compensation circuit 22 during the vertical blanking phase (i.e., VBLunk area) of the current frame when the display panel 10 is running in hardware super-resolution mode (i.e., HSR mode).

[0039] The compensation circuit 22 responds to the compensation start signal output by the timing controller 21, performs voltage detection on the first pixel electrode to obtain a first voltage, performs voltage detection on the second pixel electrode to obtain a second voltage, and performs voltage compensation on the first pixel electrode based on the first voltage and the second voltage, so that the difference between the voltage of the first pixel electrode and the voltage of the second pixel electrode is less than or equal to a preset voltage value.

[0040] In this context, the voltage detection target and voltage compensation target of the compensation circuit 22 are both the first pixel electrode and the second pixel electrode in the corresponding column of sub-pixels P. Specifically, voltage detection of the first pixel electrode by the compensation circuit 22 refers to voltage detection of the first pixel electrode in the corresponding column of sub-pixels P. Obtaining the second voltage by voltage detection of the second pixel electrode by the compensation circuit 22 refers to voltage detection of the second pixel electrode in the corresponding column of sub-pixels P. Voltage compensation of the first pixel electrode by the compensation circuit 22 refers to voltage compensation of the first pixel electrode in the corresponding column of sub-pixels P.

[0041] The preset voltage value can be set according to requirements. For example, the preset voltage value can be zero or close to zero, such as 0.01V.

[0042] The driving circuit 20 provided in this application, through the timing controller 21, controls the compensation circuit 22 to start the voltage compensation function during the vertical blanking stage of the current frame when the display panel 10 is running in hardware super-resolution mode. The compensation circuit 22 detects the voltage of the first pixel electrode located in the last row of the same column of sub-pixels to obtain a first voltage, and detects the voltage of the second pixel electrode located in the second-to-last row of the same column of sub-pixels to obtain a second voltage. Based on the first voltage and the second voltage, the voltage of the first pixel electrode is compensated so that the difference between the voltage of the first pixel electrode and the voltage of the second pixel electrode is less than or equal to a preset voltage value. In this way, the voltage of the pixel electrode in the last row of sub-pixels P can be compensated based on the charging voltage of the pixel electrode in the second-to-last row of sub-pixels P. This can improve the brightness of the last row of sub-pixels P and reduce the brightness difference between the last row of sub-pixels P and other rows of sub-pixels P, thereby improving the problem of dark lines at the tail of the display panel 10 in HSR mode.

[0043] In some embodiments of this application, the timing controller 21 is used to output a compensation start signal to the compensation circuit 22 during the vertical blanking phase of the current frame when the display panel 10 is running in hardware super-resolution mode and the number of non-zero grayscale sub-pixels in the (M-1)th row of sub-pixels P is greater than or equal to a preset number based on the image data of the current frame; wherein the image data of the current frame includes the target grayscale of each sub-pixel P, and the non-zero grayscale sub-pixels are sub-pixels whose target grayscale is not zero.

[0044] The timing controller 21 is also used to not output a compensation start signal to the compensation circuit 22 when the display panel 10 is running in normal mode, or when the number of non-zero gray level sub-pixels in the sub-pixel P of the (M-1)th row is less than a preset number, based on the image data of the current frame.

[0045] It's easy to understand that, as mentioned earlier, the data voltage received by the last row sub-pixel P (i.e., the Mth row sub-pixel P) is the same as the data voltage of the second-to-last row sub-pixel P in the same column (i.e., the (M-1)th row sub-pixel P). Therefore, when the target grayscale of the (M-1)th row sub-pixel P is zero grayscale, the charging voltage of the Mth row sub-pixel P is also zero grayscale voltage. At this time, even if the charging rate of the Mth row sub-pixel P is low, there will be no brightness difference between the Mth row sub-pixel P and the (M-1)th row sub-pixel P.

[0046] Therefore, when the proportion of zero-grayscale sub-pixels in the (M-1)th row of sub-pixels P is large, for example, greater than 90%, the display panel 10 will not exhibit trailing dark lines even without activating the compensation circuit 22. Thus, the timing controller 21 only activates the compensation circuit 22 during the vertical blanking phase of the current frame when the display panel 10 is running in hardware super-resolution mode and the number of non-zero-grayscale sub-pixels in the (M-1)th row of sub-pixels P, determined based on the image data of the current frame, is greater than or equal to a preset number. This reduces the power consumption of the compensation circuit 22.

[0047] In some embodiments of this application, the compensation circuit 22 includes a switching circuit 221, a control circuit 222, and an amplifier circuit 223.

[0048] The switching circuit 221 is electrically connected to the control circuit 222, the timing controller 21, the first pixel electrode in the corresponding column sub-pixel P, and the second pixel electrode in the corresponding column sub-pixel P. In response to the compensation start signal output by the timing controller 21, the switching circuit 221 connects the control circuit 222 to the first pixel electrode in the corresponding column sub-pixel P and connects the control circuit 222 to the second pixel electrode in the corresponding column sub-pixel P.

[0049] The amplifier circuit 223 is electrically connected to the switch circuit 221, the control circuit 222, and the first pixel electrode in the corresponding column sub-pixel P.

[0050] The control circuit 222 is used to detect the voltage of the first pixel electrode in the corresponding column sub-pixel P to obtain a first voltage, detect the voltage of the second pixel electrode in the corresponding column sub-pixel P to obtain a second voltage, and based on the first voltage and the second voltage, control the amplification circuit 223 to amplify the first voltage to obtain a third voltage, and output the third voltage to the first pixel electrode in the corresponding column sub-pixel P to achieve voltage compensation for the first pixel electrode in the corresponding column sub-pixel P.

[0051] Specifically, when the compensation start signal is not received, the switch circuit 221 disconnects the electrical connection between the control circuit 222 and the first pixel electrode in the corresponding column sub-pixel P, and disconnects the electrical connection between the control circuit 222 and the second pixel electrode in the corresponding column sub-pixel P.

[0052] Thus, the switching circuit 22 is switched on and off by switching circuit 221, and the first voltage is amplified by amplifier circuit 223 to obtain a third voltage to compensate the voltage of the first pixel electrode. The structure is simple and the reliability is high.

[0053] In some embodiments of this application, the switching circuit 221 includes a first switching transistor T1 and a second switching transistor T2.

[0054] The first switch T1 includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the first switch T1 is electrically connected to the first pixel electrode in the corresponding column sub-pixel P. The second connection terminal of the first switch T1 is electrically connected to the control circuit 222. The control terminal of the first switch T1 is electrically connected to the timing controller 21. The first switch T1 responds to the compensation start signal output by the timing controller 21 to conduct the electrical connection between the first pixel electrode in the corresponding column sub-pixel P and the control circuit 222.

[0055] The second switch T2 includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the second switch T2 is electrically connected to the second pixel electrode. The second connection terminal of the first switch T1 is electrically connected to the control circuit 222. The control terminal of the first switch T1 is electrically connected to the timing controller 21. The second switch T2 responds to the compensation start signal output by the timing controller 21 to turn on the electrical connection between the second pixel electrode and the control circuit 222.

[0056] For example, the first switch T1 and the second switch T2 are N-type thin-film transistors.

[0057] Thus, the compensation circuit 22 is controlled by two switching transistors as the switching circuit 221, resulting in a simple structure.

[0058] In some embodiments of this application, the amplifier circuit 223 includes an operational amplifier U1, a first resistor R1, and a second resistor R2.

[0059] The operational amplifier U1 includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is electrically connected to the switching circuit 221, and the output terminal is electrically connected to the first pixel electrode in the corresponding column sub-pixel P.

[0060] The first resistor R1 is electrically connected between the inverting input terminal of the operational amplifier U1 and ground.

[0061] The second resistor R2 is electrically connected between the inverting input terminal and the output terminal of the operational amplifier U1, and the second resistor R2 is an adjustable resistor.

[0062] The control circuit 222 is electrically connected to the second resistor R2. The control circuit 222 determines the target resistance value of the second resistor R2 based on the first voltage and the second voltage, and adjusts the resistance value of the second resistor R2 to the target resistance value, so that the operational amplifier U1, in conjunction with the first resistor R1 and the second resistor R2, amplifies the first voltage to obtain the third voltage and outputs the third voltage to the first pixel electrode in the corresponding column sub-pixel P.

[0063] Thus, by adjusting the second resistor R2, the operational amplifier U1 can output different compensation voltages, resulting in a simple structure and convenient control.

[0064] In some embodiments of this application, the control circuit 222 is used to calculate the target resistance value of the second resistor R2 using the following formula: V2 / V1 = 1 + R2 / R1; Wherein, V1 is the first voltage, V2 is the second voltage, R1 is the resistance value of the first resistor R1, and R2 is the target resistance value of the second resistor R2.

[0065] Thus, the third voltage output by the operational amplifier U1 to the first pixel electrode is the second voltage, thereby compensating the voltage of the first pixel electrode to be consistent with the voltage of the second pixel electrode, so that the brightness of the Mth row sub-pixel P is consistent with that of the (M-1)th row sub-pixel P.

[0066] In some embodiments of this application, the amplification circuit 223 further includes a first capacitor C1 and a third resistor R3, wherein the first capacitor C1 is electrically connected between the inverting input terminal of the operational amplifier U1 and ground. The third resistor R3 is electrically connected between the output terminal of the operational amplifier U1 and the first pixel electrode in the corresponding column sub-pixel P.

[0067] In some embodiments of this application, the second resistor R2 may be a memristor.

[0068] A memristor is a two-terminal device whose resistance depends not only on the current flowing through it but also on the path that current has taken. In other words, the resistance of a memristor changes according to the direction and magnitude of the current flow, and it can "remember" its previous resistance value after the current is interrupted. This characteristic allows a memristor to retain its state after power is turned off, similar to non-volatile memory.

[0069] The control circuit 222 includes a detection and calculation module 2221 and an adjustment module 2222. The detection and calculation module 2221 is electrically connected to the second connection terminal of the first switching transistor T1, the second connection terminal of the second switching transistor T2, and the adjustment module 2222, respectively. The adjustment module 2222 is also electrically connected to the second resistor R2. The detection and calculation module 2221 is used to detect the voltage of the first pixel electrode in the corresponding column of sub-pixels P to obtain a first voltage, and to detect the voltage of the second pixel electrode in the corresponding column of sub-pixels P to obtain a second voltage. Based on the first voltage and the second voltage, it calculates the target resistance value of the second resistor R2 and outputs the target resistance value to the adjustment module 2222, so that the adjustment module 2222 adjusts the resistance value of the second resistor R2 to the target resistance value.

[0070] In some embodiments of this application, the adjustment module 2222 includes an adjustment controller and a third switch T3, wherein the third switch T3 is electrically connected between the first adjustment pin (unlabeled) of the adjustment controller and the first end of the second resistor R2, the control terminal of the third switch T3 is electrically connected to the control pin (unlabeled) of the adjustment controller, and the second adjustment pin (unlabeled) of the adjustment controller is electrically connected to the second end of the second resistor R2.

[0071] During operation, the adjustment controller outputs a drive signal to the control terminal of the third switch transistor T3 to drive the third switch transistor T3 to conduct and adjust the magnitude and / or direction of the current between its first adjustment pin and second adjustment pin, thereby adjusting the resistance of the second resistor R2 to the target resistance value.

[0072] In some embodiments of this application, the driving circuit 20 includes N compensation circuits 22, each corresponding to one of the N columns of sub-pixels P. The i-th compensation circuit 22 is electrically connected to the first pixel electrode and the second pixel electrode of the i-th column of sub-pixels P, respectively; where 1 ≤ i ≤ N.

[0073] In this way, brightness compensation can be performed on all sub-pixels P in the last row of the display panel 10, thereby improving the display effect of the display panel 10.

[0074] In other embodiments, the number of compensation circuits 22 may be less than N, that is, the driving circuit 20 may only compensate a portion of the sub-pixels P in the tail row of the display panel 10.

[0075] Please refer to it again. Figure 1 In some embodiments of this application, the display panel 10 includes M scan lines 11 and N data lines 12. The M scan lines 11 are electrically connected to M rows of sub-pixels P in a one-to-one correspondence, and the N data lines 12 are electrically connected to N columns of sub-pixels P in a one-to-one correspondence.

[0076] The drive circuit 20 also includes a scan driver 25, a data driver 24, and a power management integrated circuit (PMIC) 23.

[0077] The scan driver 25 is electrically connected to the M scan lines 11 respectively. The scan driver 25 is used to output the corresponding scan signal to the M scan lines 11 during the effective display stage (i.e., the active area) of the current frame, so as to scan the M rows of sub-pixels P sequentially from the first row of sub-pixels P to the Mth row of sub-pixels P.

[0078] The data driver 24 is electrically connected to each of the N data lines 12.

[0079] The power management chip 23 is electrically connected to the data driver 24 and the timing controller 21 respectively, and the power management chip 23 is used to output analog power supply voltage.

[0080] The timing controller 21 is further configured to, when the display panel 10 is operating in hardware super-resolution mode, and when the scan driver 25 finishes scanning the (M-1)th row of sub-pixels P in the display panel 10, output a corresponding voltage adjustment signal to the power management chip 23, so that the power management chip 23 outputs a first analog power supply voltage to the data driver 24. The power management chip 23 is further configured to output a second analog power supply voltage to the data driver 24 when it does not receive the voltage adjustment signal. The first analog power supply voltage is higher than the second analog power supply voltage.

[0081] The data driver 24 receives the analog power supply voltage output by the power management chip 23 and outputs corresponding data voltages to the N data lines 12 based on the received analog power supply voltage to charge the scanned sub-pixel P. The analog power supply voltage includes a first analog power supply voltage and a second analog power supply voltage.

[0082] The simulated power supply voltage, AVDD, also known as the Gamma reference voltage, is a set of reference voltages required by the display device to accurately reproduce the grayscale levels of an image. The data voltage output by the data driver 24 to each sub-pixel P is generated based on this set of Gamma voltages. This set of Gamma voltages is typically generated by precision resistor division of the simulated power supply voltage. In other words, when the value of the simulated power supply voltage increases, the value of this set of Gamma voltages also increases. Consequently, the data voltage corresponding to the same grayscale level also increases. That is, for the same target grayscale level, the brightness of a sub-pixel P charged based on the first simulated power supply voltage will be higher than the brightness of a sub-pixel P charged based on the second simulated power supply voltage.

[0083] For example, please refer to Figure 5 , Figure 5 for Figure 4 The diagram shows the timing of the driving signals for the last two rows of sub-pixels in the display device. Figure 5 As shown, the charging time of sub-pixel P in row M-1 is t2, the charging time of sub-pixel P in row M is 0.5×t2, and the data voltage of a certain sub-pixel P in row M-1 is V1. Then the data voltage of the sub-pixel adjacent to sub-pixel P in row M is V2. Since V1 is generated by the data driver 24 based on the second analog power supply voltage, and V2 is generated by the data driver 24 based on the first analog power supply voltage, and the first analog power supply voltage is greater than the second analog power supply voltage, therefore, V2 > V1.

[0084] Thus, the data driver 24 charges the sub-pixels P in rows 1 to M-1 based on a second analog power supply voltage with a lower voltage value, and charges the sub-pixel P in row M based on a first analog power supply voltage with a higher voltage value. This can achieve overcharge compensation for the sub-pixel P in row M, reduce the difference in charging rate between sub-pixels P in row M and row M-1, and reduce the difference in brightness between sub-pixels P in row M and row M-1. This can further improve the problem of dark lines at the tail of the display panel 10 in HSR mode.

[0085] In some embodiments of this application, the first analog supply voltage and the second analog supply voltage satisfy the following relationship: AVDD1 = K × AVDD2; Wherein, AVDD1 is the first analog power supply voltage, AVDD2 is the second analog power supply voltage, K is the amplification factor, and K≥2.

[0086] In an ideal scenario, ignoring the voltage drop caused by line loss during data transmission, K is set to 2.

[0087] In this way, the charging rates of sub-pixels P in the Mth row and the (M-1)th row can be kept basically the same, thus making the brightness of sub-pixels P in the Mth row basically the same as that of sub-pixels P in the (M-1)th row.

[0088] In some embodiments of this application, the power management chip 23, in response to the voltage adjustment signal output by the timing controller 21, changes from outputting the second analog power supply voltage to the data driver 24 to outputting the first analog power supply voltage when the scanning of the (M-1)th row of sub-pixels P in the display panel 10 ends, until the duration of outputting the first analog power supply voltage reaches a preset duration, and then resumes outputting the second analog power supply voltage to the data driver 24.

[0089] The preset duration can be calculated using the following formula: t3 = t1 - 0.5 × t2; like Figure 5 As shown, t1 is the time interval between the turn-off times of two adjacent scan signals (i.e., the time when the scan signal changes from the turn-on voltage to the turn-off voltage, such as the falling edge of the scan signal), t2 is the charging time of each row of sub-pixels P when the display panel 10 is running in hardware super-resolution mode, and t3 is the preset duration.

[0090] In some embodiments of this application, the driving circuit 20 further includes a function selection module electrically connected to the timing controller 21. The function selection module is used to receive a mode switching instruction and control the display panel 10 to work in hardware super-resolution mode according to the received mode switching instruction.

[0091] In some embodiments of this application, the driving circuit 20 further includes a counter 26, which is electrically connected to the scan driver 25 and the timing controller 21, respectively. The counter 26 is used to detect and count the falling edges of the scan line signals output by the scan driver 25, and when the falling edge of the (M-1)th scan signal is detected, it outputs a trigger signal to the timing controller 21 to trigger the timing controller 21 to output a corresponding voltage adjustment signal to the power management chip 23.

[0092] Based on the same inventive concept, this application also provides a display device 100, which includes a display panel 10 and a driving circuit 20 as described in any of the embodiments above. The driving circuit 20 is electrically connected to the display panel 10 and is used to drive the display panel 10 to perform display.

[0093] Although embodiments of this application have been shown and described, those skilled in the art will understand that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of this application, the scope of which is defined by the claims and their equivalents.

Claims

1. A driving circuit for driving a display panel to display, the display panel comprising a plurality of sub-pixels arranged in an array of M rows and N columns, each sub-pixel comprising a pixel electrode, M being an even number greater than 1, and N being an integer greater than 1, characterized in that, The driving circuit includes: A compensation circuit is electrically connected to the first pixel electrode and the second pixel electrode in the same column of sub-pixels, respectively; wherein the first pixel electrode is the pixel electrode of the sub-pixel located in the Mth row, and the second pixel electrode is the pixel electrode of the sub-pixel located in the (M-1)th row; and A timing controller is electrically connected to the compensation circuit. The timing controller is used to output a compensation start signal to the compensation circuit during the vertical blanking phase of the current frame when the display panel is running in hardware super-resolution mode. The compensation circuit responds to the compensation start signal output by the timing controller, performs voltage detection on the first pixel electrode to obtain a first voltage, performs voltage detection on the second pixel electrode to obtain a second voltage, and performs voltage compensation on the first pixel electrode based on the first voltage and the second voltage, so that the difference between the voltage of the first pixel electrode and the voltage of the second pixel electrode is less than or equal to a preset voltage value.

2. The driving circuit as described in claim 1, characterized in that, The timing controller is used to output a compensation start signal to the compensation circuit during the vertical blanking phase of the current frame when the display panel is running in hardware super-resolution mode and the number of non-zero grayscale sub-pixels in the M-1th row of sub-pixels is greater than or equal to a preset number based on the image data of the current frame; wherein, the non-zero grayscale sub-pixels are sub-pixels whose target grayscale is not zero.

3. The driving circuit as described in claim 1, characterized in that, The compensation circuit includes: Control circuit; A switching circuit is electrically connected to the control circuit, the first pixel electrode, the second pixel electrode, and the timing controller, respectively. In response to a compensation start signal output by the timing controller, the switching circuit connects the control circuit to the first pixel electrode and the second pixel electrode. The amplifier circuit is electrically connected to the switching circuit, the first pixel electrode, and the control circuit, respectively. The control circuit is used to detect the voltage of the first pixel electrode to obtain a first voltage, detect the voltage of the second pixel electrode to obtain a second voltage, and based on the first voltage and the second voltage, control the amplification circuit to amplify the first voltage to obtain a third voltage, and output the third voltage to the first pixel electrode to achieve voltage compensation of the first pixel electrode.

4. The driving circuit as described in claim 3, characterized in that, The amplifier circuit includes: An operational amplifier includes a non-inverting input terminal, an inverting input terminal, and an output terminal. The non-inverting input terminal is electrically connected to the switching circuit, and the output terminal is electrically connected to the first pixel electrode. The first resistor is electrically connected between the inverting input of the operational amplifier and ground; and The second resistor is electrically connected between the inverting input terminal and the output terminal of the operational amplifier, and the second resistor is an adjustable resistor; The control circuit is electrically connected to the second resistor. The control circuit determines the target resistance value of the second resistor based on the first voltage and the second voltage, and adjusts the resistance value of the second resistor to the target resistance value, so that the operational amplifier, in conjunction with the first resistor and the second resistor, amplifies the first voltage to obtain the third voltage and outputs the third voltage to the first pixel electrode.

5. The driving circuit as described in claim 4, characterized in that, The control circuit is used to calculate the target resistance value of the second resistor using the following formula: V2 / V1 = 1 + R2 / R1; Wherein, V1 is the first voltage, V2 is the second voltage, R1 is the resistance value of the first resistor, and R2 is the target resistance value of the second resistor.

6. The driving circuit as described in claim 4, characterized in that, The driving circuit includes N compensation circuits, each corresponding to one of the N columns of sub-pixels; wherein the i-th compensation circuit of the N compensation circuits is electrically connected to the first pixel electrode and the second pixel electrode of the i-th column of the N columns of sub-pixels respectively; wherein 1≤i≤N.

7. The driving circuit as described in claim 3, characterized in that, The switching circuit includes: The first switching transistor includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the first switching transistor is electrically connected to the first pixel electrode, the second connection terminal of the first switching transistor is electrically connected to the control circuit, and the control terminal of the first switching transistor is electrically connected to the timing controller. The first switching transistor turns on the electrical connection between the first pixel electrode and the control circuit in response to the compensation start signal output by the timing controller. The second switch includes a first connection terminal, a second connection terminal, and a control terminal. The first connection terminal of the second switch is electrically connected to the second pixel electrode, the second connection terminal of the second switch is electrically connected to the control circuit, and the control terminal of the second switch is electrically connected to the timing controller. The second switch responds to the compensation start signal output by the timing controller to turn on the electrical connection between the second pixel electrode and the control circuit.

8. The driving circuit as described in claim 1, characterized in that, The display panel includes M scan lines and N data lines; the M scan lines are electrically connected to M rows of sub-pixels in a one-to-one correspondence, and the N data lines are electrically connected to N columns of sub-pixels in a one-to-one correspondence. The driving circuit also includes: A scan driver is electrically connected to each of the M scan lines. The scan driver is used to output corresponding scan signals to the M scan lines during the effective display phase of the current frame to scan the M rows of sub-pixels sequentially. The data driver is electrically connected to each of the N data lines; and The power management chip is electrically connected to the data driver and the timing controller, respectively. The timing controller is further configured to, when the display panel is running in hardware super-resolution mode and when the scan driver finishes scanning the (M-1)th row of sub-pixels in the display panel, output a corresponding voltage adjustment signal to the power management chip, so that the power management chip outputs a first analog power supply voltage to the data driver; the power management chip is further configured to output a second analog power supply voltage to the data driver when it does not receive the voltage adjustment signal; wherein, the first analog power supply voltage is higher than the second analog power supply voltage; The data driver is used to receive the analog power supply voltage output by the power management chip, and output the corresponding data voltage to the N data lines based on the received analog power supply voltage to charge the scanned sub-pixels; wherein the analog power supply voltage includes the first analog power supply voltage and the second analog power supply voltage.

9. The driving circuit as described in claim 8, characterized in that, The first analog supply voltage and the second analog supply voltage satisfy the following relationship: AVDD1 = K × AVDD2; Wherein, AVDD1 is the first analog power supply voltage, AVDD2 is the second analog power supply voltage, and K≥2.

10. A display device, characterized in that, The display device includes: Display panel; and The driving circuit according to any one of claims 1 to 9, wherein the driving circuit is electrically connected to the display panel, and the driving circuit is used to drive the display panel to perform display.

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