Gate driving circuit and driving method thereof, display panel, display device

Abstract

The application discloses a gate driving circuit and a driving method thereof, a display panel and a display device. The gate driving circuit comprises an input module, an inverting and maintaining module, a bootstrap module and an output module. The input module transmits a starting signal input by an input end to a first node. The inverting and maintaining module is used for outputting an inverting potential of the first node at a second node. The output module is controlled by a potential of the second node to output an output signal with a potential of a first power signal at an output end, or is controlled by a potential of a third node to output an output signal with a potential of a second power signal at the output end. When the output signal has the potential of the first power signal, the bootstrap module controls a pull-down signal to be electrically isolated from the third node with the first power signal, or the bootstrap module pulls down the potential of the third node in the process that the output signal has the potential of the second power signal. The complexity of the gate driving circuit is simplified, and the stability of the output signal can be provided.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a gate driving circuit and its driving method, a display panel, and a display device. Background Technology

[0002] The display panel contains a gate drive circuit to provide gate drive signals to the pixel circuits within the panel. Low-Temperature Poly-Silicon Thin Film Transistors (LTPS TFTs) offer advantages such as high mobility and stable characteristics. However, when a full LTPS TFT is used for the gate drive circuit, its design becomes more complex, requiring more transistors and capacitors. Eliminating the falling edge step of the gate drive signal output from the circuit further increases the complexity by necessitating even more transistors and capacitors. Additionally, the gate drive signal exhibits a floating state, leading to instability. Summary of the Invention

[0003] The present invention provides a gate driving circuit and driving method thereof, a display panel and a display device, to simplify the complexity of the gate driving circuit and at the same time provide stability of the output signal.

[0004] In a first aspect, embodiments of the present invention provide a gate driving circuit, comprising:

[0005] An input module includes an input terminal and a first node. The input module is controlled by a first clock signal and an inverted signal of the first clock signal, and transmits the start signal input from the input terminal to the first node.

[0006] An inverting sustaining module includes a second node connected to a first node. The inverting sustaining module is used to maintain the potential of the first node and is controlled by the potential of the first node to transmit a first power signal or a second power signal to the second node so as to output the inverted potential of the first node at the second node. The potential of the first power signal is greater than the potential of the second power signal.

[0007] The bootstrap module includes a third node connected to the first node, the bootstrap module is connected to the second node and is connected to a pull-down signal with a first potential, the first potential being less than the potential of the first power signal;

[0008] An output module includes an output terminal. The output module is connected to the second node and the third node respectively. The output module is controlled by the potential of the second node and outputs an output signal with the potential of the first power signal at the output terminal. Alternatively, it is controlled by the potential of the third node and outputs the output signal with the potential of the second power signal at the output terminal.

[0009] Specifically, when the output signal has the potential of the first power signal, the bootstrap module is controlled by the potential of the second node to control the pull-down signal to be electrically isolated from the third node using the first power signal; or, during the process of the output signal having the potential of the second power signal, the bootstrap module is controlled by the start signal to couple the first potential of the pull-down signal to pull down the potential of the third node.

[0010] Optionally, the inverting sustaining module further includes an inverter and a first capacitor;

[0011] The input terminal of the inverter and the first terminal of the first capacitor are connected to the first node. The first power supply terminal of the inverter is used to input the first power signal, and the second power supply terminal of the inverter and the second terminal of the first capacitor are used to input the second power signal. The output terminal of the inverter is connected to the second node. The inverter is used to output the first power signal when the potential of the first node is low and to output the second power signal when the potential of the first node is high.

[0012] Optionally, the inverter includes a first transistor and a second transistor; the gate of the first transistor and the first gate of the second transistor are connected to the first node, the first terminal of the first transistor is used to input the first power supply signal, the second terminals of the first transistor and the second terminal of the second transistor are connected to the second node, and the first terminal of the second transistor is used to input the second power supply signal; the first transistor is a P-type transistor and the second transistor is an N-type transistor;

[0013] Preferably, the second transistor further includes a second gate for inputting a third power supply signal, the level of which is lower than the level of the second power supply signal.

[0014] Optionally, the input module further includes a third transistor and a fourth transistor;

[0015] The first terminals of the third transistor and the fourth transistor are connected to the input terminal. The third gate of the third transistor is used to input the inverted signal of the first clock signal, and the gate of the fourth transistor is used to input the first clock signal. The second terminals of the third transistor and the fourth transistor are connected to the first node. The third transistor is an N-type transistor, and the fourth transistor is a P-type transistor.

[0016] Preferably, the third transistor further includes a fourth gate, which is used to input a third power supply signal, the level of which is lower than the level of the second power supply signal.

[0017] Optionally, the bootstrap module further includes a first node control unit, a fourth node, a coupling unit, a fifth node, a second node control unit, and a switching unit;

[0018] The first control terminal of the first node control unit is used to input the first clock signal, the input terminal of the first node control unit is connected to the input terminal, and the output terminal of the first node control unit is connected to the fourth node; the control terminal and input terminal of the switch unit are connected to the fourth node, and the output terminal of the switch unit is connected to the third node; the first terminal of the coupling unit is connected to the fourth node, the second terminal of the coupling unit is connected to the fifth node, the first control terminal of the second node control unit is connected to the second node, the second control terminal of the second node control unit is connected to the fourth node, the first input terminal of the second node control unit is used to input the first power signal, the second input terminal of the second node control unit is used to input the pull-down signal, and the output terminal of the second node control unit is connected to the fifth node;

[0019] When the output signal has the potential of the first power signal, the second node control unit is controlled by the potential of the second node and outputs the first power signal to the second terminal of the coupling unit. The coupling unit controls the disconnection between the input and output terminals of the switching unit with the first power signal. During the process when the output signal has the potential of the second power signal, the first node control unit controls the potential of the fourth node according to the start signal. The second node control unit is controlled by the potential of the fourth node and outputs the pull-down signal to the second terminal of the coupling unit. The coupling unit couples the first potential of the pull-down signal to control the conduction between the input and output terminals of the switching unit and pulls down the potential of the third node.

[0020] Optionally, the first node control unit includes a fifth transistor, the gate of which is used to input the first clock signal, the first terminal of which is connected to the input terminal, and the second terminal of which is connected to the fourth node;

[0021] Preferably, the fifth transistor is a P-type transistor.

[0022] Optionally, the coupling unit includes a second capacitor, the first terminal of which is connected to the fourth node, and the second terminal of which is connected to the fifth node.

[0023] Optionally, the second node control unit includes a sixth transistor and a seventh transistor;

[0024] The gate of the sixth transistor is connected to the fourth node, the first terminal of the sixth transistor is used to input the pull-down signal, the second terminal of the sixth transistor and the second terminal of the seventh transistor are connected to the fifth node, the gate of the seventh transistor is connected to the second node, and the first terminal of the seventh transistor is used to input the first power signal.

[0025] Preferably, the pull-down signal is a second clock signal;

[0026] Preferably, the first potential of the second clock signal lags behind the first potential of the first clock signal;

[0027] Preferably, the sixth transistor and the seventh transistor are P-type transistors.

[0028] Optionally, the switching unit includes an eighth transistor; the first terminal and gate of the eighth transistor are connected to the fourth node, and the second terminal of the eighth transistor is connected to the third node;

[0029] Preferably, the eighth transistor is a P-type transistor.

[0030] Optionally, the first node control unit further includes a ninth transistor;

[0031] The gate of the ninth transistor is used to input a first fixed potential signal; the first terminal of the ninth transistor is connected to the second terminal of the fifth transistor; the second terminal of the ninth transistor is connected to the fourth node; the ninth transistor is used to continuously conduct according to the first fixed potential signal.

[0032] Preferably, the ninth transistor is a P-type transistor, and the first fixed potential signal is the second power supply signal; or, the ninth transistor is an N-type transistor, and the first fixed potential signal is the first power supply signal.

[0033] Optionally, the output module includes a tenth transistor and an eleventh transistor;

[0034] The gate of the tenth transistor is connected to the third node, the first terminal of the tenth transistor is used to input the second power signal, the second terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and serves as the output terminal of the gate drive circuit; the gate of the eleventh transistor is connected to the second node, and the first terminal of the eleventh transistor is used to input the first power signal.

[0035] Preferably, both the tenth transistor and the eleventh transistor are P-type transistors.

[0036] Optionally, the gate drive circuit further includes a twelfth transistor, the gate of which is used to input a second fixed potential signal, the first terminal of which is connected to the first node, and the second terminal of which is connected to the third node;

[0037] Preferably, the twelfth transistor is a P-type transistor, and the second fixed potential signal is the second power supply signal; or, the twelfth transistor is an N-type transistor, and the second fixed potential signal is the first power supply signal.

[0038] Optionally, the gate drive circuit further includes:

[0039] The inverting module includes an inverting output terminal connected to the input module. The inverting module is controlled by the potential of the first clock signal to transmit the first power signal to the inverting output terminal, or to transmit the second power signal to the inverting output terminal, so as to output a signal with a potential opposite to that of the first clock signal at the inverting output terminal, as the inverted signal of the first clock signal.

[0040] Optionally, the inverting module includes a thirteenth transistor and a fourteenth transistor;

[0041] The fifth gate of the thirteenth transistor and the gate of the fourteenth transistor are used to input the first clock signal. The first terminal of the thirteenth transistor is used to input the second power signal. The second terminals of the thirteenth transistor and the fourteenth transistor are connected to the input module. The first terminal of the fourteenth transistor is used to input the first power signal. The thirteenth transistor is an N-type transistor, and the fourteenth transistor is a P-type transistor.

[0042] Preferably, the thirteenth transistor further includes a sixth gate, which is used to input a third power supply signal, the level of which is lower than the level of the second power supply signal.

[0043] In a second aspect, embodiments of the present invention also provide a driving method for a gate driving circuit, used to drive the gate driving circuit described in the first aspect, the driving method comprising:

[0044] In the first stage, the input module responds to the first clock signal and its inverted signal to transmit the start signal with a first control potential to the first node. The inverted sustaining module maintains the first control potential at the first node and responds to the first control potential by outputting a first inverted potential of the first control potential at the second node. The bootstrap module responds to the first inverted potential by controlling the pull-down signal to be electrically isolated from the third node with the first power supply signal. The output module responds to the first inverted potential by outputting an output signal with the potential of the first power supply signal at the output terminal, wherein the first control potential is greater than the first inverted potential.

[0045] In the second stage, the input module responds to the first clock signal and its inverted signal to transmit the start signal with a second control potential to the first node. The inverted sustaining module maintains the second control potential at the first node and responds to the second control potential by outputting a second inverted potential of the second control potential at the second node. The bootstrap module transmits the second control potential at the third node. The output module responds to the second control potential and outputs an output signal with a potential of the second power supply signal at the output terminal, wherein the second control potential is less than the second inverted potential.

[0046] In the third stage, the bootstrap module, controlled by the second control potential, couples the first potential of the pull-down signal to pull down the potential of the third node, wherein the first potential is less than the second control potential.

[0047] Thirdly, embodiments of the present invention also provide a display panel, including a start signal line, a first clock signal line, a second clock signal line, a first pull-down signal line, a second pull-down signal line, and a multi-level gate driving circuit as described in any one of claims 1-12;

[0048] The input terminal of the input module in the first-stage gate driving circuit is connected to the start signal line, and the input terminal of the input module in the next-stage gate driving circuit is connected to the output terminal of the output module in the previous-stage gate driving circuit. The first clock signal of the odd-numbered-stage gate driving circuit is provided by the first clock signal line, the inverted signal of the first clock signal of the odd-numbered-stage gate driving circuit is provided by the first clock signal line through the first inverter, and the pull-down signal of the odd-numbered-stage gate driving circuit is provided by the first pull-down signal line. The first clock signal of the even-numbered-stage gate driving circuit is provided by the second clock signal line, the inverted signal of the first clock signal of the even-numbered-stage gate driving circuit is provided by the second clock signal line through the second inverter, and the pull-down signal of the even-numbered-stage gate driving circuit is provided by the second pull-down signal line. The clock signal provided by the first clock signal line and the clock signal provided by the second clock signal line have the same waveform, the effective level of the clock signal provided by the first clock signal line leads the effective level of the clock signal provided by the second clock signal line, and the first potential of the pull-down signal provided by the first pull-down signal line leads the first potential of the pull-down signal provided by the second pull-down signal line.

[0049] Optionally, the second clock signal line is multiplexed as the first pull-down signal line, and the first clock signal line is multiplexed as the second pull-down signal line.

[0050] Fourthly, embodiments of the present invention also provide a display panel, including a start signal line, a first clock signal line, a second clock signal line, a first pull-down signal line, a second pull-down signal line, and a multi-level gate driving circuit as described in claim 13 or 14;

[0051] The input terminal of the input module in the first-stage gate driving circuit is connected to the start signal line, and the input terminal of the input module in the next-stage gate driving circuit is connected to the output terminal of the output module in the previous-stage gate driving circuit. The first clock signal of the odd-numbered-stage gate driving circuit is provided by the first clock signal line, and the pull-down signal of the odd-numbered-stage gate driving circuit is provided by the first pull-down signal line. The first clock signal of the even-numbered-stage gate driving circuit is provided by the second clock signal line, and the pull-down signal of the even-numbered-stage gate driving circuit is provided by the second pull-down signal line. The clock signal provided by the first clock signal line and the clock signal provided by the second clock signal line have the same waveform. The effective level of the clock signal provided by the first clock signal line leads the effective level of the clock signal provided by the second clock signal line, and the first potential of the pull-down signal provided by the first pull-down signal line leads the first potential of the pull-down signal provided by the second pull-down signal line.

[0052] Optionally, the second clock signal line is multiplexed as the first pull-down signal line, and the first clock signal line is multiplexed as the second pull-down signal line.

[0053] Fifthly, embodiments of the present invention also provide a display device, including a driving unit and a display panel as described in any one of claims 16 to 19; the driving unit is connected to the start signal line, the first clock signal line, the second clock signal line, the first pull-down signal line, and the second pull-down signal line, and is used to provide a start signal to the start signal line, a clock signal to the first clock signal line, a clock signal to the second clock signal line, a first pull-down signal to the first pull-down signal line, and a second pull-down signal to the second pull-down signal line.

[0054] The technical solution of this invention, by setting an inverting sustaining module to directly maintain and invert the potential of the first node, simplifies the structure of the gate drive circuit while ensuring its normal operation. Simultaneously, the bootstrap module is connected to the inverting sustaining module and controlled by the start signal. While ensuring the normal operation of the gate drive circuit, this allows the output module to always be controlled by the potential of the second node to output an output signal with a first power supply signal, or controlled by the potential of the third node to output an output signal with a second power supply signal. This avoids a floating state at the output terminal of the output module and improves the stability of the output signal. Furthermore, it ensures that the falling edge of the output signal is stepless, thereby improving the reliability of the output signal while simplifying the gate drive circuit structure. Moreover, the potential of the third node is lower than the first potential, resulting in a strong driving force when the output signal with the second power supply signal is output, further improving the stability of the output signal. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention;

[0056] Figure 2 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0057] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0058] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0059] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0060] Figure 6 for Figure 5 A waveform timing diagram of each signal corresponding to the provided gate drive circuit;

[0061] Figure 7 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention;

[0062] Figure 8 A schematic flowchart of a driving method for a gate driving circuit provided in an embodiment of the present invention;

[0063] Figure 9 This is a partial structural diagram of a display panel provided in an embodiment of the present invention;

[0064] Figure 10 A waveform diagram of the output signal of a four-stage gate drive circuit provided in an embodiment of the present invention;

[0065] Figure 11 A partial structural schematic diagram of another display panel provided in an embodiment of the present invention;

[0066] Figure 12 This is a schematic diagram of the structure of a display device provided in an embodiment of the present invention. Detailed Implementation

[0067] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and not intended to limit it. Furthermore, it should be noted that, for ease of description, the accompanying drawings show only the parts relevant to the present invention, and not all of the structures.

[0068] Figure 1 This is a schematic diagram of a gate driving circuit provided in an embodiment of the present invention. Figure 1 As shown, the gate drive circuit includes:

[0069] The input module 10 includes an input terminal and a first node N1. The input module 10 is controlled by the first clock signal ECK1 and the inverted signal ECK1B of the first clock signal, and transmits the start signal EIN input from the input terminal to the first node N1.

[0070] The inverting sustaining module 20 includes a second node N2. The inverting sustaining module 20 is connected to the first node N1. The inverting sustaining module 20 is used to maintain the potential of the first node N1 and is controlled by the potential of the first node N1. It transmits a first power signal VGH or a second power signal VGL to the second node N2 so as to output the inverted potential of the first node N1 at the second node N2. The potential of the first power signal VGH is greater than the potential of the second power signal VGL.

[0071] The bootstrap module 30 includes a third node N3 connected to the first node N1, the bootstrap module 30 is connected to the second node N2, and is connected to a pull-down signal EK with a first potential, the first potential being less than the potential of the first power signal VGH.

[0072] The output module 40 includes an output terminal. The output module 40 is connected to the second node N3 and the third node N3 respectively. The output module 40 is controlled by the potential of the second node N2 and outputs an output signal EM with the potential of the first power signal VGH at the output terminal, or is controlled by the potential of the third node N3 and outputs an output signal EM with the potential of the second power signal VGL at the output terminal.

[0073] Specifically, when the output signal EM has the potential of the first power signal VGH, the bootstrap module 30 is controlled by the potential of the second node N2 to control the pull-down signal EK to be electrically isolated from the third node N3 by the first power signal VGH. Alternatively, when the output signal EM has the potential of the second power signal VGL, the bootstrap module 30 is controlled by the start signal EIN to couple the first potential of the pull-down signal EK to pull down the potential of the third node N3.

[0074] Specifically, input module 10 can connect its input terminal and first node N1 when the first clock signal ECK1 is valid, thereby transmitting the start signal EIN to the first node N1. The start time of the valid level of the start signal EIN can precede the start time of the valid level of the first clock signal ECK1, allowing input module 10 to delay the transmission of the start signal EIN to the first node N1, which is used to shift the output signal EM relative to the start signal EIN. Inverting and sustaining module 20 can maintain the potential of the first node N1 and invert the potential of the first node N1, so that the potential of the second node N2 is opposite to the potential of the first node N1. At this time, inverting and sustaining module 20 can directly invert the potential of the first node N1, which simplifies the structure of the gate drive circuit while ensuring the normal operation of the gate drive circuit. For example, the start signal EIN can include a high-level potential and a low-level potential. When the start signal EIN is a high-level potential, inverting and sustaining module 20 outputs a second power supply signal VGL at the second node N2. When the start signal EIN is at a low level, the inverting sustain module 20 outputs a first power signal VGH at the second node N2. Both the first power signal VGH and the second power signal VGL can be signals with fixed potentials. For example, the first power signal VGH can be a 7V signal, and the second power signal VGL can be a -7V signal.

[0075] The potential of the pull-down signal EK can include a first potential and a second potential, where the first potential is lower than the second potential. When the pull-down signal EK jumps from the second potential to the first potential, the bootstrap module 30 can couple the first potential to pull down the potential of the third node N3, making the potential of the third node N3 lower than the potential of the starting signal EIN. When the second node N2 outputs the first power supply signal VGH, the bootstrap module 30, controlled by the starting signal EIN, couples the first potential of the pull-down signal EK to pull down the potential of the third node N3. At this time, the output module 40 can be controlled by the potential of the third node N3, outputting an output signal EM with the potential of the second power supply signal VGL at the output terminal. Simultaneously, the output module 40 has a self-coupling effect, ensuring that the falling edge of the output signal EM is stepless, thereby improving the reliability of the output signal EM while simplifying the gate drive circuit structure. Moreover, the lower potential of the third node N3 compared to the first potential provides a strong driving force when the output signal EM with the potential of the second power supply signal VGL is output, improving the stability of the output signal EM.

[0076] When the second node N2 outputs the second power supply signal VGL, the bootstrap module 30, controlled by the potential of the second node N2, uses the first power supply signal VGH to control the pull-down signal EK, which is electrically isolated from the third node N3. The output module 40, controlled by the potential of the second node N2, outputs an output signal EM with the potential of the first power supply signal VGH at its output terminal. Thus, the bootstrap module 30 can be connected to the inverting sustaining module 20 and controlled by the start signal EIN. This ensures the normal operation of the gate drive circuit while preventing a floating state at the output terminal of the output module 40, further improving the stability of the output signal.

[0077] The technical solution of this embodiment directly maintains and inverts the potential of the first node by setting an inverting sustain module. This simplifies the structure of the gate drive circuit while ensuring its normal operation. Simultaneously, the bootstrap module is connected to the inverting sustain module and controlled by the start signal. While ensuring the normal operation of the gate drive circuit, this allows the output module to always be controlled by the potential of the second node, outputting a potential with the first power signal, or controlled by the potential of the third node, outputting a potential with the second power signal. This avoids a floating state at the output terminal of the output module and improves the stability of the output signal. Furthermore, it ensures a stepless falling edge for the output signal, thereby improving the reliability of the output signal while simplifying the gate drive circuit structure. Moreover, the potential of the third node is lower than the first potential, providing a strong driving force when outputting a potential with the second power signal, further enhancing the stability of the output signal.

[0078] Figure 2 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 2 As shown, the inverting sustaining module 20 also includes an inverter 21 and a first capacitor C1; the input terminal of the inverter 21 and the first terminal of the first capacitor C1 are connected to the first node N1, the first power supply terminal of the inverter 21 is used to input the first power supply signal VGH, and the second power supply terminal of the inverter 21 and the second terminal of the first capacitor C1 are used to input the second power supply signal VGL; the output terminal of the inverter 21 is connected to the second node N2, and the inverter 21 is used to output the first power supply signal VGH when the potential of the first node N1 is low, and to output the second power supply signal VGL when the potential of the first node N1 is high.

[0079] Specifically, the second terminal of the first capacitor C1 is input with the second power supply signal VGL, which can fix the potential of the second terminal of the first capacitor C1. The first terminal of the first capacitor C1 is connected to the first node N1, so that the first capacitor C1 can maintain the potential of the first node N1. At the same time, the inverter 21 inverts the potential of the first node N1. When the start signal EIN is high, the second node N2 outputs the second power supply signal VGL, and the output module 40 is controlled by the potential of the second node N2, outputting an output signal EM with the potential of the first power supply signal VGH at its output terminal. Thus, the first power supply signal VGH can be output with a delay relative to the start signal EIN, realizing the shift output of the gate drive circuit. When the start signal EIN is low, the second node N2 outputs the first power supply signal VGH, and the bootstrap module 30 is controlled by the start signal EIN, coupling the first potential of the pull-down signal EK to pull down the potential of the third node N3. At this time, the output module 40 can be controlled by the potential of the third node N3, outputting an output signal EM with the potential of the second power supply signal VGL at its output terminal. This simplifies the complexity of the gate drive circuit by using the structure of inverter 21, first capacitor C1 and bootstrap module 30, while ensuring the normal operation of the gate drive circuit.

[0080] Continue to refer to Figure 2 The inverter 21 includes a first transistor T1 and a second transistor T2; the gate of the first transistor T1 and the first gate of the second transistor T2 are connected to the first node N1, the first terminal of the first transistor T1 is used to input the first power supply signal VGH, the second terminal of the first transistor T1 and the second terminal of the second transistor T2 are connected to the second node N2, and the first terminal of the second transistor T2 is used to input the second power supply signal VGL; the first transistor T1 is a P-type transistor and the second transistor T2 is an N-type transistor.

[0081] Specifically, the first transistor T1 is a P-type transistor, and the second transistor T2 is an N-type transistor. For example, the first transistor T1 can be an LTPS transistor, and the second transistor T2 can be an Indium Gallium Zinc Oxide Thin Film Transistor (IGZO TFT). When the potential of the first node N1 is high, the first transistor T1 is off, and the second transistor T2 is on. The second transistor T2 transmits the second power supply signal VGL input from the first terminal to the second node N2, making the potential of the second node N2 low, opposite to the potential of the first node N1. When the potential of the first node N1 is low, the first transistor T1 is on, and the second transistor T2 is off. The first transistor T1 transmits the first power supply signal VGH input from the first terminal to the second node N2, making the potential of the second node N2 high, opposite to the potential of the first node N1. In this way, the gate drive circuit only needs two transistors to achieve the inversion function of the inverter 21, simplifying the structure and complexity of the gate drive circuit while ensuring its normal operation.

[0082] In some embodiments, the second transistor T2 further includes a second gate for inputting a third power supply signal VGLL, the level of which is lower than the level of the second power supply signal VGL.

[0083] Specifically, the second transistor T2 can be a dual-gate transistor. The level of the third power supply signal VGLL is lower than the level of the second power supply signal VGL. When the third power supply signal VGLL is input to the second gate of the second transistor T2, the threshold voltage of the second transistor T2 can be shifted positively, causing the threshold voltage of the second transistor T2 to approach 0 from a negative state. This avoids the phenomenon that the second transistor T2 cannot be turned off when the voltage difference between the gate and the first electrode is equal to 0, thus improving the reliability of the inverter 21 and consequently improving the reliability of the gate drive circuit.

[0084] Figure 3 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 3 As shown, the input module 10 also includes a third transistor T3 and a fourth transistor T4; the first terminal of the third transistor T3 and the first terminal of the fourth transistor T4 are connected to the input terminal, the third gate of the third transistor T3 is used to input the inverted signal ECK1B of the first clock signal, the gate of the fourth transistor T4 is used to input the first clock signal ECK1, and the second terminals of the third transistor T3 and the fourth transistor T4 are connected to the first node N1; the third transistor T3 is an N-type transistor, and the fourth transistor T4 is a P-type transistor.

[0085] Specifically, the third transistor T3 can be an IGZO TFT, and the fourth transistor T4 can be an LTPS TFT. When the start signal EIN is high, and the first clock signal ECK1 is low and its inverted signal ECK1B is high, both the third transistor T3 and the fourth transistor T4 are turned on. When the start signal EIN is low, the difference between the potential of the start signal EIN and the potential of the first clock signal ECK1 approaches 0, and the start signal EIN has a certain voltage drop when passing through the third transistor T3. At this time, the fourth transistor T4 can compensate for the on-state voltage drop of the third transistor T3, making the potential of the first node N1 approach the low level potential of the start signal EIN. When the start signal EIN is high, the difference between the potential of the start signal EIN and the potential of the inverted signal ECK1B approaches 0, and the start signal EIN has a certain voltage drop when passing through the fourth transistor T4. At this time, the third transistor T3 can compensate for the on-state voltage drop of the fourth transistor T4, making the potential of the first node N1 approach the high level potential of the start signal EIN. This ensures the accuracy of the input module 10 in transmitting the start signal EIN, whether the start signal EIN is high or low.

[0086] In some embodiments, the third transistor T3 further includes a fourth gate for inputting a third power supply signal VGLL, the level of which is lower than the level of the second power supply signal VGL.

[0087] Specifically, the third transistor T3 can be a dual-gate transistor. The level of the third power supply signal VGLL is lower than the level of the second power supply signal VGL. When the third power supply signal VGLL is input to the fourth gate of the third transistor T3, the threshold voltage of the third transistor T3 can be shifted positively, causing the threshold voltage of the third transistor T3 to approach 0 from a negative state. This avoids the phenomenon that the third transistor T3 cannot be turned off when the voltage difference between the gate and the first electrode is equal to 0, thus improving the reliability of the input module 10 and consequently improving the reliability of the gate drive circuit.

[0088] Figure 4 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 4As shown, the bootstrap module 30 also includes a first node control unit 31, a fourth node N4, a coupling unit 32, a fifth node N5, a second node control unit 33, and a switching unit 34; the first control terminal of the first node control unit 31 is used to input the first clock signal ECK1, the input terminal of the first node control unit 31 is connected to the input terminal, and the output terminal of the first node control unit 31 is connected to the fourth node N4; the control terminal and input terminal of the switching unit 34 are connected to the fourth node N4, and the output terminal of the switching unit 34 is connected to the third node N3; the first terminal of the coupling unit 32 is connected to the fourth node N4, the second terminal of the coupling unit 32 is connected to the fifth node N5, the first control terminal of the second node control unit 33 is connected to the second node N3, the second control terminal of the second node control unit 33 is connected to the fourth node N4, the first input terminal of the second node control unit 33 is used to input the first power signal VGH, and the second node... The second input terminal of the control unit 33 is used to input the pull-down signal EK, and the output terminal of the second node control unit 33 is connected to the fifth node N5. When the output signal EM has the potential of the first power signal VGH, the second node control unit 33 is controlled by the potential of the second node N2 and outputs the first power signal VGH to the second terminal of the coupling unit 32. The coupling unit 32 controls the input and output terminals of the switching unit 34 to disconnect with the first power signal VGH. During the process when the output signal EM has the potential of the second power signal VGL, the first node control unit 31 controls the potential of the fourth node N4 according to the start signal EIN. The second node control unit 33 is controlled by the potential of the fourth node N4 and outputs the pull-down signal EK to the second terminal of the coupling unit 32. The coupling unit 32 couples the first potential of the pull-down signal EK to control the conduction between the input and output terminals of the switching unit 34 and pull down the potential of the third node N3.

[0089] Specifically, the input terminal of the first node control unit 31 is connected to the input terminal to input the start signal EIN. During the operation of the gate drive circuit, when the output signal EM has the potential of the first power signal VGH, the second node control unit 33 is controlled by the potential of the second node N2 and outputs the first power signal VGH to the second terminal of the coupling unit 32. The coupling unit 32 controls the disconnection between the input and output terminals of the switching unit 34 with the first power signal VGH. At this time, the potential of the third node N3 is controlled by the potential of the first node N1, causing the output module 40 to stop outputting the second power signal VGL. During the process when the output signal EM has the potential of the second power signal VGL, the output module 40 is controlled by the potential of the second node N2 to stop outputting the first power signal VGH, and the potential of the third node N3 is controlled by the potential of the first node N1, which is opposite to the potential of the second node N2. The output module 40 is controlled by the potential of the third node N3 to output the second power signal VGL. Then, the first node control unit 31 controls the potential of the fourth node N4 according to the start signal EIN, making the potential of the fourth node N4 opposite to that of the second node N2. The second node control unit 33, controlled by the potential of the fourth node N4, outputs a pull-down signal EK to the second terminal of the coupling unit 32. When the potential of the pull-down signal EK jumps to the first potential, the coupling effect of the coupling unit 32 allows the potential of the fourth node N4 to continue to pull down. At this time, the potential of the fourth node N4 is less than the first potential and also less than the potential of the second power signal VGL. The switching unit 34 connects the input and output terminals under the influence of the potential of the fourth node N4, allowing the potential of the fourth node N4 to be transmitted to the third node N3, thus pulling down the potential of the third node N3. At this time, the output module 40, controlled by the potential of the third node N3, outputs the second power signal VGL. This not only achieves complete output of the second power signal VGL, improving the accuracy of the output signal EM, but also improves the driving capability of the output module 40. When the gate drive circuit outputs the output signal EM at the potential of the second power signal VGL for a long time, it can maintain the stability of the output signal EM.

[0090] Continue to refer to Figure 4 The first node control unit 31 includes a fifth transistor T5. The gate of the fifth transistor T5 is used to input the first clock signal ECK1. The first terminal of the fifth transistor T5 is connected to the input terminal, and the second terminal of the fifth transistor T5 is connected to the fourth node N4.

[0091] Specifically, Figure 4 The example shows that the fifth transistor T5 is a P-type transistor, such as an LTPS TFT. When the first clock signal ECK1 is low, the fifth transistor T5 can transmit the start signal EIN to the fourth node N4 to control the potential of the fourth node N4.

[0092] Continue to refer to Figure 4 The coupling unit 65 includes a second capacitor C2, the first terminal of the second capacitor C2 is connected to the fourth node N4, and the second terminal of the second capacitor C2 is connected to the fifth node N5.

[0093] Specifically, during the process where the output signal EM has the potential of the second power supply signal VGL, the first node control unit 31 controls the potential of the fourth node N4 according to the start signal EIN. The second node control unit 33, controlled by the potential of the fourth node N4, outputs a pull-down signal EK to the second terminal of the coupling unit 32. Then, when the potential of the pull-down signal EK jumps to the first potential, the first node control unit 31 stops outputting the start signal EIN to the fourth node N4 according to the first clock signal ECK1, and the potential of the fourth node N4 is in a floating state. When the potential of the pull-down signal EK is transmitted from the second node control unit 33 to the second terminal of the second capacitor C2, the coupling effect of the second capacitor C2 pulls down the potential of the fourth node N4, causing the potential of the fourth node N4 to continue to drop from the low level of the start signal EIN to an even lower level. At this time, the switching unit 34 connects the input and output terminals under the action of the potential of the fourth node N4, so that the potential of the fourth node N4 is transmitted to the third node N3, pulling down the potential of the third node N3.

[0094] Continue to refer to Figure 4 The second node control unit 33 includes a sixth transistor T6 and a seventh transistor T7; the gate of the sixth transistor T6 is connected to the fourth node N4, the first terminal of the sixth transistor T6 is used to input the pull-down signal EK, the second terminals of the sixth transistor T6 and the seventh transistor T7 are connected to the fifth node N5, the gate of the seventh transistor T7 is connected to the second node N2, and the first terminal of the seventh transistor T7 is used to input the first power supply signal VGH.

[0095] Specifically, Figure 4The example illustrates that the sixth transistor T6 and the seventh transistor T7 are P-type transistors, such as LTPS TFTs. When the output signal EM has the potential of the first power signal VGH, the potential of the second node N2 is low, the seventh transistor T7 is turned on, and the first power signal VGH is transmitted to the fifth node N5 through the seventh transistor T7. At this time, the first node N1 is high, and the fourth node N4 is in a floating state. The coupling unit 32 couples the first power signal VGH, making the fourth node N4 high, thus disconnecting the input and output terminals of the control switching unit 34. The potential of the third node N3 is controlled by the potential of the first node N1, causing the output module 40 to stop outputting the second power signal VGL. During the process where the output signal EM has the potential of the second power signal VGL, the potential of the second node N2 is high, and the seventh transistor T7 is turned off. The output module 40 stops outputting the first power signal VGH under the control of the potential of the second node N2. The potential of the first node N1 is low, and the third node N3 is controlled by the potential of the first node N1, which is opposite to the potential of the second node N2. Output module 40 outputs a second power signal VGL controlled by the potential of the third node N3. Simultaneously, the first node control unit 31 outputs a start signal EIN, and the potential of the fourth node N4 is controlled by the start signal EIN to be low, turning on the sixth transistor T6. The pull-down signal EK is transmitted to the fifth node N5 via the sixth transistor T6. When the first clock signal ECK1 and the pull-down signal EK transition, the first node control unit 31 stops outputting the start signal EIN to the fourth node N4, and the fourth node N4 becomes floating. When the pull-down signal EK transitions to the first potential, the coupling effect of the coupling unit 32 pulls down the potential of the fourth node N4, making it lower than the potential of the third node N3. Then, the switching unit 34 connects the input and output terminals, allowing the potential of the fourth node N4 to be transmitted to the third node N3, pulling down the potential of the third node N3 and improving the driving capability of the output module 40.

[0096] In some embodiments, the pull-down signal EK is the second clock signal ECK2, that is, the pull-down signal EK is a clock signal, so that when the pull-down signal EK jumps from a high level to a low level, the potential of the fourth node N4 is pulled down through the coupling effect of the coupling unit 32.

[0097] In some embodiments, the first potential of the second clock signal ECK2 lags behind the first potential of the first clock signal ECK1.

[0098] Specifically, the first potential can be a low level. By setting the first potential of the second clock signal ECK2 to lag behind the first potential of the first clock signal ECK1, the fifth transistor T5 can be turned on first by the low level of the first clock signal ECK1, transmitting the low level of the start signal EIN to the fourth node N4, controlling the sixth transistor T6 to turn on. The high level potential of the second clock signal ECK2 is transmitted to the second terminal of the second capacitor C2. Then, in the next stage, the second clock signal ECK2 jumps from high to low, the first clock signal ECK1 jumps from low to high, the fifth transistor T5 is turned off, making the fourth node N4 a floating state. At the same time, the low level of the second clock signal ECK2 is transmitted by the sixth transistor T6 to the second terminal of the second capacitor C2, so that the second capacitor C2 can pull down the potential of the fourth node N4 according to the jump of the second clock signal ECK2.

[0099] Continue to refer to Figure 4 The switching unit 34 includes an eighth transistor T8; the first terminal and gate of the eighth transistor T8 are connected to the fourth node N4, and the second terminal of the eighth transistor T8 is connected to the third node N3.

[0100] Specifically, Figure 4 The example shows the eighth transistor as a P-type transistor, such as an LTPS TFT. When the output signal EM has the potential of the first power supply signal VGH, the potential of the second node N2 is low, the seventh transistor T7 is turned on, and the first power supply signal VGH is transmitted to the fifth node N5 through the seventh transistor T7. The coupling unit 32 couples the first power supply signal VGH, making the fourth node N4 high and the eighth transistor T8 off. During the process when the output signal EM has the potential of the second power supply signal VGL, the first clock signal ECK1 is low, the start signal EIN is low, and the sixth transistor T6 is turned on. At the same time, the third node N3 is low, making the voltage difference between the gate and source of the eighth transistor T8 approach 0, and the eighth transistor T8 is in a near-on state. When the first clock signal ECK1 changes from low to high and the pull-down signal EK changes from high to low, the coupling effect of the coupling unit 32 pulls down the potential of the fourth node N4. The potential of the fourth node N4 is less than the potential of the third node N3. That is, the voltage difference between the gate and source of the eighth transistor T8 is less than the threshold voltage. The eighth transistor T8 is turned on, so that the potential of the fourth node N4 is transferred to the third node N3, thereby pulling down the potential of the third node N3 and improving the driving capability of the output module 40.

[0101] Continue to refer to Figure 4The first node control unit 31 also includes a ninth transistor T9; the gate of the ninth transistor T9 is used to input a first fixed potential signal V1, the first terminal of the ninth transistor T9 is connected to the second terminal of the fifth transistor T5, and the second terminal of the ninth transistor T9 is connected to the fourth node N4; the ninth transistor T9 is used to be continuously turned on according to the first fixed potential signal V1.

[0102] Specifically, the ninth transistor T9 is connected between the fifth transistor T5 and the fourth node N4. The ninth transistor T9 is continuously turned on according to the first fixed potential signal V1. When the potential of the fourth node N4 is pulled down to a lower potential, it can avoid damage caused by excessive potential difference between the gate and the second electrode of the fifth transistor T5, thus improving the reliability of the gate drive circuit.

[0103] For example, the ninth transistor T9 is a P-type transistor, and the first fixed potential signal V1 is the second power supply signal VGL, so that the ninth transistor T9 is continuously turned on; or, the ninth transistor T9 is an N-type transistor, and the first fixed potential signal V1 is the first power supply signal VGH, so that the ninth transistor T9 is continuously turned on.

[0104] Figure 5 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 5 As shown, the output module 40 includes a tenth transistor T10 and an eleventh transistor T11; the gate of the tenth transistor T10 is connected to the third node N3, the first terminal of the tenth transistor T10 is used to input the second power supply signal VGL, the second terminal of the tenth transistor T10 and the second terminal of the eleventh transistor T11 are connected and serve as the output terminal of the gate drive circuit; the gate of the eleventh transistor T11 is connected to the second node N2, and the first terminal of the eleventh transistor T11 is used to input the first power supply signal VGH.

[0105] Specifically, Figure 5The example illustrates that both the tenth transistor T10 and the eleventh transistor T11 are P-type transistors. When the potential of the second node N2 is low and the potential of the third node N3 is high, the eleventh transistor T11 is turned on, and the tenth transistor T10 is turned off. The first power supply signal VGH is transmitted to the output terminal through the eleventh transistor T11, and the output signal EM has the potential of the first power supply signal VGH. When the potential of the second node N2 is high and the potential of the third node N3 is low, the eleventh transistor T11 is turned off, and the tenth transistor T10 is turned on. The second power supply signal VGL is transmitted to the output terminal through the tenth transistor T10, and the output signal EM has the potential of the second power supply signal VGL. Moreover, when the potential of the third node N3 changes from high to low, the tenth transistor T10 turns on to output the second power supply signal VGL. Furthermore, the parasitic capacitance between the gate and the second electrode of the tenth transistor T10 pulls down the output signal EM, thereby ensuring that the transition of the output signal EM from the first power supply signal VGH to the second power supply signal VGL is stepless, improving the reliability of the output signal EM.

[0106] Continue to refer to Figure 5 The gate drive circuit also includes a twelfth transistor T12, the gate of which is used to input a second fixed potential signal V2, the first terminal of which is connected to the first node N1, and the second terminal of which is connected to the third node N3.

[0107] Specifically, the twelfth transistor T12 is connected between the first node N1 and the third node N3. The twelfth transistor T12 is continuously turned on according to the second fixed potential signal V2. When the potential of the third node N3 is pulled down to a lower potential, it can avoid damage caused by excessive potential difference between the gate and the second electrode of the third transistor T3 and the fourth transistor T4, thus improving the reliability of the gate drive circuit.

[0108] For example, the twelfth transistor T12 is a P-type transistor, and the second fixed potential signal V2 is the second power supply signal VGL; or, the twelfth transistor T12 is an N-type transistor, and the second fixed potential signal V2 is the first power supply signal VGH.

[0109] Figure 6 for Figure 5 The provided gate drive circuit provides a waveform timing diagram for each signal, where the horizontal axis represents time (s), the vertical axis represents voltage (U), n1 represents the timing of the potential of the first node N1, n2 represents the timing of the potential of the second node N2, n3 represents the timing of the potential of the third node N3, and n4 represents the timing of the potential of the fourth node N4. Simultaneously, the pull-down signal EK is multiplexed as the second clock signal ECK2. The following is a reference. Figure 5 and Figure 6 Explain the working process of the gate drive circuit.

[0110] In the first sub-stage t11, the start signal EIN is low. When the first clock signal ECK1 is low and the pull-down signal EK is high, the inverted signal ECK1B of the first clock signal is high. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on, and the start signal EIN is transmitted to the first node N1. At this time, the first transistor T1 is turned on, and the second transistor T2 is turned off, making the potential of the second node N2 the potential of the first power supply signal VGH, which is high. The third node N3 is low. Then the seventh transistor T7 is turned off, the eleventh transistor T11 is turned off, and the tenth transistor T10 is turned on. The second power supply signal VGL is transmitted to the output terminal through the tenth transistor T10, and the output signal EM is low. At this time, the fifth transistor T5 transmits the start signal EIN to the fourth node N4, the fourth node N4 is low, the sixth transistor T6 is turned on, and the pull-down signal EK is transmitted to the fifth node N5, and the eighth transistor T8 is turned off. When the first clock signal ECK1 is high and the pull-down signal EK is low, the potential of the first node N1 remains unchanged through the first capacitor C1, the potential of the second node N2 remains unchanged, and the pull-down signal EK changes from high to low. The coupling effect of the second capacitor C4 pulls down the potential of the fourth node N4, turns on the eighth transistor T8, pulls down the potential of the third node N3, and keeps the tenth transistor T10 on.

[0111] In the second sub-stage t12, the start signal EIN is high, the first clock signal ECK1 is high, and the inverted signal ECK1B of the first clock signal is low. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are off. The potential of the first node N1 is maintained low through the first capacitor C1, and the potential of the second node N2 remains unchanged. The potential of the fourth node N4 can be maintained constant through the second capacitor C2, or pulled down to a lower potential when the pull-down signal EK changes. At this time, the output signal EM continuously follows the potential of the second power supply signal VGL.

[0112] In the third sub-stage t13, the start signal EIN is high, the first clock signal ECK1 is low, the inverted signal ECK1B of the first clock signal is high, and the pull-down signal EK is high. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. The first node N1 is high. The first transistor T1 is turned off, and the second transistor T2 is turned on, making the potential of the second node N2 the potential of the second power supply signal VGL, which is low. The eleventh transistor T11 is turned on under the control of the second node N2, and the output signal EM is the potential of the first power supply signal VGH, which is high. The potential of the third node N3 is controlled by the potential of the first node N1, which is high. The tenth transistor T10 is turned off. Simultaneously, the seventh transistor T7 is turned on, and the first power supply signal VGH is transmitted to the fifth node N5 through the seventh transistor T7, and coupled to the potential of the fourth node N4 through the second capacitor C2, which is high. The sixth transistor T6 and the eighth transistor T8 are turned off.

[0113] In the fourth sub-stage t14, the start signal EIN remains high. During the transition between the first clock signal ECK1 and the pull-down signal EK, the potential of the first node N1 remains unchanged, and consequently, the potentials of the second node N2, the third node N3, and the fourth node N4 also remain unchanged. The output signal EM continuously outputs the potential of the first power supply signal VGH.

[0114] In the fifth sub-stage t15, the start signal EIN is low, and the first clock signal ECK1 is high. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are off. The potential of the first node N1 is maintained low through the first capacitor C1, while the potentials of the second node N2 and the third node N3 remain unchanged. The potential of the fourth node N4 is maintained constant through the second capacitor C2. The output signal EM continuously outputs the potential of the first power supply signal VGH.

[0115] In the sixth sub-stage t16, the start signal EIN is low, the first clock signal ECK1 is low, the inverted signal ECK1B of the first clock signal is high, and the pull-down signal EK is high. The third transistor T3, the fourth transistor T4, and the fifth transistor T5 are turned on. The first node N1 is low, the second node N2 is high, and the third node N3 is low. The tenth transistor T10 transmits the second power supply signal VGL to the output, making the potential of the output signal EM the potential of the second power supply signal VGL. Simultaneously, the potential of the third node N3 jumps from the high level of the fifth stage t15 to the low level of the current stage. The parasitic capacitance between the second terminal and the gate of the tenth transistor T10 pulls down the potential of the output signal EM, allowing the output signal EM to jump from high to low without a step, improving the stability and reliability of the output signal EM. Furthermore, the fifth transistor T5 transmits the start signal EIN to the fourth node N4, making the fourth node N4 low. When the sixth transistor T6 is turned on, the voltage difference between the gate and source of the eighth transistor T8 is greater than the threshold voltage, and the eighth transistor T8 is turned off.

[0116] In the seventh sub-stage t17, when the pull-down signal EK transitions from high to low, the potential of the fifth node N5 also transitions from high to low. The coupling effect of the second capacitor C2 pulls the potential of the fourth node N4 down to an extremely low level. The gate potential of the eighth transistor T8 is lower than the potential of the third node N3, so the eighth transistor T8 is turned on, transmitting the extremely low potential of the fourth node N4 to the third node N3. This improves the driving capability of the tenth transistor T10. When the output signal EM outputs the potential of the second power supply signal VGL for a long period, the stability of the output signal EM can be maintained.

[0117] Figure 7 This is a schematic diagram of another gate driving circuit provided in an embodiment of the present invention. Figure 7 As shown, the gate drive circuit also includes:

[0118] The inverting module 50 includes an inverting output terminal OUT connected to the input module 10. The inverting module 50 is controlled by the potential of the first clock signal ECK1 to transmit the first power signal VGH to the inverting output terminal OUT, or to transmit the second power signal VGL to the inverting output terminal OUT, so as to output a signal with a potential opposite to that of the first clock signal ECK1 at the inverting output terminal OUT, as the inverted signal ECK1B of the first clock signal.

[0119] Specifically, the inverting module 50 inverts the first clock signal ECK1 to form the inverted signal ECK1B of the first clock signal. This reduces the gate drive circuit's reliance on external signals and lowers the signal channel requirement of the display panel's driver chip. For example, continue to refer to... Figure 7The inverting module 50 includes a thirteenth transistor T13 and a fourteenth transistor T14; the fifth gate of the thirteenth transistor T13 and the gate of the fourteenth transistor T14 are used to input the first clock signal ECK1, the first terminal of the thirteenth transistor T13 is used to input the second power supply signal VGL, the second terminals of the thirteenth transistor T13 and the fourteenth transistor T14 are connected to the input module, and the first terminal of the fourteenth transistor T14 is used to input the first power supply signal VGH; the thirteenth transistor T13 is an N-type transistor, and the fourteenth transistor T14 is a P-type transistor.

[0120] Specifically, when the first clock signal ECK1 is low, the fourteenth transistor T14 is turned on, and the thirteenth transistor T13 is turned off. The first power supply signal VGH is transmitted to the input module 10 through the fourteenth transistor T14, serving as the inverted signal ECK1B of the first clock signal. When the first clock signal ECK1 is high, the fourteenth transistor T14 is turned off, and the thirteenth transistor T13 is turned on. The second power supply signal VGL is transmitted to the input module 10 through the thirteenth transistor T13, serving as the inverted signal ECK1B of the first clock signal.

[0121] In some embodiments, the thirteenth transistor T13 further includes a sixth gate, which is used to input a third power supply signal VGLL, the level of which is lower than the level of the second power supply signal VGL.

[0122] Specifically, the thirteenth transistor T13 can be a dual-gate transistor. The level of the third power supply signal VGLL is lower than the level of the second power supply signal VGL. When the third power supply signal VGLL is input to the sixth gate of the thirteenth transistor T13, the threshold voltage of the thirteenth transistor T13 can be shifted positively, causing the threshold voltage of the thirteenth transistor T13 to approach 0 from a negative state. This avoids the phenomenon that the thirteenth transistor T13 cannot be turned off when the voltage difference between the gate and the first electrode is equal to 0, improving the reliability of the inverting module 50, and thus improving the reliability of the gate drive circuit.

[0123] This invention also provides a driving method for a gate driving circuit. Figure 8 This is a schematic flowchart illustrating a driving method for a gate driving circuit according to an embodiment of the present invention. (See reference...) Figure 5 , Figure 6 and Figure 8 The driving method includes:

[0124] S110. In the first stage, the input module responds to the first clock signal and the inverted signal of the first clock signal, and transmits the start signal with the first control potential to the first node. The inverted sustaining module maintains the first control potential at the first node and responds to the first control potential, and outputs the first inverted potential of the first control potential at the second node. The bootstrap module responds to the first inverted potential and controls the pull-down signal to be electrically isolated from the third node with the first power supply signal. The output module responds to the first inverted potential and outputs an output signal with the potential of the first power supply signal at the output terminal, wherein the first control potential is greater than the first inverted potential.

[0125] Specifically, the first phase may include Figure 6 The process is divided into three sub-stages, t13 to t15. The first control potential can be high. In the first stage, when the start signal EIN is high, the input module 10 transmits the start signal EIN to the first node N1 when the first clock signal ECK1 is valid, making the first node N1 high. The inverting sustaining module 20 inverts the potential of the first node N1, and the first inverted potential of the second node N2 is low. The bootstrap module 30 responds to the first inverted potential of the second node N2 and controls the pull-down signal EK to be electrically isolated from the third node N3 by the first power signal VGH. The third node N3 is controlled to be high by the potential of the first node N1. The output module 40 responds to the first inverted potential of the second node N2 and outputs an output signal EM with the potential of the first power signal VGH at the output terminal. At this time, the output module 40 stops outputting the second power signal VGL in response to the potential of the third node N3. When the start signal EIN is low, the input module 10 stops transmitting the start signal EIN to the first node N1 when the first clock signal ECK1 is invalid, making the first node N1 maintain a high level. The potentials of the second node N2 and the third node N3 remain constant. The potential of the fourth node N4 can be maintained constant through the second capacitor C2. The output signal EM continuously outputs the potential of the first power supply signal VGH.

[0126] It should be noted that before the first stage, the operation of the gate drive circuit also includes a first sub-stage t11 and a second sub-stage t12. In the second sub-stage t12, the output signal EM is shifted relative to the start signal EIN.

[0127] S120. In the second stage, the input module responds to the first clock signal and the inverted signal of the first clock signal, and transmits the start signal with the second control potential to the first node. The inverted sustaining module maintains the second control potential at the first node and responds to the second control potential, and outputs the second inverted potential of the second control potential at the second node. The bootstrap module transmits the second control potential at the third node. The output module responds to the second control potential and outputs an output signal with the potential of the second power supply signal at the output terminal, wherein the second control potential is less than the second inverted potential.

[0128] Specifically, the second phase may include Figure 6 The sixth sub-stage t16. The second control potential can be low. In the second stage, the start signal EIN is low, and the first clock signal ECK1 is active. The input module 10 can transmit the start signal EIN to the first node N1, and the first node N1 is low. The inverting and holding module 20 inverts the potential of the first node N1, the second inverted potential of the second node N2 is high, the third node N3 is controlled by the second control potential of the first node N1, and outputs an output signal EM with the potential of the second power supply signal VGL at the output terminal.

[0129] S130. In the third stage, the bootstrap module is controlled by the second control potential and couples the first potential of the pull-down signal to the potential of the third node, wherein the first potential is less than the second control potential.

[0130] Specifically, the third phase may include Figure 6 The seventh sub-stage t17. The first potential can be low. In the third stage, the start signal EIN is at a low level, and the first clock signal ECK1 is at an invalid level. The bootstrap module 30 is controlled by the second control potential and couples the first potential of the pull-down signal EK, so that the potential of the third node N3 is coupled to a lower potential, thereby improving the driving capability of the output module 40 when outputting the potential of the second power signal VGL. When the output signal EM outputs the potential of the second power signal VGL for a long time, the stability of the output signal EM can be maintained.

[0131] The technical solution of this invention directly maintains and inverts the potential of the first node through an inverting sustain module, simplifying the structure of the gate drive circuit while ensuring its normal operation. Simultaneously, the bootstrap module is connected to the inverting sustain module and controlled by the start signal. While ensuring the normal operation of the gate drive circuit, this allows the output module to always be controlled by the potential of the second node to output a potential with the first power signal, or controlled by the potential of the third node to output a potential with the second power signal. This avoids a floating state at the output terminal of the output module and improves the stability of the output signal. Furthermore, it eliminates the step-like falling edge of the output signal, thereby improving the reliability of the output signal while simplifying the gate drive circuit structure. Moreover, the potential of the third node is lower than the first potential, resulting in a strong driving force when outputting a potential with the second power signal, further enhancing the stability of the output signal.

[0132] This invention also provides a display panel. Figure 9This is a partial structural diagram of a display panel provided in an embodiment of the present invention. Figure 9 As shown, the display panel includes a start signal line EN, a first clock signal line CK1, a second clock signal line CK2, a first pull-down signal line K1, a second pull-down signal line K2, and a multi-stage gate drive circuit GIP provided in this embodiment of the invention. In this case, the gate drive circuit GIP only includes an input module, an inverting sustain module, a bootstrap module, and an output module.

[0133] In the first-stage gate driver circuit (GIP), the input terminal of the input module is connected to the start signal line EN. In the next-stage gate driver circuit (GIP), the input terminal of the input module is connected to the output terminal of the previous-stage gate driver circuit (GIP). The first clock signal ECK1 of the odd-numbered stage gate driver circuit (GIP) is provided by the first clock signal line CK1. The inverted signal ECK1B of the first clock signal of the odd-numbered stage gate driver circuit (GIP) is provided by the first clock signal line CK1 via the first inverter F1. The pull-down signal EK of the odd-numbered stage gate driver circuit (GIP) is provided by the first pull-down signal line K1. The first clock signal ECK1 of the even-numbered stage gate driver circuit (GIP) is provided by the second clock signal line. The even-numbered gate drive circuit GIP's first clock signal ECK1B is provided by the second clock signal line CK2 via the second inverter F2. The even-numbered gate drive circuit GIP's pull-down signal EK is provided by the second pull-down signal line K2. The clock signal provided by the first clock signal line CK1 has the same waveform as the clock signal provided by the second clock signal line CK2. The effective level of the clock signal provided by the first clock signal line CK1 leads the effective level of the clock signal provided by the second clock signal line CK2. The first potential of the pull-down signal provided by the first pull-down signal line K1 leads the first potential of the pull-down signal provided by the second pull-down signal line K2.

[0134] Specifically, the first inverter F1 inverts the clock signal provided by the first clock signal line CK1, forming an inverted clock signal, which serves as the inverted first clock signal for the odd-level gate driver circuit GIP. The second inverter F2 inverts the clock signal provided by the second clock signal line CK2, forming an inverted clock signal, which serves as the inverted first clock signal for the even-level gate driver circuit GIP. Thus, the first clock signal ECK1 and its inverted signal ECK1B are provided to the odd-level gate driver circuit GIP via the first clock signal line CK1 and the first inverter F1, and the first pull-down signal line K1 provides the pull-down signal EK for the odd-level gate driver circuit GIP. Similarly, the first clock signal ECK1 and its inverted signal ECK1B are provided to the even-level gate driver circuit GIP via the second clock signal line CK2 and the second inverter F2, and the second pull-down signal line K2 provides the pull-down signal EK for the even-level gate driver circuit GIP. This ensures the normal operation of the multi-stage gate drive circuit (GIP) and provides the output signal EM by shifting the output terminal. For example, Figure 10 This is a waveform diagram of the output signal of a four-stage gate drive circuit provided in an embodiment of the present invention. The horizontal axis represents time, and the vertical axis represents voltage; ck1 represents the timing of the clock signal provided by the first clock signal line CK1, ck2 represents the timing of the clock signal provided by the second clock signal line CK2, and EM... <1> The timing of the output signal EM from the first-stage gate drive circuit GIP is as follows: EM <2> The timing of the output signal EM from the second-stage gate drive circuit GIP, EM <3> The timing of the output signal EM from the third-stage gate drive circuit GIP, EM <4> This refers to the timing of the output signal EM from the fourth-stage gate drive circuit GIP. For example... Figure 10 As shown, the multi-stage gate drive circuit GIP sequentially shifts and outputs the corresponding start signal EIN and output signal EM.

[0135] Since the display panel includes the gate driving circuit provided in the embodiments of the present invention, it has the same beneficial effects as the gate driving circuit provided in the embodiments of the present invention, which will not be described again here.

[0136] Continue to refer to Figure 9 The second clock signal line CK2 is multiplexed as the first pull-down signal line K1, and the first clock signal line CK1 is multiplexed as the second pull-down signal line K2. While meeting the signal requirements of the gate drive circuit, the signal channel requirements of the driver chip can be reduced, which helps to simplify the structure of the display panel and reduce the cost of the display panel.

[0137] This invention also provides a display panel. Figure 11 This is a partial structural diagram of another display panel provided in an embodiment of the present invention. Figure 11As shown, the display panel includes a start signal line EN, a first clock signal line CK1, a second clock signal line CK2, a first pull-down signal line K1, a second pull-down signal line K2, and a multi-stage gate drive circuit GIP provided in this embodiment of the invention. The gate drive circuit GIP includes an input module, an inverting sustain module, a bootstrap module, an output module, and an inverting module.

[0138] The input terminal of the input module in the first-stage gate drive circuit GIP is connected to the start signal line EN, and the input terminal of the input module in the next-stage gate drive circuit GIP is connected to the output terminal of the output module in the previous-stage gate drive circuit GIP. The first clock signal ECK1 of the odd-numbered gate drive circuit GIP is provided by the first clock signal line CK1, and the pull-down signal EK of the odd-numbered gate drive circuit GIP is provided by the first pull-down signal line K1. The first clock signal ECK1 of the even-numbered gate drive circuit GIP is provided by the second clock signal line CK2, and the pull-down signal EK of the even-numbered gate drive circuit GIP is provided by the second pull-down signal line K2. The clock signals provided by the first clock signal line CK1 and the clock signals provided by the second clock signal line CK2 have the same waveform. The effective level of the clock signal provided by the first clock signal line CK1 leads the effective level of the clock signal provided by the second clock signal line CK2. The first potential of the pull-down signal provided by the first pull-down signal line K1 leads the first potential of the pull-down signal provided by the second pull-down signal line K2.

[0139] Specifically, when the gate drive circuit includes an inverting module, the first clock signal ECK1 and the inverted signal ECK1B of each stage of the gate drive circuit can be provided by a single clock signal line, which can simplify the external structural setup of the gate drive circuit.

[0140] Since the display panel includes the gate driving circuit provided in the embodiments of the present invention, it has the same beneficial effects as the gate driving circuit provided in the embodiments of the present invention, which will not be described again here.

[0141] Continue to refer to Figure 11 The second clock signal line CK2 is multiplexed as the first pull-down signal line K1, and the first clock signal line CK1 is multiplexed as the second pull-down signal line K2. While meeting the signal requirements of the gate drive circuit, the signal channel requirements of the driver chip can be reduced, which helps to simplify the structure of the display panel and reduce the cost of the display panel.

[0142] This invention also provides a display device. Figure 12 This is a schematic diagram of a display device provided in an embodiment of the present invention. Figure 12As shown, the display device includes a driving unit 100 and a display panel 200 provided in any embodiment of the present invention. The driving unit 100 is connected to a start signal line EN, a first clock signal line CK1, a second clock signal line CK2, a first pull-down signal line K1, and a second pull-down signal line K2, and is used to provide a start signal to the start signal line EN, a clock signal to the first clock signal line CK1, a clock signal to the second clock signal line CK2, a first pull-down signal to the first pull-down signal line K1, and a second pull-down signal to the second pull-down signal line K2. Since the display device includes the display panel 200 provided in the embodiments of the present invention, it has the same beneficial effects as the display panel 200 provided in the embodiments of the present invention, and will not be described again here. The display device can be, for example, any product or component with display function such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, smart wearable device, or information kiosks in public lobbies.

[0143] Note that the above description is merely a preferred embodiment of the present invention and the technical principles employed. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and various obvious changes, readjustments, and substitutions can be made without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in detail through the above embodiments, the present invention is not limited to the above embodiments, and may include many other equivalent embodiments without departing from the concept of the present invention, the scope of which is determined by the scope of the appended claims.

Claims

1. A gate driving circuit, characterized in that, include: An input module includes an input terminal and a first node. The input module is controlled by a first clock signal and an inverted signal of the first clock signal, and transmits the start signal input from the input terminal to the first node. An inverting sustaining module includes a second node connected to a first node. The inverting sustaining module is used to maintain the potential of the first node and is controlled by the potential of the first node to transmit a first power signal or a second power signal to the second node so as to output the inverted potential of the first node at the second node. The potential of the first power signal is greater than the potential of the second power signal. The bootstrap module includes a third node connected to the first node, the bootstrap module is connected to the second node and is connected to a pull-down signal with a first potential, the first potential being less than the potential of the first power signal; An output module includes an output terminal. The output module is connected to the second node and the third node respectively. The output module is controlled by the potential of the second node and outputs an output signal with the potential of the first power signal at the output terminal. Alternatively, it is controlled by the potential of the third node and outputs the output signal with the potential of the second power signal at the output terminal. Specifically, when the output signal has the potential of the first power signal, the bootstrap module is controlled by the potential of the second node to control the pull-down signal to be electrically isolated from the third node using the first power signal; or, during the process of the output signal having the potential of the second power signal, the bootstrap module is controlled by the start signal to couple the first potential of the pull-down signal to pull down the potential of the third node.

2. The gate driving circuit according to claim 1, characterized in that, The phase-inverting sustaining module also includes an inverter and a first capacitor; The input terminal of the inverter and the first terminal of the first capacitor are connected to the first node. The first power supply terminal of the inverter is used to input the first power signal, and the second power supply terminal of the inverter and the second terminal of the first capacitor are used to input the second power signal. The output terminal of the inverter is connected to the second node. The inverter is used to output the first power signal when the potential of the first node is low and to output the second power signal when the potential of the first node is high.

3. The gate driving circuit according to claim 2, characterized in that, The inverter includes a first transistor and a second transistor; the gate of the first transistor and the first gate of the second transistor are connected to the first node, the first terminal of the first transistor is used to input the first power supply signal, the second terminals of the first transistor and the second terminal of the second transistor are connected to the second node, and the first terminal of the second transistor is used to input the second power supply signal; the first transistor is a P-type transistor and the second transistor is an N-type transistor.

4. The gate driving circuit according to claim 3, characterized in that, The second transistor further includes a second gate for inputting a third power supply signal, the level of which is lower than the level of the second power supply signal.

5. The gate driving circuit according to claim 1, characterized in that, The input module further includes a third transistor and a fourth transistor; The first terminal of the third transistor and the first terminal of the fourth transistor are connected to the input terminal. The third gate of the third transistor is used to input the inverted signal of the first clock signal, and the gate of the fourth transistor is used to input the first clock signal. The second terminals of the third transistor and the fourth transistor are connected to the first node. The third transistor is an N-type transistor, and the fourth transistor is a P-type transistor.

6. The gate driving circuit according to claim 5, characterized in that, The third transistor further includes a fourth gate, which is used to input a third power supply signal, the level of which is lower than the level of the second power supply signal.

7. The gate driving circuit according to claim 1, characterized in that, The bootstrap module also includes a first node control unit, a fourth node, a coupling unit, a fifth node, a second node control unit, and a switching unit; The first control terminal of the first node control unit is used to input the first clock signal, the input terminal of the first node control unit is connected to the input terminal, and the output terminal of the first node control unit is connected to the fourth node; the control terminal and input terminal of the switch unit are connected to the fourth node, and the output terminal of the switch unit is connected to the third node; the first terminal of the coupling unit is connected to the fourth node, the second terminal of the coupling unit is connected to the fifth node, the first control terminal of the second node control unit is connected to the second node, the second control terminal of the second node control unit is connected to the fourth node, the first input terminal of the second node control unit is used to input the first power signal, the second input terminal of the second node control unit is used to input the pull-down signal, and the output terminal of the second node control unit is connected to the fifth node; When the output signal has the potential of the first power signal, the second node control unit is controlled by the potential of the second node and outputs the first power signal to the second terminal of the coupling unit. The coupling unit controls the disconnection between the input and output terminals of the switching unit with the first power signal. During the process when the output signal has the potential of the second power signal, the first node control unit controls the potential of the fourth node according to the start signal. The second node control unit is controlled by the potential of the fourth node and outputs the pull-down signal to the second terminal of the coupling unit. The coupling unit couples the first potential of the pull-down signal to control the conduction between the input and output terminals of the switching unit and pulls down the potential of the third node.

8. The gate driving circuit according to claim 7, characterized in that, The first node control unit includes a fifth transistor, the gate of which is used to input the first clock signal, the first terminal of which is connected to the input terminal, and the second terminal of which is connected to the fourth node.

9. The gate driving circuit according to claim 8, characterized in that, The fifth transistor is a P-type transistor.

10. The gate driving circuit according to claim 7, characterized in that, The coupling unit includes a second capacitor, the first terminal of which is connected to the fourth node, and the second terminal of which is connected to the fifth node.

11. The gate driving circuit according to claim 7, characterized in that, The second node control unit includes a sixth transistor and a seventh transistor; The gate of the sixth transistor is connected to the fourth node, the first terminal of the sixth transistor is used to input the pull-down signal, the second terminals of the sixth transistor and the seventh transistor are connected to the fifth node, the gate of the seventh transistor is connected to the second node, and the first terminal of the seventh transistor is used to input the first power signal.

12. The gate driving circuit according to claim 7, characterized in that, The pull-down signal is the second clock signal.

13. The gate driving circuit according to claim 12, characterized in that, The first potential of the second clock signal lags behind the first potential of the first clock signal.

14. The gate driving circuit according to claim 11, characterized in that, The sixth and seventh transistors are P-type transistors.

15. The gate driving circuit according to claim 7, characterized in that, The switching unit includes an eighth transistor; the first electrode and gate of the eighth transistor are connected to the fourth node, and the second electrode of the eighth transistor is connected to the third node.

16. The gate driving circuit according to claim 15, characterized in that, The eighth transistor is a P-type transistor.

17. The gate driving circuit according to claim 8, characterized in that, The first node control unit also includes a ninth transistor; The gate of the ninth transistor is used to input a first fixed potential signal. The first terminal of the ninth transistor is connected to the second terminal of the fifth transistor, and the second terminal of the ninth transistor is connected to the fourth node. The ninth transistor is used to continuously conduct according to the first fixed potential signal.

18. The gate driving circuit according to claim 17, characterized in that, The ninth transistor is a P-type transistor, and the first fixed potential signal is the second power supply signal; or, the ninth transistor is an N-type transistor, and the first fixed potential signal is the first power supply signal.

19. The gate driving circuit according to claim 1, characterized in that, The output module includes a tenth transistor and an eleventh transistor; The gate of the tenth transistor is connected to the third node, the first terminal of the tenth transistor is used to input the second power signal, the second terminal of the tenth transistor is connected to the second terminal of the eleventh transistor and serves as the output terminal of the gate drive circuit; the gate of the eleventh transistor is connected to the second node, and the first terminal of the eleventh transistor is used to input the first power signal.

20. The gate driving circuit according to claim 19, characterized in that, Both the tenth transistor and the eleventh transistor are P-type transistors.

21. The gate driving circuit according to claim 1, characterized in that, It also includes a twelfth transistor, the gate of which is used to input a second fixed potential signal, the first terminal of which is connected to the first node, and the second terminal of which is connected to the third node.

22. The gate driving circuit according to claim 21, characterized in that, The twelfth transistor is a P-type transistor, and the second fixed potential signal is the second power supply signal; or, the twelfth transistor is an N-type transistor, and the second fixed potential signal is the first power supply signal.

23. The gate driving circuit according to any one of claims 1-22, characterized in that, Also includes: The inverting module includes an inverting output terminal connected to the input module. The inverting module is controlled by the potential of the first clock signal to transmit the first power signal to the inverting output terminal, or to transmit the second power signal to the inverting output terminal, so as to output a signal with a potential opposite to that of the first clock signal at the inverting output terminal, as the inverted signal of the first clock signal.

24. The gate driving circuit according to claim 23, characterized in that, The inverting module includes a thirteenth transistor and a fourteenth transistor; The fifth gate of the thirteenth transistor and the gate of the fourteenth transistor are used to input the first clock signal. The first terminal of the thirteenth transistor is used to input the second power signal. The second terminals of the thirteenth transistor and the fourteenth transistor are connected to the input module. The first terminal of the fourteenth transistor is used to input the first power signal. The thirteenth transistor is an N-type transistor, and the fourteenth transistor is a P-type transistor.

25. The gate driving circuit according to claim 24, characterized in that, The thirteenth transistor also includes a sixth gate, which is used to input a third power supply signal, the level of which is lower than the level of the second power supply signal.

26. A method for driving a gate driving circuit, used to drive the gate driving circuit according to any one of claims 1-25, characterized in that, The driving method includes: In the first stage, the input module responds to the first clock signal and its inverted signal to transmit the start signal with a first control potential to the first node. The inverted sustaining module maintains the first control potential at the first node and responds to the first control potential by outputting a first inverted potential of the first control potential at the second node. The bootstrap module responds to the first inverted potential by controlling the pull-down signal to be electrically isolated from the third node with the first power supply signal. The output module responds to the first inverted potential by outputting an output signal with the potential of the first power supply signal at the output terminal, wherein the first control potential is greater than the first inverted potential. In the second stage, the input module responds to the first clock signal and its inverted signal to transmit the start signal with a second control potential to the first node. The inverted sustaining module maintains the second control potential at the first node and responds to the second control potential by outputting a second inverted potential of the second control potential at the second node. The bootstrap module transmits the second control potential at the third node. The output module responds to the second control potential and outputs an output signal with a potential of the second power supply signal at the output terminal, wherein the second control potential is less than the second inverted potential. In the third stage, the bootstrap module, controlled by the second control potential, couples the first potential of the pull-down signal to pull down the potential of the third node, wherein the first potential is less than the second control potential.

27. A display panel, characterized in that, It includes a start signal line, a first clock signal line, a second clock signal line, a first pull-down signal line, a second pull-down signal line, and a multi-level gate drive circuit as described in any one of claims 1-22; The input terminal of the input module in the first-stage gate driving circuit is connected to the start signal line, and the input terminal of the input module in the next-stage gate driving circuit is connected to the output terminal of the output module in the previous-stage gate driving circuit. The first clock signal of the gate drive circuit in the odd-numbered stages is provided by the first clock signal line, and the inverted signal of the first clock signal of the gate drive circuit in the odd-numbered stages is provided by the first clock signal line through the first inverter. The pull-down signal of the gate drive circuit in the odd-numbered stages is provided by the first pull-down signal line. The first clock signal of the gate drive circuit in the even-numbered stages is provided by the second clock signal line, and the inverted signal of the first clock signal of the gate drive circuit in the even-numbered stages is provided by the second clock signal line through the second inverter. The pull-down signal of the gate drive circuit in the even-numbered stages is provided by the second pull-down signal line. The clock signal provided by the first clock signal line and the clock signal provided by the second clock signal line have the same waveform. The effective level of the clock signal provided by the first clock signal line leads the effective level of the clock signal provided by the second clock signal line. The first potential of the pull-down signal provided by the first pull-down signal line leads the first potential of the pull-down signal provided by the second pull-down signal line.

28. The display panel according to claim 27, characterized in that, The second clock signal line is multiplexed as the first pull-down signal line, and the first clock signal line is multiplexed as the second pull-down signal line.

29. A display panel, characterized in that, It includes a start signal line, a first clock signal line, a second clock signal line, a first pull-down signal line, a second pull-down signal line, and a multi-stage gate drive circuit as described in any one of claims 23 to 25; The input terminal of the input module in the first-stage gate driving circuit is connected to the start signal line, and the input terminal of the input module in the next-stage gate driving circuit is connected to the output terminal of the output module in the previous-stage gate driving circuit. The first clock signal of the gate drive circuit in the odd-numbered stages is provided by the first clock signal line, and the pull-down signal of the gate drive circuit in the odd-numbered stages is provided by the first pull-down signal line. The first clock signal of the gate drive circuit in the even-numbered stages is provided by the second clock signal line, and the pull-down signal of the gate drive circuit in the even-numbered stages is provided by the second pull-down signal line. The clock signals provided by the first clock signal line and the clock signals provided by the second clock signal line have the same waveform. The effective level of the clock signal provided by the first clock signal line leads the effective level of the clock signal provided by the second clock signal line. The first potential of the pull-down signal provided by the first pull-down signal line leads the first potential of the pull-down signal provided by the second pull-down signal line.

30. The display panel according to claim 29, characterized in that, The second clock signal line is multiplexed as the first pull-down signal line, and the first clock signal line is multiplexed as the second pull-down signal line.

31. A display device, characterized in that, The device includes a driving unit and a display panel as described in any one of claims 27 to 30; the driving unit is connected to the start signal line, the first clock signal line, the second clock signal line, the first pull-down signal line, and the second pull-down signal line, and is used to provide a start signal to the start signal line, a clock signal to the first clock signal line, a clock signal to the second clock signal line, a first pull-down signal to the first pull-down signal line, and a second pull-down signal to the second pull-down signal line.

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