A display panel

Abstract

The application provides a display panel, comprising a display area, two gate driving circuits and two gate adjusting circuits; wherein the two gate driving circuits are located at opposite sides of the display area to provide gate initial driving signals from the opposite sides of the display area respectively; the two gate adjusting circuits are configured to process the corresponding gate initial driving signals to generate gate adjusting driving signals based on the position of the breakpoint in response to the occurrence of the breakpoint on any gate line of the display area. The application sets the gate adjusting circuits on the opposite sides of the display area respectively, and when an abnormal situation occurs on the gate line, the gate initial driving signals are processed and converted into the gate adjusting driving signals by the gate adjusting circuits based on the position of the breakpoint, so as to reduce the brightness difference on both sides of the breakpoint, solve the display difference problem caused by the abnormal gate line, and make the display effect on both sides of the breakpoint equivalent.

Description

Technical Field

[0001] This application relates to the field of semiconductor display panel manufacturing, and in particular to a display panel. Background Technology

[0002] In the fields of semiconductor manufacturing, display panels, and microelectronic devices, gate lines are key structures for controlling current, and their precision and integrity directly affect device performance. As process nodes shrink to the nanometer scale, gate lines are prone to failure due to microscopic defects, stress damage, and material migration. If a gate line fails, one end will appear brighter than the other, resulting in abnormal display and affecting the viewing experience. Summary of the Invention

[0003] This application provides a display panel that solves the problem of display differences caused by abnormal gate lines in the display area.

[0004] To solve the above-mentioned technical problems, the technical solution adopted in this application is: to provide a display panel, including: a display area, two gate driving circuits and two gate adjustment circuits; Two gate drive circuits are located on opposite sides of the display area to provide gate initial drive signals from opposite sides of the display area respectively; Two gate adjustment circuits are configured to process the corresponding local gate initial drive signal to generate a local gate adjustment drive signal based on the location of the breakpoint when any gate line in the display area occurs.

[0005] In one embodiment, based on the location of the breakpoint, two gate adjustment circuits generate a first local gate adjustment drive signal and a second local gate adjustment drive signal, respectively, and the first local gate adjustment drive signal and the second local gate adjustment drive signal have opposite trends relative to the corresponding local gate initial drive signal.

[0006] In one embodiment, in response to the breakpoint appearing on the left side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left side is less than the enable validity period of the corresponding local gate initial drive signal; the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right side is greater than the enable validity period of the corresponding local gate initial drive signal. In response to the breakpoint appearing on the right side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left is greater than the enable validity period of the corresponding local gate initial drive signal; the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right is less than the enable validity period of the corresponding local gate initial drive signal.

[0007] In one embodiment, in response to the breakpoint being closer to the left side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left side is shorter than the enable validity period of the corresponding local gate initial drive signal; the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right side is longer than the enable validity period of the corresponding local gate initial drive signal. The closer the breakpoint is to the right side of the display area, the longer the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left is than the enable validity period of the corresponding local gate initial drive signal; the shorter the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right is than the enable validity period of the corresponding local gate initial drive signal.

[0008] In one embodiment, in response to the breakpoint appearing on the left side of the display area, the decrease in the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left relative to the enable validity period of the corresponding local gate initial drive signal is equal to the increase in the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right relative to the enable validity period of the corresponding local gate initial drive signal. In response to the breakpoint appearing on the right side of the display area, the increase in the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left relative to the enable validity period of the corresponding local gate initial drive signal is equal to the decrease in the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right relative to the enable validity period of the corresponding local gate initial drive signal.

[0009] In one embodiment, each gate adjustment circuit includes: a reference signal generation circuit, a first type of adjustment circuit, and a second type of adjustment circuit; The reference signal generation circuit is configured to generate a reference signal; The first type of adjustment circuit is connected to the reference signal generation circuit and receives the corresponding current gate initial drive signal. Based on the current gate initial drive signal and the reference signal, it generates a current gate adjustment drive signal with reduced enable validity period. The second type of adjustment circuit is connected to the reference signal generation circuit and receives the corresponding initial drive signal of the gate at this stage. Based on the initial drive signal of the gate at this stage and the reference signal, it generates an adjustment drive signal of the gate at this stage with an increased enable validity period.

[0010] In one embodiment, the middle position of the enable validity period of the reference signal is located at the end point of the enable validity period of the initial drive signal of the current gate.

[0011] In one embodiment, the first type of adjustment circuit includes: an AND logic circuit and a subtraction circuit; The logic AND circuit is configured to perform a logical AND operation on the enable validity period of the gate initial drive signal and the enable validity period of the reference signal to obtain an intermediate reference signal; The subtraction circuit is configured to perform a subtraction operation on the enable validity period of the current stage gate initial drive signal based on the intermediate reference signal, so as to obtain the current stage gate adjustment drive signal with a reduced enable validity period.

[0012] In one embodiment, the second type of adjustment circuit includes: The logic OR circuit is configured to perform a logic OR operation on the enable validity period of the current gate initial drive signal and the enable validity period of the reference signal to obtain a current gate adjustment drive signal with an increased enable validity period.

[0013] In one embodiment, the reference signal generation circuit includes: an input terminal, an RC filter circuit, and a transistor; The input terminal receives input signals with regular pulses. An RC filter circuit is connected between the input terminal and the ground voltage. The node between the regulating resistor and the regulating capacitor of the RC filter circuit is used to generate a phase-shifted signal with irregular pulses based on the input signal with regular pulses. In a transistor, the collector is connected to the input terminal, the base is connected to the node between the regulating resistor and the regulating capacitor, and the emitter is connected to ground through a bleed resistor.

[0014] The beneficial effects of this application are as follows: Unlike existing technologies, this application provides a display panel including a display area, two gate driving circuits, and two gate adjustment circuits. The two gate driving circuits are located on opposite sides of the display area to provide initial gate driving signals from opposite sides of the display area. The two gate adjustment circuits, in response to a break in any gate line of the display area, are configured to process the corresponding initial gate driving signal to generate a gate adjustment driving signal based on the break point's location. By providing gate adjustment circuits on opposite sides of the display area, when an abnormality occurs in the gate line, the gate adjustment circuits convert the initial gate driving signal into a gate adjustment driving signal based on the break point's location, reducing the brightness difference on both sides of the break point and solving the display difference problem caused by gate line abnormalities, thereby making the display effect on both sides of the break point comparable. Attached Figure Description

[0015] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0016] Figure 1 A schematic diagram of the frame of the first embodiment of the display panel provided in this application; Figure 2 For this application Figure 1 A schematic diagram of the framework of one embodiment of the gate adjustment circuit; Figure 3 For this application Figure 2 A waveform diagram of an embodiment of the first type of adjustment circuit; Figure 4 For this application Figure 2 A waveform diagram of an embodiment of the second type of adjustment circuit; Figure 5 For this application Figure 2 A schematic diagram of the framework of an embodiment of the reference signal generation circuit; Figure 6 For this application Figure 2 A waveform diagram of an embodiment of the reference signal generation circuit; Figure 7 A schematic diagram of the framework of a second embodiment of the display panel provided in this application; Figure 8 A schematic diagram of the framework of a third embodiment of the display panel provided in this application.

[0017] Reference numerals: Display panel 100, Display area 101, Non-display area 102, Gate drive circuit 10, Gate adjustment circuit 20, Gate lines s, n, g, h, Breakpoints A, B, D, E, F, Gate initial drive signal P, First local level gate adjustment drive signal P1, Second local level gate adjustment drive signal P2, Reference signal generation circuit 21, First type adjustment circuit 22, Logic AND circuit 221, Subtraction circuit 222, Second type adjustment circuit 23, Logic OR circuit 231, Adjustment... Resistor R1, regulating capacitor C1, node N1, transistor T1, bleed resistor R2, ground GND1, ground GND2, reference signal M, phase shift signal a, intermediate reference signal c, gate adjustment drive signal d for decreasing enable validity period and gate adjustment drive signal b for increasing enable validity period, distance L1 between breakpoints E and F, distance L2 between the two gate lines g and h, distance K1 from breakpoint D to the left edge of display area 101, distance K2 from breakpoint B to the right edge of display area 101. Detailed Implementation

[0018] The embodiments of this application will now be described in detail with reference to the accompanying drawings.

[0019] In the following description, specific details such as particular system architectures, interfaces, and technologies are presented for illustrative purposes rather than for limiting purposes, in order to provide a thorough understanding of this application.

[0020] In this article, the term "and / or" simply describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can represent: A alone, A and B simultaneously, or B alone. Additionally, the character " / " generally indicates that the preceding and following related objects have an "or" relationship. Furthermore, "more" in this article means two or more objects.

[0021] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0022] Before providing a further detailed description of the embodiments of this application, the nouns and terms involved in the embodiments of this application will be explained, and the nouns and terms involved in the embodiments of this application shall be interpreted as follows.

[0023] like Figure 1 As shown, Figure 1 This is a schematic diagram of the framework of a first embodiment of the display panel provided in this application. The display panel 100 provided in this application includes: a display area 101, two gate driving circuits 10 and two gate adjustment circuits 20; wherein, the two gate driving circuits 10 are located on opposite sides of the display area 101 to provide gate initial driving signals P from opposite sides of the display area 101 respectively; the two gate adjustment circuits 20 are configured to process the corresponding local gate initial driving signal P to generate local gate adjustment driving signals P1 and / or P2 based on the position of the breakpoint A when any gate line s of the display area 101 occurs.

[0024] It should be noted that the current gate is the gate that is currently being processed and causes a display difference due to an anomaly. It is the direct target of the current gate drive signal. The current gate drive signal includes the current gate initial drive signal P and the current gate adjustment drive signal P1 and / or P2.

[0025] In some embodiments, the display panel 100 includes a display area 101 (marked within the display area) and a non-display area 102. The display area 101 refers to the core area on the display panel 100 used to display images, and the area surrounding it is the non-display area 102. The initial gate drive signal P is the original control signal output by the gate drive circuit 10, used to drive the gate line s. The gate adjustment drive signals P1 and / or P2 are signals processed by the gate adjustment circuit 20, used to compensate for the effect of signal interruption caused by breakpoint A on the gate drive signal P of the pixels in the display area 101. Breakpoint A in the gate line s means that the gate line s is broken inside the display panel 100. If the gate line s in the display area 101 is configured to extend horizontally in the display panel 100, then the two gate drive circuits 10 can be respectively located on the left and right sides of the display area 101. The gate drive circuits 10 are used to provide the initial gate drive signal P. When the gate line s is abnormal, such as broken, the gate adjustment circuit 20 receives the initial gate drive signal P of this stage, processes the initial gate drive signal P of this stage based on the position of the breakpoint A, and generates the corresponding gate adjustment drive signal P1 and / or P2 of this stage.

[0026] This embodiment reduces the brightness difference on both sides of the breakpoint by setting two gate driving circuits and two gate adjustment circuits in the display panel respectively, and converts the initial gate driving signal into a gate adjustment driving signal through processing. This solves the display difference problem caused by abnormal gate lines, thereby making the display effect on both sides of the breakpoint comparable.

[0027] It should be noted that, in the following embodiments of this application, the left side of the display area specifically refers to the left half of the display area with the center line as the reference; the right side of the display area specifically refers to the right half of the display area with the center line as the reference. Furthermore, the range for breakpoints closer to the left and right sides of the display area is limited to between the center line and the left / right edge of the display area.

[0028] In one embodiment, based on the position of breakpoint A, the two gate adjustment circuits 20 respectively generate a first local gate adjustment drive signal P1 and a second local gate adjustment drive signal P2. The first local gate adjustment drive signal P1 and the second local gate adjustment drive signal P2 have opposite trends relative to their corresponding local gate initial drive signal P. That is, one of the first local gate adjustment drive signal P1 and the second local gate adjustment drive signal P2 increases relative to the corresponding local gate initial drive signal P, while the other decreases relative to the corresponding local gate initial drive signal P.

[0029] It should be noted that the position of the break point A of the gate line s can be determined based on the brightness of the display area 101. Specifically, when the brightness to the left of the break point A is greater than the brightness to the right, it indicates that the charging time of the gate line s to the left of the break point A is long, resulting in excessively high display brightness, while the charging time of the gate line s to the right of the break point A is short, resulting in excessively low display brightness. Therefore, the position of the break point A is determined to be on the left side of the display area 101. Conversely, when the brightness to the left of the break point A is less than the brightness to the right, it indicates that the charging time of the gate line s to the left of the break point A is short, resulting in excessively low display brightness, while the charging time of the gate line s to the right of the break point A is long, resulting in excessively high display brightness. Therefore, the position of the break point A is determined to be on the right side of the display area 101.

[0030] Based on this, the change trend of the first local gate adjustment drive signal P1 relative to the local gate initial drive signal P to the left of the breakpoint A is opposite to the change trend of the second local gate adjustment drive signal P2 relative to the local gate initial drive signal P to the right of the breakpoint A, thereby ensuring that the drive signal at the breakpoint A can be continuously transmitted, and further reducing the brightness difference between different areas when the breakpoint A occurs within the display area 101.

[0031] In one embodiment, in response to breakpoint A appearing on the left side of display area 101, the enable validity period of the first local gate adjustment drive signal P1 generated by the gate adjustment circuit 20 on the left side is less than the enable validity period of the corresponding local gate initial drive signal P; the enable validity period of the second local gate adjustment drive signal P2 generated by the gate adjustment circuit 20 on the right side is greater than the enable validity period of the corresponding local gate initial drive signal P.

[0032] It should be noted that the enable validity period in this embodiment refers to the time window during which the signal effectively drives the gate line. It can be the high-level time of the signal waveform or the charging time of the pixel capacitor in the display area 101. Specifically, the enable validity period is expressed as the pulse width of the signal waveform.

[0033] Specifically, when breakpoint A appears on the left side of display area 101, based on the fact that the brightness on the left side of display area 101 is greater than that on the right side, the enable validity period of the local gate initial drive signal P corresponding to the gate drive circuit 10 on the left side is reduced to generate the corresponding first local gate adjustment drive signal P1, thereby reducing the brightness on the left side of display area 101; the enable validity period of the local gate initial drive signal P corresponding to the gate drive circuit 10 on the right side is increased to generate the corresponding second local gate adjustment drive signal P2, thereby increasing the brightness on the right side of display area 101. Based on this, a smooth brightness transition at breakpoint A is ensured, reducing the display difference of display area 101.

[0034] In another embodiment, in response to breakpoint A appearing on the right side of display area 101, the enable validity period of the first local gate adjustment drive signal P1 generated by the gate adjustment circuit 20 on the left side is greater than the enable validity period of the corresponding local gate initial drive signal P; the enable validity period of the second local gate adjustment drive signal P2 generated by the gate adjustment circuit 20 on the right side is less than the enable validity period of the corresponding local gate initial drive signal P.

[0035] Specifically, when breakpoint A appears on the right side of display area 101, since the brightness on the left side of display area 101 is less than that on the right side, the enable validity period of the initial gate drive signal P corresponding to the gate drive circuit 10 on the left side is increased to generate the corresponding first gate adjustment drive signal P1, thereby increasing the brightness on the left side of display area 101; the enable validity period of the initial gate drive signal P corresponding to the gate drive circuit 10 on the right side is decreased to generate the corresponding second gate adjustment drive signal P2, thereby decreasing the brightness on the right side of display area 101. Based on this, a smooth brightness transition at breakpoint A is ensured, reducing the display difference of display area 101.

[0036] It should be noted that before the gate line s malfunctions, the display effect of the display area 101 is normal, and the display brightness of each part is consistent. After the gate line s malfunctions, such as breaking, regardless of whether the break point A is on the left or right side of the display area 101, the difference between the brightness of the side with excessive brightness and the brightness of the side with excessive brightness and the brightness of the side with excessive brightness is the same.

[0037] In one embodiment, in response to the closer the breakpoint A is to the left side of the display area 101, the shorter the enable validity period of the first local gate adjustment drive signal P1 generated by the left gate adjustment circuit 20 is compared to the enable validity period of the corresponding local gate initial drive signal P; the longer the enable validity period of the second local gate adjustment drive signal P2 generated by the right gate adjustment circuit 20 is compared to the enable validity period of the corresponding local gate initial drive signal P. It can be understood that when the position of the breakpoint A moves to the left, the left gate adjustment circuit 20 gradually reduces the enable validity period of the first local gate adjustment drive signal P1 based on the distance of the breakpoint A to the left, thereby gradually reducing the brightness of the left display area 101 and avoiding the risk of excessive brightness due to an excessively long signal; the right gate adjustment circuit 20 gradually increases the enable validity period of the second local gate adjustment drive signal P2 based on the distance of the breakpoint A to the right, thereby gradually increasing the brightness of the left display area 101 and avoiding the risk of excessive darkness due to an excessively short signal.

[0038] In another embodiment, in response to the closer the breakpoint A is to the right side of the display area 101, the longer the enable validity period of the first local gate adjustment drive signal P1 generated by the left gate adjustment circuit 20 is than the enable validity period of the corresponding local gate initial drive signal P; the shorter the enable validity period of the second local gate adjustment drive signal P2 generated by the right gate adjustment circuit 20 is than the enable validity period of the corresponding local gate initial drive signal P. It can be understood that when the breakpoint A moves to the right, the left gate adjustment circuit 20 gradually increases the enable validity period of the first local gate adjustment drive signal P1 based on the distance the breakpoint is closer to the left, thereby gradually increasing the brightness of the left display area 101 and avoiding the risk of being too dark due to a short signal; the right gate adjustment circuit 20 gradually decreases the enable validity period of the second local gate adjustment drive signal P2 based on the distance the breakpoint A is closer to the right, thereby gradually decreasing the brightness of the left display area 101 and avoiding the risk of being too bright due to a long signal.

[0039] This embodiment achieves continuous compensation at the gate line breakpoint by dynamically adjusting the enable validity period, further ensuring a smooth brightness transition at the breakpoint, thereby reducing display differences in the display area.

[0040] In one embodiment, in response to breakpoint A appearing on the left side of display area 101, the decrease in the enable validity period of the first local gate adjustment drive signal P1 generated by the gate adjustment circuit 20 on the left relative to the enable validity period of the corresponding local gate initial drive signal P is equal to the increase in the enable validity period of the second local gate adjustment drive signal P2 generated by the gate adjustment circuit 20 on the right relative to the enable validity period of the corresponding local gate initial drive signal P; in response to breakpoint A appearing on the right side of display area 101, the increase in the enable validity period of the first local gate adjustment drive signal P1 generated by the gate adjustment circuit 20 on the left relative to the enable validity period of the corresponding local gate initial drive signal P is equal to the decrease in the enable validity period of the second local gate adjustment drive signal P2 generated by the gate adjustment circuit 20 on the right relative to the enable validity period of the corresponding local gate initial drive signal P.

[0041] Specifically, the enable validity period of the drive signal is dynamically adjusted based on the position of the breakpoint A of the gate line s. When the breakpoint A is on the left, the enable validity period on the left is shortened to reduce the risk of the display area 101 being too bright, while the enable validity period on the right is extended to compensate for the problem of the display area 101 being too dark. The reduction in the enable validity period on the left is equal to the increase in the enable validity period on the right, thus offsetting the change in total brightness. When the breakpoint A is on the right, the enable validity period on the left is extended to compensate for the problem of the display area 101 being too dark, while the enable validity period on the right is shortened to reduce the risk of the display area 101 being too bright. Similarly, the brightness balance of the display area 101 is achieved by making the increase in the enable validity period on the left equal to the decrease in the enable validity period on the right.

[0042] It should be noted that this embodiment ensures the symmetry of brightness compensation by precisely limiting the reduction and increase of the enable validity period to be equal, thus avoiding brightness imbalance caused by unilateral compensation.

[0043] like Figure 2 As shown, in one embodiment, each gate adjustment circuit 20 includes a reference signal generation circuit 21, a first type adjustment circuit 22, and a second type adjustment circuit 23. The reference signal generation circuit 21 is configured to generate a reference signal M. The first type adjustment circuit 22 is connected to the reference signal generation circuit 21 and receives the corresponding local gate initial drive signal P. Based on the local gate initial drive signal P and the reference signal M, it generates local gate adjustment drive signals P1 and / or P2 with reduced enable validity. The second type adjustment circuit 23 is connected to the reference signal generation circuit 21 and receives the corresponding local gate initial drive signal P. Based on the local gate initial drive signal P and the reference signal M, it generates local gate adjustment drive signals P1 and / or P2 with increased enable validity.

[0044] It should be noted that the two gate adjustment circuits 20 respectively use the first type adjustment circuit 22 and the second type adjustment circuit 23 to perform calculations on the reference signal M generated by the reference signal generation circuit 21 and the initial gate drive signal P of the current stage, to obtain the corresponding first current stage gate adjustment drive signal P1 and second current stage gate adjustment drive signal P2.

[0045] This embodiment provides a stable reference signal through a reference signal generation circuit, thereby achieving precise control of the enable validity period. This reduces the enable validity period of the first type of adjustment circuit, thus reducing the risk of excessive brightness at the breakpoint; and increases the enable validity period of the second type of adjustment circuit, thereby compensating for the problem of excessive darkness at the breakpoint. This achieves a smooth brightness transition at the breakpoint, further improving the display uniformity of the display panel and helping to reduce the occurrence of uneven brightness in the display area.

[0046] In one embodiment, the midpoint of the enable validity period of the reference signal M is located at the end point of the enable validity period of the initial drive signal P of the current gate. It can be understood that the enable validity period refers to the time window during which the signal effectively drives the gate line s, with the midpoint being the middle of that time window. The enable validity period of the initial drive signal P of the current gate refers to the effective drive time window of that initial drive signal P. By precisely aligning the midpoint of the enable validity period of the reference signal M to the end point of the enable validity period of the initial drive signal P, it can be ensured that the reference signal M has been received by the gate adjustment circuit 20 by the end of the initial drive signal P, avoiding brightness transition distortion at the break point A of the gate line s due to time offset.

[0047] In one embodiment, the first type of adjustment circuit 22 includes: a logic AND circuit 221 and a subtraction circuit 222; specifically, the logic AND circuit 221 is configured to perform a logic AND operation on the enable validity period of the current gate initial drive signal P and the enable validity period of the reference signal M to obtain an intermediate reference signal c; the subtraction circuit 222 is configured to perform a subtraction operation on the enable validity period of the current gate initial drive signal P based on the intermediate reference signal c to obtain a current gate adjustment drive signal P1 and / or P2 with a reduced enable validity period.

[0048] Specifically, the AND circuit 221 generates an intermediate reference signal c by performing a AND operation on the enable validity period of the current gate initial drive signal P and the enable validity period of the reference signal M, ensuring that the signal is output only during the time period when the enable validity periods of the two signals completely overlap, thereby accurately capturing the intersection point of the time window; the subtraction circuit 222 performs a subtraction operation on the enable validity period of the current gate initial drive signal P based on the intermediate reference signal c, reducing the enable validity period of the current gate initial drive signal P, thereby suppressing the overbrightness phenomenon at the breakpoint A of the display area 101, further improving the brightness transition uniformity of the display panel 100, and helping to reduce the fault of uneven brightness in the display area 101.

[0049] In one embodiment, the reference signal M is positioned at the center of the falling edge of the initial gate drive signal P. Specifically, assuming an enable validity period of CLK signal X1 and an enable validity period of reference signal M Y1, after delaying the reference signal M by (X1-Y1 / 2), the reference signal M is located at the middle of the falling edge of the initial gate drive signal P, i.e., the centerline of the reference signal M is aligned with the falling edge of the initial gate drive signal P. In other embodiments, the delay parameter of the reference signal M can be adjusted according to the position of breakpoint A to solve the display abnormality problem caused by the breakage of gate line s, depending on the actual situation.

[0050] Combination Figure 3 In one embodiment, the reference signal M is set at the center of the falling edge of the initial gate drive signal P. Assuming the enable validity period of P is set to X and the enable validity period of M is set to Y, a logical AND operation is performed on signals P and M to obtain the intermediate reference signal c. The enable validity period of signal c is then Y / 2. A subtraction operation is then performed on signals P and M to obtain the gate adjustment drive signals P1 and / or P2. The enable validity period of the gate adjustment drive signals P1 and / or P2 is then (XY / 2). Based on this, the brightness of the side with stronger brightness on both sides of the gate line breakpoint A is reduced.

[0051] In one embodiment, the second type of adjustment circuit 23 includes a logic OR circuit 231, which is configured to perform a logic OR operation on the enable validity period of the local gate initial drive signal P and the enable validity period of the reference signal M to obtain local gate adjustment drive signals P1 and / or P2 with increased enable validity periods.

[0052] Specifically, the logic OR circuit 231 performs a logic OR operation, which outputs a valid value when either the current-stage gate initial drive signal P or the reference signal M is valid, thereby superimposing the enable validity periods of the two signals. This increases the enable validity period of the current-stage gate initial drive signal P, thus avoiding brightness transition problems caused by signal interruption.

[0053] Combination Figure 4 In one embodiment, the reference signal M is set at the center of the falling edge of the initial gate drive signal P. Assuming that the enable validity period of P is set to X2 and the enable validity period of b1 is set to M, a logical OR operation is performed on signals P and M to obtain the adjustment drive signals P1 and / or P2. Then, the enable validity period of signals P1 and / or P2 can be obtained as (X+Y / 2). Based on this, the brightness of the weaker side on both sides of the gate line breakpoint A is increased.

[0054] It should be noted that selectors can be set in the two gate adjustment circuits 20 respectively. After determining the position of the breakpoint, the corresponding first / second type adjustment circuit 22 / 23 is selected to dynamically adjust the enable validity period of the gate initial drive signal P by judging the position of the initial drive signal P.

[0055] like Figure 5 As shown, in one embodiment, the reference signal generation circuit 21 includes: an input terminal Vin, an RC filter circuit, and a transistor T1; wherein, the input terminal Vin is used to receive an input signal with regular pulses; the RC filter circuit is connected between the input terminal Vin and the ground voltage GND1, wherein the node N1 between the regulating resistor R1 and the regulating capacitor C1 of the RC filter circuit is used to generate a phase shift signal a with irregular pulses based on the input signal with regular pulses; the collector C of the transistor T1 is connected to the input terminal Vin, the base B of the transistor T1 is connected to the node N1 between the regulating resistor R1 and the regulating capacitor C1, and the emitter E of the transistor T1 is connected to the ground voltage GND2 through the bleed resistor R2.

[0056] It should be noted that the input signal with regular pulses received by the input terminal Vin includes the initial drive signal P of other gate levels output by the gate drive circuit 10. Other gate levels refer to the gates after the current processing level in the gate drive circuit 10. The input terminal Vin receiving the initial drive signal P of the gate after the current processing level in the gate drive circuit 10 can ensure that the reference signal generation circuit 21 can work based on the overall driving timing of the display panel 100.

[0057] Understandably, a regular pulse is a pulse signal with "fixed parameters and periodic repetition." In actual circuits, the parameters of a regular pulse (such as period and duty cycle) need to be designed according to specific functional requirements. For example, in this embodiment, the gate clock pulse of the display panel 100 needs to match the pixel charging time to ensure the effective period and stable display effect. An irregular pulse refers to a signal with an adjustable pulse width and effective period. Unlike a standard regular pulse, the RC filter circuit generates a phase-shifted signal a with irregular pulses by adjusting the combination of resistor R1 and capacitor C1. The voltage change at node N1 controls the conduction state of transistor T1 (the conduction characteristic of transistor T1 is that the emitter E is forward biased and the collector C is reverse biased), so that the width of the output enable effective period is determined by the resistor and capacitor values.

[0058] In this embodiment, the transistor can adopt an NPN structure. The collector receives the input signal, i.e., the gate initial drive signal, and the base receives the phase shift signal. When the input signal voltage is higher than the phase shift signal voltage, the transistor conducts, and the emitter is grounded through a bleed resistor to form a loop, thereby generating a reference signal. The bleed resistor can be a fixed resistor used to release residual charge in the circuit.

[0059] Combination Figure 6 In one embodiment, P is the gate initial drive signal, i.e., the input signal, with a high-level time of t1~t3, and b2 is the phase shift signal a, which has irregular pulses. Based on the conduction characteristics of transistor T1, that is, transistor T1 conducts when the input signal voltage is higher than the phase shift signal a voltage, and the time for the voltage of signal P to be higher than the voltage of signal a is t1~t2, therefore, the high-level time of the reference signal M finally output by transistor T1 is t1~t2. Based on this, the reference signal M is obtained and used in the gate adjustment circuit 20 to perform corresponding calculations with the gate initial drive signal P according to the actual situation to obtain the gate adjustment drive signals P1 and / or P2.

[0060] In one embodiment, the larger the resistance value of the adjusting resistor R1 and / or the capacitance value of the adjusting capacitor C1 in the RC filter circuit, the wider the enable validity period of the reference signal M generated by the reference signal generation circuit 21. Specifically, when the resistance value of the adjusting resistor R1 and / or the capacitance value of the adjusting capacitor C1 increases, the capacitor charges more slowly, the voltage rises to the peak value slowly, and the discharge also becomes slower, resulting in a significantly wider waveform pulse width, thereby widening the enable validity period. When the resistance value of the adjusting resistor R1 and / or the capacitance value of the adjusting capacitor C1 decreases, the capacitor charges more quickly, the voltage reaches the peak value rapidly, and the discharge also becomes rapid, resulting in a narrower waveform pulse width, thereby narrowing the enable validity period. In this embodiment, the adjusting resistor R1 in the RC filter circuit can be adjusted using a digital potentiometer, and the adjusting capacitor C1 can be an adjustable capacitor such as a ceramic capacitor. In other embodiments, the RC filter circuit can also use a combination of fixed resistors and capacitors.

[0061] Understandably, in some embodiments, the positional difference of breakpoint A will cause differences in the required enable validity period on the left and right sides. When breakpoint A is in the middle of display area 101, the enable validity period of reference signal M is 0, meaning that no display abnormality will occur, and there is no need to compensate for the display brightness on the left and right sides of the breakpoint. Assuming that breakpoint A moves closer to the edge from the middle position, the enable validity period of reference signal M also needs to be increased synchronously. Specifically, assuming that breakpoint A is at the outermost edge of display area 101, the difference in enable validity period between the left and right driving signals is Z, and the required enable validity period at the middle position is 0. Taking FHD (Full High Definition) as an example, there are 1920 sub-pixels in the H direction. If an abnormality occurs in sub-pixel 300 (counting horizontally from left to right), the difference in enable validity period that needs to be adjusted is 300*Z / 960. Based on this, in practical applications, the enable validity period can be adjusted according to the actual position of breakpoint A.

[0062] This embodiment ensures that the reference signal generation circuit can operate based on the overall driving timing of the display panel, which helps reduce the phenomenon of display brightness deviation caused by gate line abnormalities. It also ensures that the input signal includes the initial driving signals of other gate stages, thereby facilitating precise synchronization between the reference signal generation circuit and the global driving timing of the display panel and reducing the problem of uneven brightness of the display panel. Furthermore, it increases the resistance value of the adjusting resistor or the capacitance value of the adjusting capacitor, and prolongs the enable validity period of the reference signal, thereby helping to reduce periodic flicker and improve display uniformity.

[0063] See Figure 7In other embodiments, if the gate line n in the display area 101 breaks twice, that is, the same gate line n has two breakpoints E and F, the two gate adjustment circuits 20 are also used to obtain the distance L1 between the two breakpoints E and F. In response to the distance L1 between the two breakpoints E and F being less than a first distance threshold, the two breakpoints E and F are considered as one point, and the enable validity period of the corresponding gate drive signal P is adjusted based on its position using the technical solution of the above embodiments, thereby reducing the difference in display brightness and further improving the uniformity of display brightness. In response to the distance L1 between the two breakpoints E and F being greater than the first distance threshold, a prompt is issued, reminding the user to consider whether to repair it.

[0064] In one embodiment, such as Figure 8 As shown, two gate lines g and h in the display area 101 simultaneously have breakpoints B and D. Two gate adjustment circuits 20 are also used to obtain the distance L2 between the two gate lines g and h. In response to a distance L2 greater than a second distance threshold, the above-mentioned technical solution is still used to adjust the enable validity period of the gate drive signals P corresponding to the two gate lines g and h based on the positions of breakpoints B and D. In response to a distance L2 less than or equal to the second distance threshold, the two gate adjustment circuits 20 are also used to obtain the distance from breakpoint B of gate line g to the right edge of the display area 101. The distance K2 and the distance K1 from the breakpoint D of gate line h to the left edge of display area 101 are given. In response to the absolute value of the difference between K1 and K2 being less than or equal to a first threshold, the brightness differences on the left and right sides of breakpoint B and breakpoint D are exactly opposite. That is, for gate line g, the left side of breakpoint B has lower display brightness and the right side has higher display brightness; for gate line h, the left side of breakpoint D has higher display brightness and the right side has lower display brightness. Based on this, the uneven display brightness distribution caused by the breakage of gate lines g and h can cancel each other out, so there is no need to change the enable validity period of the initial gate drive signal P on both sides of the breakpoint. In response to the absolute value of the difference between K1 and K2 being greater than the first threshold, the above technical solution is still used to adjust the enable validity period of the gate drive signal P corresponding to the two gate lines g and h based on the positions of breakpoints B and D respectively.

[0065] To ensure that differences in display brightness can be reduced and display brightness uniformity further improved, taking a 55-inch 4K display panel as an example, the above... Figure 7 and Figure 8 In both embodiments, the first distance threshold and the second distance threshold can be set between 0 and 0.5 mm, such as 0.3 mm, 0.2 mm, etc.

[0066] This application incorporates two gate adjustment circuits, each with a separate gate drive circuit, into the display panel. These circuits process and convert the initial gate drive signal into a gate adjustment drive signal, ensuring continuous transmission of the gate signal at breakpoints and preventing uneven brightness in the display area. This further improves the reliability and lifespan of the display panel and helps reduce maintenance costs.

[0067] In some embodiments, the functions or modules of the apparatus provided in this disclosure can be used to perform the methods described in the above method embodiments. The specific implementation can be referred to the description of the above method embodiments, and for the sake of brevity, it will not be repeated here.

[0068] The description of the various embodiments above tends to emphasize the differences between the various embodiments. The similarities or similarities between them can be referred to, and for the sake of brevity, they will not be repeated here.

[0069] In the several embodiments provided in this application, it should be understood that the disclosed methods and apparatus can be implemented in other ways. For example, the apparatus implementations described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the mutual coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection of devices or units may be electrical, mechanical, or other forms.

[0070] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0071] The above are merely embodiments of this application and do not limit the scope of patent protection of this application. Any equivalent structural or procedural changes made using the content of this application’s specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the scope of patent protection of this application.

Claims

1. A display panel, characterized in that, include: Display area; Two gate driving circuits are located on opposite sides of the display area to provide gate initial driving signals from opposite sides of the display area, respectively. Two gate adjustment circuits are configured to respond to a break in any gate line of the display area. Based on the location of the breakpoint, the two gate adjustment circuits respectively generate a first local gate adjustment drive signal and a second local gate adjustment drive signal. The first local gate adjustment drive signal and the second local gate adjustment drive signal have opposite trends relative to the corresponding local gate initial drive signal. In response to the breakpoint appearing on the left side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left side is less than the enable validity period of the corresponding local gate initial drive signal. The enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right is longer than the enable validity period of the corresponding local gate initial drive signal. In response to the breakpoint appearing on the right side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left side is greater than the enable validity period of the corresponding local gate initial drive signal. The enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right is shorter than the enable validity period of the corresponding local gate initial drive signal.

2. The display panel according to claim 1, characterized in that, In response to the breakpoint being closer to the left side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left side is shorter than the enable validity period of the corresponding local gate initial drive signal. The enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right is greater than the enable validity period of the corresponding local gate initial drive signal; In response to the breakpoint being closer to the right side of the display area, the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left side is greater than the enable validity period of the corresponding local gate initial drive signal. The enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right is shorter than the enable validity period of the corresponding local gate initial drive signal.

3. The display panel according to claim 1, characterized in that, In response to the breakpoint appearing on the left side of the display area, the decrease in the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left relative to the enable validity period of the corresponding local gate initial drive signal is equal to the increase in the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right relative to the enable validity period of the corresponding local gate initial drive signal. In response to the breakpoint appearing on the right side of the display area, the increase in the enable validity period of the first local gate adjustment drive signal generated by the gate adjustment circuit on the left relative to the enable validity period of the corresponding local gate initial drive signal is equal to the decrease in the enable validity period of the second local gate adjustment drive signal generated by the gate adjustment circuit on the right relative to the enable validity period of the corresponding local gate initial drive signal.

4. The display panel according to claim 1, characterized in that, Each of the gate adjustment circuits includes: The reference signal generation circuit is configured to generate a reference signal; The first type of adjustment circuit is connected to the reference signal generation circuit and receives the corresponding initial drive signal of the current gate. Based on the initial drive signal of the current gate and the reference signal, it generates the current gate adjustment drive signal with reduced enable validity period. The second type of adjustment circuit is connected to the reference signal generation circuit and receives the corresponding initial drive signal of the current gate. Based on the initial drive signal of the current gate and the reference signal, it generates the current gate adjustment drive signal with an increased enable validity period.

5. The display panel according to claim 4, characterized in that, The middle position of the enable validity period of the reference signal is located at the end point of the enable validity period of the initial drive signal of the current gate.

6. The display panel according to claim 5, characterized in that, The first type of adjustment circuit includes: The logic AND circuit is configured to perform a logical AND operation on the enable validity period of the current gate initial drive signal and the enable validity period of the reference signal to obtain an intermediate reference signal; The subtraction circuit is configured to perform a subtraction operation on the enable validity period of the current stage gate initial drive signal based on the intermediate reference signal, so as to obtain the current stage gate adjustment drive signal with a reduced enable validity period.

7. The display panel according to claim 5, characterized in that, The second type of adjustment circuit includes: A logic OR circuit is configured to perform a logic OR operation on the enable validity period of the local gate initial drive signal and the enable validity period of the reference signal to obtain the local gate adjustment drive signal with an increased enable validity period.

8. The display panel according to claim 4, characterized in that, The reference signal generation circuit includes: The input terminal receives input signals with regular pulses. An RC filter circuit is connected between the input terminal and ground voltage, wherein the node between the regulating resistor and the regulating capacitor of the RC filter circuit is used to generate a phase-shift signal with irregular pulses based on the input signal with regular pulses; The transistor has its collector connected to the input terminal, its base connected to the node between the regulating resistor and the regulating capacitor, and its emitter connected to the ground voltage through a bleed resistor.

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