Non-volatile static random access memory resistant to single event upsets

Abstract

The application discloses a non-volatile static random access memory (SRAM) with anti-single event upset, and belongs to the field of integrated circuits, and can be applied to realize non-volatility and anti-single event upset reliability of the SRAM.The scheme of the application is that a magnetic tunnel junction (MTJ), a PMOS transistor and an NMOS transistor are added on the basis of a traditional 6-transistor SRAM circuit, so that the traditional SRAM is integrated with non-volatility, and errors caused by single event upset effects can be effectively corrected.The application has the following advantages: the magnetic tunnel junction is used as a non-volatile storage unit, so that the application has high reliability, low power consumption and good compatibility with a traditional process; the sensitive node of the single event effect is considered, so that the application can quickly correct error data bit upset, has stronger anti-single event upset capability, and can be used for reliable storage of data in a space radiation environment.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a non-volatile static random access memory resistant to single-event upsets. Background Technology

[0002] Static Random Access Memory (SRAM) is a semiconductor memory based on the flip-flop principle. Due to its superior high-speed performance, it has become a core component of CPU cache and other high-speed storage devices that require high performance. However, the requirement for continuous power supply to ensure that stored data is not lost is a major obstacle to its development. Furthermore, SRAM is sensitive to complex radiation environments and has low radiation resistance, making it difficult to meet the high reliability requirements of aerospace applications.

[0003] Magnetic tunnel junctions (MTJs) are widely used spin devices composed of a free magnetic layer, a tunnel gate layer, and a fixed magnetic layer. When the magnetic fields of the free and fixed layers are parallel, the MTJ exhibits low resistance; conversely, it exhibits high resistance. By detecting the resistance of the MTJ, the stored data can be determined as "0" or "1," eliminating the need for charge to store information and providing inherent radiation resistance. Integrating MTJs into a traditional 6-transistor (6T) static random access memory (SRAM) allows for the construction of non-volatile SRAMs, meaning data is retained even after power loss and can be recovered upon power restoration, with strong radiation resistance in its core storage unit. However, the peripheral control circuitry of non-volatile SRAMs uses transistors manufactured using traditional CMOS technology, making them susceptible to single-event upsets and other radiation effects from high-energy particles such as protons, electrons, and heavy ions in the space environment. This can lead to functional failures, becoming a significant factor limiting their space applications.

[0004] Therefore, there is an urgent need for a method to solve the single-event flip problem of static random access memory (SRAM), eliminate the above-mentioned effects, and design non-volatile SRAM with single-event flip resistance capability, which has important significance for space applications. Summary of the Invention

[0005] The purpose of this invention is to provide a non-volatile static random access memory (SRAM) resistant to single-event upsets, in order to solve the problems in the prior art.

[0006] To solve the above-mentioned technical problems, the present invention provides a non-volatile static random access memory resistant to single-event upsets, including magnetic tunnel junctions MTJ1 and MTJ2, NMOS transistors N1 to N10, and PMOS transistors P1 to P4;

[0007] The source of PMOS transistor P1 is connected to VDD, and the drain of PMOS transistor P1 is connected to the drain of NMOS transistor N1, with the connection point at node I1; the source of NMOS transistor N1 is grounded. The source of PMOS transistor P2 is connected to VDD, and the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N2, with the connection point at node I2; the source of NMOS transistor N2 is grounded. The source of PMOS transistor P3 is connected to VDD, and the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N3, with the connection point at node I3; the source of NMOS transistor N3 is grounded. The source of PMOS transistor P4 is connected to VDD, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4, with the connection point at node I4; the source of NMOS transistor N4 is grounded.

[0008] The drain of NMOS transistor N9 is connected to the drain of NMOS transistor N1 at node I1. The source of NMOS transistor N9 is connected to the variable magnetic layer of magnetic tunnel junction MTJ1. The fixed magnetic layer of magnetic tunnel junction MTJ1 is connected to the TE control signal.

[0009] The drain of NMOS transistor N10 is connected to the drain of NMOS transistor N4 at node I4. The source of NMOS transistor N10 is connected to the variable magnetic layer of magnetic tunnel junction MTJ2. The fixed magnetic layer of magnetic tunnel junction MTJ2 is connected to the TE control signal.

[0010] The drain of NMOS transistor N5 is connected to the drain of NMOS transistor N1 at node I1, and the source of NMOS transistor N5 is connected to the bit line signal BL; the drain of NMOS transistor N7 is connected to the drain of NMOS transistor N3 at node I3, and the source of NMOS transistor N7 is connected to the bit line signal BL.

[0011] The drain of NMOS transistor N6 is connected to the drain of NMOS transistor N2 at node I2. The source of NMOS transistor N6 is connected to the complementary bit line signal BLB. The drain of NMOS transistor N8 is connected to the drain of NMOS transistor N4 at node I4. The source of NMOS transistor N8 is connected to the complementary bit line signal BLB.

[0012] The gate of PMOS transistor P1 is simultaneously connected to the drain of PMOS transistor P4 and the gate of NMOS transistor N3; the gate of PMOS transistor P2 is simultaneously connected to the drain of NMOS transistor N3 and the gate of NMOS transistor N4; the gate of PMOS transistor P3 is simultaneously connected to the drain of NMOS transistor N2 and the gate of NMOS transistor N1; the gate of PMOS transistor P4 is simultaneously connected to the drain of NMOS transistor N1 and the gate of NMOS transistor N2.

[0013] The gate of NMOS transistor N9 is connected to the SW control signal; the gate of NMOS transistor N10 is connected to the SW control signal.

[0014] The gate of NMOS transistor N5 is connected to the word line signal WL; the gate of NMOS transistor N6 is connected to the word line signal WL; the gate of NMOS transistor N7 is connected to the word line signal WL; the gate of NMOS transistor N8 is connected to the word line signal WL.

[0015] In one embodiment, the growth structure of the magnetic tunnel junctions MTJ1 and MTJ2 is a ferromagnetic layer / non-magnetic insulating layer / ferromagnetic layer. The data storage method utilizes the different resistance values ​​of the two ferromagnetic layers when they are parallel and non-parallel. The data writing method utilizes a small current passing through the magnetic tunnel junction to cause the ferromagnetic layer to flip, thereby changing the logic state.

[0016] In one embodiment, before data is written, the bit line signal BL is pre-set to "1" and the complementary bit line signal BLB is pre-set to "0" in the non-volatile static random access memory.

[0017] When the word line signal WL is set to "1", it controls NMOS transistors N5, NMOS transistor N6, NMOS transistor N7 and NMOS transistor N8 to turn on. The bit line signal BL charges node I1 through NMOS transistor N5 and charges node I3 through NMOS transistor N7, so that nodes I1 and I3 are written with logic "1".

[0018] The complementary bit line signal BLB discharges node I2 through NMOS transistor N6 and node I4 through NMOS transistor N8, causing nodes I2 and I4 to be written with logic "0". Finally, the data "1, 0, 1, 0" is written to the four storage nodes I1, I2, I3 and I4 in sequence, completing the write operation of logic "1". Since the non-volatile static random access memory is designed symmetrically, it is also applicable when storing data as logic "0".

[0019] In one implementation, the logic states of the magnetic tunnel junctions MTJ1 and MTJ2 are always complementary. When the TE control signal is set to "0", because nodes I1 and I3 are at a high level, current flows from nodes I1 and I3 to TE, causing the magnetic tunnel junction MTJ1 to change from antiparallel to parallel, thus realizing the writing of logic "1" into the magnetic tunnel junction MTJ1.

[0020] When the TE control signal is set to "1", the current flows from TE to nodes I2 and I4, causing the magnetic tunnel junction MTJ2 to change from antiparallel to parallel, thus writing logic "0" into the magnetic tunnel junction MTJ2; finally, the non-volatile write operation is completed.

[0021] In one embodiment, the single-event sensitive nodes of the static random access memory are the drain of a PMOS transistor that is turned off and the source of a NMOS transistor that is turned off, and the nodes that may generate single-event pulse current are I1, I2, I3 and I4.

[0022] If a single-event flip (SET) occurs at sensitive node I1, changing it from logic "1" to logic "0", PMOS transistor P4 turns on and NMOS transistor N2 turns off. Node I4 generates a weak "1" level, while PMOS transistor P1 is temporarily turned off. Nodes I2 and I3 are unaffected by the I1 flip, and NMOS transistor N4 remains on. Therefore, node I4 is pulled down to a strong "0" level by NMOS transistor N4, achieving SEU self-repair. Subsequently, PMOS transistor P1 turns on again, pulling node I1 back up to logic "1". Ultimately, the generated SET quickly recovers without affecting data reading.

[0023] If a single-event flip occurs at sensitive node I2, changing it from logic "0" to logic "1", PMOS transistor P3 will turn off and NMOS transistor N1 will turn on. NMOS transistor N1 will temporarily pull down node I1 to output a weak "0". This weak level will be neutralized by the strong "1" output by the continuously conducting PMOS transistor P1, restoring node I1. NMOS transistor N2 will then turn on again, pulling node I2 down to logic "0". Due to the symmetrical design of the non-volatile static random access memory, the single-event flip of nodes I3 and I4 is also applicable.

[0024] In one embodiment, the feature size range of the NMOS transistors N1 to N10 and the PMOS transistors P1 to P4 is 7nm-130μm.

[0025] In one embodiment, the non-volatile static random access memory is suitable for radiation-hardened circuits that use magnetic tunnel junctions as non-volatile memory cells.

[0026] The present invention provides a non-volatile static random access memory resistant to single-event upsets, which has the following advantages:

[0027] (1) By integrating a magnetic tunnel junction (MTJ) on a traditional 6T static random access memory cell, the static random access memory becomes non-volatile, which can improve memory reliability, reduce power consumption, and expand its application range.

[0028] (2) The single-event upset resistance is improved by adding NMOS and PMOS transistors. The method is simple and compatible with traditional transistor manufacturing processes. The hardening method has a sufficient process basis and the hardening results are highly reliable.

[0029] (3) The hardening method can effectively correct errors caused by single-event upsets and can be used to improve the single-event upset reliability of space static random access memory circuits. Attached Figure Description

[0030] Figure 1 This is a schematic diagram of the reinforcement structure of the present invention;

[0031] Figure 2 This is a diagram illustrating the single-particle reinforcement principle of the reinforced structure of this invention.

[0032] Figure 3 This is a simulation test result diagram of the reinforced structure of the present invention. Detailed Implementation

[0033] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, provides a non-volatile static random access memory (SRAM) resistant to single-event upsets proposed in this invention. The advantages and features of the invention will become clearer from the following description. It should be noted that the drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the invention.

[0034] This invention provides a non-volatile static random access memory (SRAM) resistant to single-event upsets, the structure of which is as follows: Figure 1 As shown, it includes magnetic tunnel junctions MTJ1 and MTJ2, NMOS transistors N1 to N10, and PMOS transistors P1 to P4; the specific transistor connections are as follows:

[0035] The source of PMOS transistor P1 is connected to VDD, and the drain of PMOS transistor P1 is connected to the drain of NMOS transistor N1 at node I1; the source of NMOS transistor N1 is grounded. The source of PMOS transistor P2 is connected to VDD, and the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N2 at node I2; the source of NMOS transistor N2 is grounded. The source of PMOS transistor P3 is connected to VDD, and the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N3 at node I3; the source of NMOS transistor N3 is grounded. The source of PMOS transistor P4 is connected to VDD, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4 at node I4; the source of NMOS transistor N4 is grounded.

[0036] The drain of NMOS transistor N9 is connected to the drain of NMOS transistor N1 at node I1. The source of NMOS transistor N9 is connected to the variable magnetic layer of magnetic tunnel junction MTJ1. The fixed magnetic layer of magnetic tunnel junction MTJ1 is connected to the TE control signal.

[0037] The drain of NMOS transistor N10 is connected to the drain of NMOS transistor N4 at node I4. The source of NMOS transistor N10 is connected to the variable magnetic layer of magnetic tunnel junction MTJ2. The fixed magnetic layer of magnetic tunnel junction MTJ2 is connected to the TE control signal.

[0038] The drain of NMOS transistor N5 is connected to the drain of NMOS transistor N1 at node I1. The source of NMOS transistor N5 is connected to the bit line signal BL. The drain of NMOS transistor N7 is connected to the drain of NMOS transistor N3 at node I3. The source of NMOS transistor N7 is connected to the bit line signal BL.

[0039] The drain of NMOS transistor N6 is connected to the drain of NMOS transistor N2 at node I2. The source of NMOS transistor N6 is connected to the complementary bit line signal BLB. The drain of NMOS transistor N8 is connected to the drain of NMOS transistor N4 at node I4. The source of NMOS transistor N8 is connected to the complementary bit line signal BLB.

[0040] The gate of PMOS transistor P1 is simultaneously connected to the drain of PMOS transistor P4 and the gate of NMOS transistor N3; the gate of PMOS transistor P2 is simultaneously connected to the drain of NMOS transistor N3 and the gate of NMOS transistor N4; the gate of PMOS transistor P3 is simultaneously connected to the drain of NMOS transistor N2 and the gate of NMOS transistor N1; the gate of PMOS transistor P4 is simultaneously connected to the drain of NMOS transistor N1 and the gate of NMOS transistor N2.

[0041] The gate of NMOS transistor N9 is connected to the SW control signal; the gate of NMOS transistor N10 is connected to the SW control signal.

[0042] The gate of NMOS transistor N5 is connected to the word line signal WL; the gate of NMOS transistor N6 is connected to the word line signal WL; the gate of NMOS transistor N7 is connected to the word line signal WL; the gate of NMOS transistor N8 is connected to the word line signal WL.

[0043] The growth structure of a magnetic tunnel junction (MTJ) consists of a ferromagnetic layer, a non-magnetic insulating layer, and a ferromagnetic layer. Data is stored by utilizing the different resistance values ​​of the two ferromagnetic layers when they are parallel and non-parallel. Data is written by using a small current to pass through the MTJ, causing the ferromagnetic layer to flip and change the logic state.

[0044] The static random access memory of this invention is suitable for radiation-hardened circuits using magnetic tunnel junctions as non-volatile memory cells. The transistor feature sizes used range from 7nm to 130μm.

[0045] Before data is written, the bit line signal BL is preset to "1", and the complementary bit line signal BLB is preset to "0". When the word line signal WL is set to "1", NMOS transistors N5, N6, N7, and N8 are turned on. The bit line signal BL charges node I1 through NMOS transistor N5 and charges node I3 through NMOS transistor N7, causing nodes I1 and I3 to be written with logic "1". The complementary bit line signal BLB discharges node I2 through NMOS transistor N6 and discharges node I4 through NMOS transistor N8, causing nodes I2 and I4 to be written with logic "0". Finally, the data "1, 0, 1, 0" is written sequentially to the four storage nodes I1, I2, I3, and I4, thus completing the write operation of logic "1".

[0046] The logic states of magnetic tunnel junctions MTJ1 and MTJ2 remain complementary. When the TE control signal is set to "0", because nodes I1 and I3 are at a high level, current flows from nodes I1 and I3 to TE, causing MTJ1 to change from a low-resistance state (parallel) to a high-resistance state (anti-parallel), thus writing a logic "1" into MTJ1. When the TE control signal is set to "1", current flows from TE to nodes I2 and I4, causing MTJ2 to change from anti-parallel to parallel, thus writing a logic "0" into MTJ2. Finally, the non-volatile write operation is completed.

[0047] In this invention, the single-event sensitive nodes of the static random access memory (SRAM) are the drain of a PMOS transistor that is turned off and the source of an NMOS transistor that is turned off. The nodes that may generate single-event pulse currents are I1, I2, I3, and I4. Taking a single-event flip at sensitive node I1 as an example, i.e., a flip from logic "1" to logic "0", causes PMOS transistor P4 to turn on and NMOS transistor N2 to turn off. Node I4 generates a weak "1" level, while PMOS transistor P1 is temporarily turned off. Nodes I2 and I3 are unaffected by the I1 flip, keeping NMOS transistor N4 on. Therefore, node I4 is pulled down to a strong "0" level by NMOS transistor N4, achieving SEU self-repair. Subsequently, PMOS transistor P1 turns back on, pulling node I1 up to restore it to logic "1". Ultimately, the generated single-event flip recovers quickly without affecting data reading.

[0048] Taking a single-event upset (SWE) at sensitive node I2 as an example, where the logic value flips from "0" to "1", causing PMOS transistor P3 to turn off and NMOS transistor N1 to turn on. NMOS transistor N1 temporarily pulls node I1 down to output a weak "0", but this weak level is neutralized by the strong "1" output by the continuously conducting PMOS transistor P1, restoring node I1 to its original state. NMOS transistor N2 then turns on again, pulling node I2 down to its original logic "0".

[0049] Because of the symmetrical circuit design, it is also applicable to single-event flips of nodes I3 and I4; because of the symmetrical circuit design, it is also applicable when the stored data is logic "0".

[0050] The testing of the structure of this invention includes the following steps:

[0051] a. Set the VDD constant voltage source to 3.3V, keep the power supply on from 0 to 47ns, turn off at 47ns, and turn on again at 55ns. The simulation duration is 60ns.

[0052] b. Set the word line signal WL to a high level of 3.3V for 5-10ns to enable write operations, and a low level of 0V at other times. Set the bit line signal BL to a high level of 3.3V for 0-10ns, and the complementary bit line signal BLB to a low level of 0V.

[0053] c. Set the SW control signal to a high level of 3.3V for 15-25ns to enable the write operation to the magnetic tunnel junction (MTJ). Set the SW control signal to a high level for 53-55ns, i.e., 2ns before the power supply is re-energized, to ensure that the MTJ and the storage node form a path and complete the operation of restoring the data stored in the MTJ to the storage node. The signal should be at a low level for the rest of the time to block the influence of other nodes and transistors on the MTJ.

[0054] d. Set the TE control signal to a low level for 15-20ns to complete the writing operation of the magnetic tunnel junction MTJ1, and a high level for 20-25ns to complete the writing operation of the magnetic tunnel junction MTJ2. The signal should also be low for the rest of the time.

[0055] e. Simulate sensitive memory nodes I1, I2, I3, and I4, as well as magnetic tunnel junction MTJ1 and

[0056] MTJ2. Sensitive node analysis, such as... Figure 2 As shown, the black transistor is on, the gray transistor is off, the black line level is "1", the gray line level is "0", the magnetic tunnel junction MTJ1 is in antiparallel state, and the magnetic tunnel junction MTJ2 is in parallel state.

[0057] f. For current pulse simulations of single-event upsets, the following double exponential function is used:

[0058]

[0059] Q inj τ represents the total charge collected at the sensitive node; τ1 represents the collection time constant; τ2 represents the ion orbital establishment time constant. t is a time variable, referring to the time of the simulated single-particle incident, Q... inj The values ​​of τ1 and τ2 are typically between -2pc and 2pc, with negative and positive values ​​at the sensitive nodes of N and P transistors, respectively. Typical values ​​for τ1 and τ2 are 150ps and 50ps, respectively. inj Let I be a function of time t, and let its graph be a single-peaked curve. inj The line integral of Q with respect to t can be used to calculate Q. inj .

[0060] g. Call the double exponential pulse current source in the analogLib library, and set the double exponential pulse current source to introduce negative current pulses at nodes I1 and I3 at 28ns and 38ns respectively, and positive current pulses at nodes I2 and I4 at 33ns and 43ns respectively.

[0061] h. Open the built-in ADEL simulation tool, set the TRAN simulation time to 60ns, and export the waveforms of VDD, WL, BL, BLB, SW, TE, MTJ1, MTJ2, I1, I2, I3, and I4. The exported results are as follows: Figure 3 As shown.

[0062] i. Simulation results show that after a negative charge pulse is introduced at node I1, the level "1" immediately decreases, causing PMOS transistor P4 to turn on and NMOS transistor N2 to turn off. Node I4 generates a weak "1" level, while PMOS transistor P1 is temporarily turned off. Nodes I2 and I3 are unaffected by the I1 flip, keeping NMOS transistor N4 on. Therefore, node I4 is pulled down to a strong "0" level by NMOS transistor N4, achieving SEU self-repair. Subsequently, PMOS transistor P1 turns on again, pulling node I1 back up to logic "1". Ultimately, the generated single-event upset recovers quickly without affecting data reading.

[0063] j. After a positive charge pulse is introduced at node I2, the voltage level "0" immediately rises, causing PMOS transistor P3 to turn off and NMOS transistor N1 to turn on. NMOS transistor N1 temporarily pulls node I1 down to output a weak "0", but this weak voltage level is neutralized by the strong "1" output by the continuously conducting PMOS transistor P1, restoring node I1 to its normal state. NMOS transistor N2 then turns on again, pulling node I2 down to its normal state "0". Simulation results show that this circuit has anti-single-event upset (SOI) properties.

[0064] The above description is merely a description of preferred embodiments of the present invention and is not intended to limit the scope of the present invention in any way. Any changes or modifications made by those skilled in the art based on the above disclosure shall fall within the protection scope of the claims.

Claims

1. A non-volatile static random access memory resistant to single-event upsets, characterized in that, Including magnetic tunnel junctions MTJ1 and MTJ2, NMOS transistors N1~N10, and PMOS transistors P1~P4; The source of PMOS transistor P1 is connected to VDD, and the drain of PMOS transistor P1 is connected to the drain of NMOS transistor N1, with the connection point at node I1; the source of NMOS transistor N1 is grounded. The source of PMOS transistor P2 is connected to VDD, and the drain of PMOS transistor P2 is connected to the drain of NMOS transistor N2, with the connection point at node I2; the source of NMOS transistor N2 is grounded. The source of PMOS transistor P3 is connected to VDD, and the drain of PMOS transistor P3 is connected to the drain of NMOS transistor N3, with the connection point at node I3; the source of NMOS transistor N3 is grounded. The source of PMOS transistor P4 is connected to VDD, and the drain of PMOS transistor P4 is connected to the drain of NMOS transistor N4, with the connection point at node I4; the source of NMOS transistor N4 is grounded. The drain of NMOS transistor N9 is connected to the drain of NMOS transistor N1 at node I1. The source of NMOS transistor N9 is connected to the variable magnetic layer of magnetic tunnel junction MTJ1. The fixed magnetic layer of magnetic tunnel junction MTJ1 is connected to the TE control signal. The drain of NMOS transistor N10 is connected to the drain of NMOS transistor N4 at node I4. The source of NMOS transistor N10 is connected to the variable magnetic layer of magnetic tunnel junction MTJ2. The fixed magnetic layer of magnetic tunnel junction MTJ2 is connected to the TE control signal. The drain of NMOS transistor N5 is connected to the drain of NMOS transistor N1 at node I1, and the source of NMOS transistor N5 is connected to the bit line signal BL; the drain of NMOS transistor N7 is connected to the drain of NMOS transistor N3 at node I3, and the source of NMOS transistor N7 is connected to the bit line signal BL. The drain of NMOS transistor N6 is connected to the drain of NMOS transistor N2 at node I2. The source of NMOS transistor N6 is connected to the complementary bit line signal BLB. The drain of NMOS transistor N8 is connected to the drain of NMOS transistor N4 at node I4. The source of NMOS transistor N8 is connected to the complementary bit line signal BLB. The gate of PMOS transistor P1 is simultaneously connected to the drain of PMOS transistor P4 and the gate of NMOS transistor N3; the gate of PMOS transistor P2 is simultaneously connected to the drain of NMOS transistor N3 and the gate of NMOS transistor N4; the gate of PMOS transistor P3 is simultaneously connected to the drain of NMOS transistor N2 and the gate of NMOS transistor N1; the gate of PMOS transistor P4 is simultaneously connected to the drain of NMOS transistor N1 and the gate of NMOS transistor N2. The gate of NMOS transistor N9 is connected to the SW control signal; the gate of NMOS transistor N10 is connected to the SW control signal. The gate of NMOS transistor N5 is connected to the word line signal WL; the gate of NMOS transistor N6 is connected to the word line signal WL; the gate of NMOS transistor N7 is connected to the word line signal WL; the gate of NMOS transistor N8 is connected to the word line signal WL.

2. The non-volatile static random access memory resistant to single-event upsets as described in claim 1, characterized in that, The growth structure of the magnetic tunnel junctions MTJ1 and MTJ2 is a ferromagnetic layer / non-magnetic insulating layer / ferromagnetic layer. The data storage method utilizes the different resistance values ​​of the two ferromagnetic layers when they are parallel and non-parallel. The data writing method utilizes a small current passing through the magnetic tunnel junction to cause the ferromagnetic layer to flip, thereby changing the logic state.

3. The non-volatile static random access memory resistant to single-event upsets as described in claim 1, characterized in that, Before data is written, the bit line signal BL of the non-volatile static random access memory is preset to "1", and the complementary bit line signal BLB is preset to "0". When the word line signal WL is set to "1", it controls NMOS transistors N5, NMOS transistor N6, NMOS transistor N7 and NMOS transistor N8 to turn on. The bit line signal BL charges node I1 through NMOS transistor N5 and charges node I3 through NMOS transistor N7, so that nodes I1 and I3 are written with logic "1". The complementary bit line signal BLB discharges node I2 through NMOS transistor N6 and node I4 through NMOS transistor N8, causing nodes I2 and I4 to be written with logic "0". Finally, the data "1, 0, 1, 0" is written to the four storage nodes I1, I2, I3 and I4 in sequence, completing the write operation of logic "1". Since the non-volatile static random access memory is designed symmetrically, it is also applicable when storing data as logic "0".

4. The non-volatile static random access memory resistant to single-event upsets as described in claim 1, characterized in that, The logic states of the magnetic tunnel junctions MTJ1 and MTJ2 are always complementary. When the TE control signal is set to "0", because nodes I1 and I3 are at a high level, current flows from nodes I1 and I3 to TE, causing the magnetic tunnel junction MTJ1 to change from antiparallel to parallel, thus realizing the writing of logic "1" into the magnetic tunnel junction MTJ1. When the TE control signal is set to "1", the current flows from TE to nodes I2 and I4, causing the magnetic tunnel junction MTJ2 to change from antiparallel to parallel, thus writing logic "0" into the magnetic tunnel junction MTJ2; finally, the non-volatile write operation is completed.

5. The non-volatile static random access memory resistant to single-event upsets as described in claim 1, characterized in that, The single-event sensitive nodes of the static random access memory are the drain of the PMOS transistor and the source of the NMOS transistor that are turned off. The nodes that may generate single-event pulse current are I1, I2, I3 and I4. If a single-event upset (SWE) occurs at sensitive node I1, flipping from logic "1" to logic "0", it turns on PMOS transistor P4 and turns off NMOS transistor N2, resulting in a weak "1" level at node I4. Simultaneously, PMOS transistor P1 is temporarily turned off. Nodes I2 and I3 are unaffected by the I1 flip, and NMOS transistor N4 remains on. Therefore, node I4 is pulled down to a strong "0" level by NMOS transistor N4, achieving SEU self-repair. Subsequently, PMOS transistor P1 turns back on, pulling node I1 up to logic "1". Ultimately, the generated SWE recovers quickly without affecting data reading. If a single-event upset (SET) occurs at sensitive node I2, flipping from logic "0" to logic "1", PMOS transistor P3 turns off and NMOS transistor N1 turns on. NMOS transistor N1 temporarily pulls node I1 down to output a weak "0". This weak "0" is neutralized by the strong "1" output by the continuously conducting PMOS transistor P1, restoring node I1. NMOS transistor N2 then turns on again, also pulling node I2 down to logic "0". Due to the symmetrical design of the non-volatile static random access memory, the SET is also applicable to nodes I3 and I4.

6. The non-volatile static random access memory resistant to single-event upsets as described in claim 1, characterized in that, The characteristic dimensions of the NMOS transistors N1~N10 and the PMOS transistors P1~P4 range from 7 nm to 130 μm.

7. The non-volatile static random access memory resistant to single-event upsets as described in claim 1, characterized in that, The non-volatile static random access memory is suitable for radiation-hardened circuits that use magnetic tunnel junctions as non-volatile memory cells.

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