A memory testing method, a training method and a memory system

Abstract

The application discloses a memory testing method, a training method and a storage system. The memory testing method is used for a memory including a plurality of memory blocks, each memory block including a data latch and a plurality of memory arrays coupled with the data latch. The method includes: obtaining a target command according to an error type, the target command including a first type of operation command, the first type of operation command including memory block information; and detecting the memory block with the target command, the detection including performing a corresponding operation on the data latch corresponding to the memory block information with the first type of operation command. The application can improve fault distinguishing efficiency.

Description

Technical Field

[0001] This application relates to the field of memory technology, specifically to a memory testing method, training method, and storage system. Background Technology

[0002] The operation modes of a memory include memory testing and training. Memory testing is used to ensure the reliability and performance of the memory, ensuring that it can work properly and that data is stored accurately. Memory training is used to optimize the memory's operating parameters so that it can achieve optimal performance under different hardware environments and operating conditions.

[0003] Currently, memory anomaly testing largely relies on normal read / write commands, i.e., accessing the memory array through normal read / write commands carrying row and column address information. The memory training process is based on MPR (Multipurpose Register) mode. Specifically, the controller sends a configuration command to the memory to enter MPR mode, masking memory cell addressing and decoding read / write commands as accesses to fixed MPR page registers. During training, the memory presets the output data of the MPR registers. The controller compares the received data with the known output pattern, calibrates the timing offset of the read / write channels, and aligns the data capture window with the clock.

[0004] However, during memory anomaly testing, if errors occur in the read / write results obtained using normal read / write commands, it's impossible to distinguish whether the error stems from an anomaly in the control logic module's decoding and addressing process or from damage to the memory cell itself. Further investigation and cross-testing are required to differentiate between these two types of faults, leading to low testing efficiency. Furthermore, command decoding in MPR mode differs significantly from normal commands. The read / write path during training bypasses normal data addressing and array access processes, interacting only through the data buffer and MPR registers. This results in a significant difference between the read / write training path under MPR commands and the complete read / write path during normal memory operation, making it difficult to accurately reflect the actual operating characteristics of the memory and consequently leading to poor read / write training results.

[0005] In summary, the aforementioned testing and training of memory systems suffer from problems such as low fault differentiation efficiency and significant deviations between training results and actual operating conditions. Summary of the Invention

[0006] This application provides a testing method, training method, and storage system for a memory, in order to improve fault differentiation efficiency and training effect.

[0007] In a first aspect, this application provides a method for testing a memory, the memory comprising a plurality of memory blocks, each memory block comprising a data latch and a plurality of memory arrays coupled to the data latch, the method comprising: The target command is obtained based on the error type. The target command includes the first type of operation command, which includes storage block information. The storage block is detected using the target command. The detection includes performing the corresponding operation on the data latch corresponding to the storage block information using the first type of operation command.

[0008] In some embodiments of this application, the error type includes read error; when the error type is read error, the first type of operation command includes a first write command and a first read command, both of which include storage block information.

[0009] In some embodiments of this application, detecting storage blocks with target commands includes: Based on the first write command, write the first test data to the data latch corresponding to the storage block information; After writing the first test data, the first read data is obtained from the data latch corresponding to the storage block information based on the first read command; The first test data and the first read data are compared to obtain the functional test results of the storage block.

[0010] In some embodiments of this application, comparing the first test data and the first read data to obtain the functional detection result of the storage block includes: when the first test data and the first read data are the same, determining that the functional detection result of the storage block is an abnormal read function of the storage array; When the first test data and the first read data are different, the cause of the anomaly is located through step-by-step detection and functional isolation analysis.

[0011] In some embodiments of this application, the error type includes a write error; when the error type is a write error, the target command further includes a second write command, which includes storage block information and storage array information, and the first type of operation command is a first read command, which includes storage block information.

[0012] In some embodiments of this application, detecting storage blocks with target commands includes: The second test data is written to the data latch corresponding to the storage block information based on the second write command; Based on the second write command, the second test data stored in the data latch is written to the storage array corresponding to the storage array information; After writing the second test data to the storage array, the second read data is obtained from the data latch corresponding to the storage block information based on the first read command; The second test data and the second read data are compared to obtain the functional test results of the storage block.

[0013] In some embodiments of this application, the second test data and the second read data are compared to obtain the functional test result of the storage block, including: When the second test data and the second read data are different, the write function between the storage block and the controller is abnormal. The write function of the storage array malfunctions when the second test data and the second read data are the same.

[0014] Secondly, this application also provides a training method for a memory, the memory comprising a plurality of memory blocks, each memory block comprising a data latch and a plurality of memory arrays coupled to the data latch, comprising: The target command is obtained according to the training type. The target command includes the first type of operation command, which includes storage block information. The storage block is trained using the target command. The training includes executing the corresponding operation on the data latch corresponding to the storage block information using the first type of operation command.

[0015] In some embodiments of this application, the training type includes read training; when the training type is read training, the first type of operation command includes a first read command, the first read command includes storage block information, and training the storage block with the target command includes: When the memory enters multipurpose register mode, pre-stored data is read from the mode register corresponding to the memory block information based on the first read command; Based on the pre-stored data being read, the read channel between the memory and the controller is adjusted.

[0016] In some embodiments of this application, the training type includes write training; when the training type is write training, the first type of operation command includes a first read command and a first write command, both of which include storage block information. Training the storage block with the target command includes: When the memory exits multi-purpose register mode, the first training data is written to the memory block corresponding to the memory block information based on the first write command; After writing the first training data, the second training data is read from the data latch corresponding to the first read command from the storage block information. The first and second training data are compared, and the write channel is adjusted based on the comparison results.

[0017] Thirdly, this application also provides a storage system, comprising: The memory includes a controller and several memory blocks, each memory block including a data latch and several memory arrays, the data latch being coupled to the controller and the several memory arrays; The controller is configured to use either the testing method provided in the first aspect or the training method provided in the second aspect.

[0018] Through one or more embodiments of the above embodiments in this application, at least the following technical effects can be achieved: In the memory testing method provided in this application, a target command is obtained according to the error type, and a read or write operation is performed on the data latch corresponding to the memory block information using the first type of operation command in the target command. The read and write results of the data latch can directly reflect whether it is a logic module or data path failure or a memory array read and write function failure, thereby effectively improving the accuracy of fault location and detection efficiency.

[0019] Furthermore, when the error type is a read error, targeted write and read tests can be performed on the memory using the first write command and the first read command. During this test, the first write command and the first read command only contain memory block information, and both operate solely on the data latch. Since neither the first write command nor the first read command involves specific address or data access operations of the memory array, the scope and complexity of the test operations are significantly reduced, improving test efficiency. In addition, when the first test data matches the first read data, it can be determined that the read function of the memory array is abnormal. That is, the read function fault of the memory array can be accurately located through the first read data, thereby achieving rapid detection and location of memory read function anomalies.

[0020] Furthermore, when the error type is a write error, targeted write and read tests are performed on the memory using a second write command and a first read command. The second write command includes memory block information and memory array information (including row and column addressing information of the memory array). When executing the second write command, the second test data is first written to the data latch corresponding to the memory block information, and then written to the memory array corresponding to the memory array information. The first read command only contains memory block information, and its effect is limited to the data latch. This command allows direct reading of the previously written second test data from the data latch. By comparing the second read data obtained from the first read command with the original second test data, the source of the fault can be clearly distinguished: if the comparison results are consistent and a write error is clearly present, it indicates an anomaly in the write function of the memory array; if the comparison results are inconsistent, it indicates a functional anomaly in the data write path between the memory block and the controller. Because it is possible to quickly locate whether the anomaly is in the write function of the memory array, the data write path between the memory block and the controller, or the controller itself during a single test, testing efficiency is significantly improved.

[0021] In the memory training method provided in this application, a first type of operation command containing memory block information is used to perform corresponding operations on the data latch corresponding to the memory block information, thereby achieving memory block training. Since the first type of operation command not only carries memory block information during execution but also triggers the corresponding data latch to perform actual operations, the training process maintains a high degree of consistency with the conventional read / write operations of the memory in terms of signal transmission path, decoding logic, and data processing flow. Therefore, the training method provided in this application makes the training process closer to the actual working state of the memory. Compared with training using MPR instructions, it can obtain more accurate training results, thereby significantly improving the training effect and ensuring the stability and reliability of the memory in subsequent applications. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this application, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a module structure diagram of a memory embodiment; Figure 2 This is a schematic diagram of the memory structure provided in an embodiment of this application; Figure 3 This is one of the flowcharts illustrating the memory testing method provided in the embodiments of this application; Figure 4 This is a second schematic flowchart of the memory testing method provided in the embodiments of this application; Figure 5 This is the third flowchart illustrating the memory testing method provided in this application embodiment; Figure 6 This is one of the flowcharts illustrating the memory training method provided in the embodiments of this application; Figure 7 This is a second schematic flowchart of the memory training method provided in the embodiments of this application; Figure 8 This is the third flowchart illustrating the memory training method provided in this application embodiment. Detailed Implementation

[0024] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0025] The terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, features defined as "first" or "second" may explicitly or implicitly include one or more features. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0026] "A and / or B" includes the following three combinations: A only, B only, and a combination of A and B.

[0027] The use of "applies to" or "configured to" in this application implies open and inclusive language, which does not preclude applicability to or configuration to devices performing additional tasks or steps. Furthermore, the use of "based on" implies openness and inclusivity, because processes, steps, calculations, or other actions "based on" one or more conditions or values ​​may in practice be based on additional conditions or values ​​beyond those conditions.

[0028] In this application, the term "exemplary" is used to mean "used as an example, illustration, or description." Any embodiment described as "exemplary" in this application is not necessarily to be construed as being more preferred or advantageous than other embodiments. The following description is provided to enable any person skilled in the art to make and use this application. Details are set forth in the following description for purposes of explanation. It should be understood that those skilled in the art will recognize that this application can be made without using these specific details. In other instances, well-known structures and processes are not described in detail to avoid obscuring the description of this application with unnecessary detail. Therefore, this application is not intended to be limited to the embodiments shown, but is consistent with the broadest scope of the principles and features disclosed in this application.

[0029] Figure 1 This is a module structure diagram of a memory embodiment. The memory includes a controller and several memory blocks, each memory block comprising several memory arrays. The controller receives read / write commands sent by an external host and performs addressing and access control on the target memory block based on the row and column address information in the read / write commands. The memory blocks store data and perform corresponding data read / write operations according to the access control signals issued by the controller.

[0030] During a regular read operation of the memory, the controller activates the word line of the target memory cell based on the row address information of the memory array carried in the read command, and selects the corresponding bit line based on the column address information, thereby reading the stored data from the target memory cell and outputting it to the external host. During a regular write operation of the memory, the controller selects the target memory cell based on the row and column address information of the memory array carried in the write command, and drives the received write data signal to the target memory cell during the write cycle to realize the storage of data.

[0031] A memory control logic module failure refers to an abnormality in the logic circuitry within the memory used for address decoding, command parsing, and read / write control. This manifests as read / write operations failing to execute as expected, incorrect address selection, or abnormal command response. A memory array failure, on the other hand, refers to damage or malfunction of the specific memory array itself, resulting in abnormal data read or write operations within a specific address or row / column range.

[0032] In the existing DDR memory protocol, regular read and write commands are performed on the memory array. Only in MPR (Multipurpose Register) mode are read and write commands redirected to a special MPR Register.

[0033] However, when a memory read / write failure occurs, the existing read / write commands cannot effectively and quickly locate the specific fault area. Generally, read / write function anomalies can be broadly categorized into the following three types: Controller error: The controller sends instructions that do not conform to the storage protocol requirements, causing the memory to be unable to perform read and write operations correctly; Control logic malfunction: The control logic module inside the memory is malfunctioning and has not transmitted the correct control signals to the target memory cell. Storage cell malfunction: The storage cell itself is defective and fails to complete read / write operations correctly.

[0034] When troubleshooting memory read / write functions, existing MPR commands can, to some extent, eliminate controller anomalies. This is because, in MPR mode, the data read / write access path is simplified, and if the controller sends instructions that do not meet protocol requirements, the memory will not be able to enter MPR mode, thus allowing such problems to be identified promptly.

[0035] However, because MPR commands and ARRAY read / write commands differ in their decoding methods and access completely different storage areas, MPR mode can only verify the correctness of the protocol interaction layer and cannot reflect the integrity of the ARRAY access path. Therefore, when the problem stems from control logic anomalies or storage unit anomalies, even if the read / write test passes in MPR mode, it does not indicate that the ARRAY access path is normal.

[0036] To address the aforementioned issues, embodiments of this application provide a testing method, training method, and storage system for a memory. The testing method, training method, and storage system for a memory provided in this application are described below with reference to the accompanying drawings.

[0037] Figure 2 This application describes a memory system comprising: a plurality of memory blocks, each memory block including a data latch and a plurality of memory arrays coupled to the data latch. A controller is configured to receive read / write commands sent by an external host and to perform addressing and access control on the target memory block based on the row and column address information in the read / write commands; the memory blocks are configured to store data and perform corresponding data read / write operations according to access control signals issued by the controller.

[0038] like Figure 3 As shown, Figure 3 This application provides an embodiment of such a method. Figure 2 The test method for the memory shown includes the following steps: S101, Obtain the target command according to the error type. The target command includes a first type of operation command, which includes storage block information.

[0039] Error types include read errors and write errors. The first type of operation command can be a read command, a write command, or a combination of both. Storage block information is used to specify the storage block (Bank) to be operated on; based on this information, the target storage block for the operation can be located from several storage arrays.

[0040] S102, the storage block is detected by the target command, and the detection includes performing the corresponding operation on the data latch corresponding to the storage block information by the first type of operation command.

[0041] The memory testing method provided in this application obtains the target command according to the error type, and uses the first type of operation command in the target command to perform read or write operations on the data latch corresponding to the memory block information. The read and write results of the data latch can directly reflect whether it is a logic module or data path failure or a memory array read and write function failure, thereby effectively improving the accuracy of fault location and detection efficiency.

[0042] In some embodiments of this application, the error type includes a read error; when the error type is a read error, the first type of operation command includes a first write command and a first read command, both of which include storage block information. It is understood that a read error refers to a situation where, during a read operation in the memory, the data actually read is inconsistent with the data that should have been read. In determining if a read error has occurred, it is necessary to determine whether the error is due to a control logic malfunction or a malfunction in the read function of the storage unit in order to pinpoint the cause of the malfunction.

[0043] like Figure 4 As shown, in the case of a read error, S102 includes: S401: Based on the first write command, write the first test data to the data latch corresponding to the storage block information. It can be understood that the first write command includes the first test data, which can be all "0"s, all "1"s, alternating "0"s and "1"s, or a pseudo-random sequence of data; there are no restrictions. The target commands include the first write command and the first read command.

[0044] S402, after writing the first test data, the first read data is obtained from the data latch corresponding to the storage block information based on the first read command.

[0045] S403, compare the first test data and the first read data to obtain the functional test result of the storage block.

[0046] S404, if the first test data and the first read data are the same, it can be determined that the read and write functions of the data latch itself are normal. However, since the aforementioned error type is a read error, it is determined that the error occurred during the transmission from the storage array to the data latch, that is, the storage array failed to correctly perform the data read operation.

[0047] If the first test data and the first read data are different, it indicates that the anomaly may not only involve write or hold errors in the data latch itself, but may also be related to transmission errors between the data latch and the external interface, or even address decoding or command execution anomalies in the control logic module. Such situations usually mean that the source of the fault is more complex, requiring further step-by-step detection and functional isolation analysis. For example, checking the functional status of the data latch, interface path, and control logic module sequentially to gradually narrow down the fault range and ultimately locate the cause of the anomaly.

[0048] Understandably, the abnormal storage block can be quickly located based on the abnormal read function results of the storage array.

[0049] In the memory testing method provided in this application embodiment, when the error type is a read error, targeted write and read tests can be performed on the memory using a first write command and a first read command. During this test, the first write command and the first read command only contain memory block information, and both operate solely on the data latch. Since neither the first write command nor the first read command involves specific addresses or data access operations of the memory array, the scope and complexity of the test operations are significantly reduced, improving test efficiency. Furthermore, when the first test data matches the first read data, it can be determined that the read function of the memory array is abnormal. That is, the read function fault of the memory array can be accurately located through the first read data, thereby achieving rapid detection and location of memory read function abnormalities.

[0050] In some embodiments of this application, the error type includes a write error; when the error type is a write error, the target command includes a second write command and a first read command, the second write command includes storage block information and storage array information, and the first read command includes storage block information.

[0051] Understandably, when responding to the second write command to perform a write operation, the target storage block is first determined based on the storage block information, and then the target storage array is determined based on the row and column address information in the storage array information. Based on this, the second write command first writes the data it carries to the data latch corresponding to the target storage block, and then writes the data it carries to the target storage array. The aforementioned first write command's write process involves determining the target storage block based on the storage block information, and then writing the data carried by the first write command to the data latch corresponding to the target storage block, bypassing the data writing to the storage array. Similarly, the first read command's read process involves determining the target storage block based on the storage block information in the first read command, and reading the data from the data latch corresponding to the target storage block. In the case of a write error, it is necessary to determine whether the write error is due to a control logic anomaly or a storage unit read function anomaly, in order to pinpoint the cause of the anomaly.

[0052] like Figure 5 As shown, in the case of a write error, S102 includes: S501: Based on the second write command, write the second test data to the data latch corresponding to the storage block information. It can be understood that the second write command includes the second test data.

[0053] S502, based on the second write command, writes the second test data stored in the data latch to the memory array corresponding to the memory array information. That is, after writing the second test data to the data latch, it is then written to the corresponding memory array. During this process, the control logic module needs to complete address decoding, write enable control, and bit / word line driving to ensure that the second test data is accurately written to the target memory array.

[0054] S503, after writing the second test data to the storage array, the second read data is obtained from the data latch corresponding to the storage block information based on the first read command.

[0055] S504: Compare the second test data and the second read data to obtain the functional test results of the storage block.

[0056] S505, when the second test data and the second read data are different, it indicates that the second test data has already encountered an error before being written to the storage array, meaning there is an anomaly in the data write function between the storage block and the controller. In other words, the second test data written by the controller via the second write command has already erred when it enters the data latch stage, causing the second read data read from the latch to be inconsistent with the expected second test data. This indicates a problem in the link from the controller to the data latch, such as an abnormal data bus transmission or an abnormal latch write circuit.

[0057] S506, when the second test data and the second read data are the same, since a write error has been clearly identified earlier, and the second test data is correct in the process of writing to the data latch, it is determined that an anomaly has occurred in the process of writing from the data latch to the memory array, that is, an error has occurred in the process of writing or reading from the memory array. Specifically, it may involve word line, bit line drive, insufficient write current of the memory array, or insufficient memory array holding capability.

[0058] The memory testing method provided in this application performs targeted write and read tests on the memory using a second write command and a first read command when the error type is a write error. The second write command includes memory block information and memory array information (including row and column addressing information of the memory array). When executing the second write command, the second test data is first written to the data latch corresponding to the memory block information, and then written to the memory array corresponding to the memory array information. The first read command only contains memory block information, and its effect is limited to the data latch. This command allows direct reading of the previously written second test data from the data latch. By comparing the second read data obtained from the first read command with the original second test data, the source of the fault can be clearly distinguished: if the comparison results are consistent and a write error is clearly present, it indicates that the write function of the memory array is abnormal; if the comparison results are inconsistent, it indicates that there is a functional abnormality in the data write path between the memory block and the controller. Because it can quickly locate whether the abnormality is in the write function of the memory array, the data write path between the memory block and the controller, or the controller itself during a single test, the testing efficiency is significantly improved.

[0059] In some embodiments of this application, a write error test is first performed on the memory using a second write command (containing second test data) and a first read command (in the write error test, the first read command reads the second read data). If the second test data and the second read data are the same, it is determined that the write function between the memory block and the controller is normal. Then, a read error test is performed on the memory using a first write command (containing first test data) and a first read command (in the read error test, the first read command reads the first read data). If the first test data and the first read data are the same, it is determined that the read function of the memory array is abnormal. By first determining that the write function between the memory block and the controller is normal, the abnormality of the read function of the memory array is then detected.

[0060] Furthermore, in existing DDR memory protocols, most regular read / write commands operate on the memory array. These commands contain row and column address information for the memory array. After row and column address decoding, the target cell is selected to complete the data read / write operation. In contrast, in MPR (Multipurpose Register) mode, commands are redirected to the MPR Register. Data interaction between the controller and memory no longer accesses the memory array but directly reads and writes registers within the MPR.

[0061] Based on the aforementioned MPR mode, the memory training process is as follows: The controller sends a setting command to the memory to enter MPR mode. Addressing of memory cells is masked, and read / write commands do not access the memory array but are decoded to access fixed MPR Page registers. During training, the memory presets the output data of the MPR Page registers (e.g., a fixed pattern of all "0", all "1", or alternating "01"). The controller then compares the received data with these known output patterns to calibrate the timing offset of the read / write channels, achieving alignment between the data capture window (DQDQS) and the clock.

[0062] However, the decoding method differs significantly from that of ordinary commands in MPR mode: MPR commands no longer parse the row and column address information of the memory array, but directly map the command to the access logic of the MPR register. Therefore, the read / write path during training bypasses the normal data addressing and array access process, interacting only with the MPR register through the data buffer (I / O buffer). In contrast, conventional read / write commands containing memory array address information require a complete process during decoding, including row address decoding, column address decoding, memory array cell access, and data latching, resulting in a longer signal propagation path and involving more circuit modules. Thus, in MPR mode, the data transmission path during read / write training is mainly concentrated between the MPR register and the controller, without involving the actual working stages such as memory array addressing, row and column decoding, and data latching near the memory array. Therefore, the read / write training path under MPR commands differs significantly from the complete read / write path formed by read / write commands containing row and column address information under normal memory operation, failing to accurately reflect the actual operating characteristics of the memory and leading to poor read / write training results.

[0063] To address the issue of poor read / write training performance, this application also provides a training method for a memory. The memory includes several memory blocks, each memory block including a data latch and several memory arrays coupled to the data latch. Based on the aforementioned memory, the corresponding training method is as follows: Figure 6 As shown, it includes the following steps: S201, Obtain the target command according to the training type. The target command includes the first type of operation command, which includes storage block information.

[0064] S202, the storage block is trained using target commands. The training includes executing corresponding operations on the data latches corresponding to the storage block information using first-type operation commands. The first-type operation commands include a first read command and / or a first write command, which enable read or write operations.

[0065] The memory training method provided in this application employs a first type of operation command containing memory block information to perform corresponding operations on the data latches corresponding to the memory block information, thereby achieving memory block training. Since the first type of operation command not only carries memory block information during execution but also triggers the corresponding data latches to perform actual operations, the training process maintains a high degree of consistency with the conventional read / write operations of the memory in terms of signal transmission paths, decoding logic, and data processing flows. Therefore, the training method provided in this application makes the training process closer to the actual working state of the memory. Compared with training using MPR instructions, it can obtain more accurate training results, thereby significantly improving the training effect and ensuring the stability and reliability of the memory in subsequent applications.

[0066] In some embodiments of this application, the training type includes read training; when the training type is read training, the first type of operation command includes a first read command, which includes storage block information.

[0067] like Figure 7 As shown, in the case of read-based training, S202 includes: S701, when the memory enters multi-purpose register mode, reads pre-stored data from the mode register corresponding to the memory block information based on the first read command.

[0068] S702 adjusts the read channel between the memory and the controller based on the pre-stored data being read.

[0069] Schematic, when the memory enters the multipurpose register (MPR) mode, the controller reads the pre-stored data Pattern from the mode register corresponding to the memory block information based on the first read command. This pre-stored data is specific data, such as all "0" data, all "1" data, alternating "01" data, etc.

[0070] After reading the pre-stored data, the controller compares the read data with the pre-stored data and, based on the comparison result, detects whether there are timing offsets, sampling errors, or signal distortions in the data transmission path between the memory and the controller. Therefore, the controller can dynamically adjust read channel parameters, such as clock offset, phase calibration, sampling window position, and level reference voltage, to compensate for read channel deviations caused by factors such as process variations, operating voltage fluctuations, and temperature changes.

[0071] The memory training process provided in this application embodiment, through the above-described read training process based on MPR mode and the first read command, can quickly and stably calibrate the read channel of the memory without relying on actual storage units, thereby shortening the initialization time and improving the data stability and reliability of subsequent normal read operations.

[0072] In some embodiments of this application, the training type includes write training; when the training type is write training, the first type of operation command includes a first read command and a first write command, both of which include storage block information.

[0073] like Figure 8 As shown, in the case of write training, S202 includes: S801: When the memory exits the multipurpose register mode, the first training data is written to the memory block corresponding to the memory block information based on the first write command.

[0074] S802, after writing the first training data, read the second training data from the data latch corresponding to the first read command from the storage block information.

[0075] S803 compares the first training data and the second training data, and adjusts the write channel based on the comparison result.

[0076] Schematic, when the memory exits multipurpose register mode, the controller writes the first training data into the memory block corresponding to the memory block information based on the first write command.

[0077] After writing the first training data, the controller reads the second training data from the data latch corresponding to the storage block information based on the first read command. The second training data is the storage and output result of the memory on the first training data under the current write channel configuration.

[0078] The controller compares the first training data with the second training data to detect whether there are data inconsistencies caused by bit flips, timing offsets, or electrical noise under the current write channel delay, drive strength, DQ-DQS alignment, and other parameter configurations. If the comparison results are consistent, the current configuration is deemed valid; if the comparison results are inconsistent, the write channel configuration parameters between the memory and the controller are adjusted, such as the step-by-step scan write delay, the phase relationship between the data strobe signal and the write clock, and the data drive voltage swing.

[0079] During the comparison and adjustment process, the controller can employ multiple iterative training methods, i.e., writing and comparing multiple different sets of initial training data to improve the statistical effectiveness and anti-interference capability of the training. Finally, based on the consistent parameter combinations from the comparison, the optimal configuration of the write channel is determined, thereby ensuring the correctness and timing stability of data writing under subsequent normal operating conditions.

[0080] The memory training method provided in this application can effectively compensate for the uncertainty of the write channel caused by manufacturing process differences, temperature drift, power fluctuations and signal integrity issues through the write training process of the first read command and the first write command, thereby improving the accuracy and reliability of data writing.

[0081] Based on any of the above embodiments, another embodiment of this application also provides a storage system, including: The memory includes a controller and several memory blocks, each memory block including a data latch and several memory arrays, the data latch being coupled to the controller and the several memory arrays.

[0082] The controller is configured to perform a test method or a training method as provided in any of the above embodiments.

[0083] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate, and the components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0084] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., including several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods of various embodiments or some parts of embodiments.

[0085] The above provides a detailed description of a memory testing method, training method, and storage system provided by the embodiments of this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The description of the above embodiments is only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.

Claims

1. A method for testing a memory, the memory comprising a plurality of memory blocks, each memory block comprising a data latch and a plurality of memory arrays coupled to the data latch, characterized in that, The method includes: The target command is obtained based on the error type. The target command includes a first type of operation command, which includes storage block information. The error types include read errors and write errors. The target command includes a first write command, a first read command, and a second write command. The storage block is detected using the target command, and the detection includes performing a corresponding operation on the data latch corresponding to the storage block information using the first type of operation command.

2. The testing method for the memory according to claim 1, characterized in that, In the case of a read error, the first type of operation command includes a first write command and a first read command, both of which include the storage block information.

3. The testing method for the memory according to claim 2, characterized in that, The detection of the storage block using the target command includes: Based on the first write command, write the first test data to the data latch corresponding to the storage block information; After writing the first test data, the first read data is obtained from the data latch corresponding to the storage block information based on the first read command; The first test data and the first read data are compared to obtain the functional test result of the storage block.

4. The testing method for the memory according to claim 3, characterized in that, Comparing the first test data and the first read data to obtain the functional detection result of the storage block includes: when the first test data and the first read data are the same, determining that the functional detection result of the storage block is that the read function of the storage array is abnormal; When the first test data and the first read data are different, the cause of the anomaly is located through step-by-step detection and functional isolation analysis.

5. The testing method for the memory according to claim 1, characterized in that, In the case where the error type is a write error, the target command further includes a second write command, which includes storage block information and storage array information, and the first type of operation command is a first read command, which includes the storage block information.

6. The testing method for the memory according to claim 5, characterized in that, The step of detecting the storage block using the target command includes: Based on the second write command, write the second test data to the data latch corresponding to the storage block information; Based on the second write command, the second test data stored in the data latch is written to the storage array corresponding to the storage array information; After writing the second test data to the storage array, the second read data is obtained from the data latch corresponding to the storage block information based on the first read command; The second test data and the second read data are compared to obtain the functional test result of the storage block.

7. The testing method for the memory according to claim 6, characterized in that, The step of comparing the second test data and the second read data to obtain the functional test result of the storage block includes: When the second test data and the second read data are different, the write function between the storage block and the controller is abnormal; When the second test data and the second read data are the same, the write function of the storage array is abnormal.

8. A training method for a memory, the memory comprising a plurality of memory blocks, each memory block comprising a data latch and a plurality of memory arrays coupled to the data latch, characterized in that, include: The target command is obtained according to the training type. The target command includes a first type of operation command, which includes storage block information. The storage block is trained using the target command, and the training includes performing corresponding operations on the data latch corresponding to the storage block information using the first type of operation command.

9. The training method for the memory according to claim 8, characterized in that, The training type includes read training; when the training type is read training, the first type of operation command includes a first read command, the first read command includes the storage block information, and training the storage block with the target command includes: When the memory enters multipurpose register mode, pre-stored data is read from the mode register corresponding to the memory block information based on the first read command; Based on the pre-stored data read, the read channel between the memory and the controller is adjusted.

10. The training method for the memory according to claim 8, characterized in that, The training type includes write training; when the training type is write training, the first type of operation command includes a first read command and a first write command, both of which include the storage block information. Training the storage block with the target command includes: When the memory exits the multipurpose register mode, first training data is written to the memory block corresponding to the memory block information based on the first write command; After writing the first training data, the second training data is read from the data latch corresponding to the storage block information based on the first read command; The first training data and the second training data are compared, and the write channel is adjusted based on the comparison results.

11. A storage system, characterized in that, include: The memory includes a controller and a plurality of memory blocks, each of the memory blocks including a data latch and a plurality of memory arrays, the data latch being coupled to the controller and the plurality of memory arrays; The controller is configured to perform the testing method as described in any one of claims 1 to 7 or the training method as described in any one of claims 8 to 10.

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