A preparation method of a non-steady cavity semiconductor laser chip and a semiconductor device

Abstract

This invention provides a method for fabricating an unstable cavity semiconductor laser chip and a semiconductor device, belonging to the field of semiconductor laser chip fabrication technology. This invention introduces an arc-shaped Bragg grating on the non-emitting cavity surface, using the Bragg grating as a reflector instead of the natural cleavage surface. To reduce the impact of the residual reflectivity of the natural cleavage surface, a high-reflection coating is deposited on the non-emitting cavity surface, achieving the high-reflectivity effect solely through the arc-shaped Bragg grating. Simultaneously, the curvature of the arc-shaped grating is designed according to the cavity length, making the designed resonant cavity an unstable cavity. This unstable cavity design increases the loss of higher-order modes, preventing lasing and reducing the number of modes within the resonant cavity, thereby effectively improving the beam quality and brightness of the semiconductor laser chip.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor laser chip fabrication technology, specifically relating to a method for fabricating an unstable cavity semiconductor laser chip and a semiconductor device. Background Technology

[0002] Semiconductor laser chips have advantages such as high photoelectric conversion efficiency, small size, and all-solid state, and have been widely used in industrial processing, scientific research and military, laser display, sensing and other fields.

[0003] In related technologies, semiconductor lasers often use the natural cleavage surface of the chip as a reflector to construct the resonant cavity. However, the flatness of the natural cleavage surface is difficult to control, resulting in unstable reflectivity and the existence of residual reflections that cannot be eliminated.

[0004] The semiconductor laser chip in the related technology adopts a stable cavity design, that is, it uses two natural cleavage surfaces of semiconductor material as mirrors of the resonant cavity, according to the resonant cavity stability criterion formula: 0< g 1 g 2<1 Where g1 = 1 - L / R1, g2 = 1 - L / R2, L is the length of the resonant cavity, and the curvature of the two cavity surface mirrors. The natural cleavage surface is a perfect mirror with infinite curvature. Therefore, current semiconductor laser chips are all designed with stable cavities. According to the characteristics of stable cavities, they not only support the operation of the fundamental transverse mode, but also have a large volume of higher-order modes. Therefore, in wide emission area designs, the number of higher-order modes in the resonant cavity is large, resulting in poor lateral beam quality.

[0005] Related technologies often leave the non-emitting cavity surface uncoated. Without coating, the natural reflectivity of the non-emitting cavity surface is high, and a large number of photons are reflected back into the cavity from the non-emitting cavity surface. Not only do they not participate in the output, but they also interfere with the main lasing mode, reducing the light output efficiency. Summary of the Invention

[0006] This invention provides a method for fabricating an unstable cavity semiconductor laser chip. By introducing an arc-shaped Bragg grating onto the non-emission cavity surface, the Bragg grating acts as a reflector instead of the natural cleavage surface. To reduce the impact of the residual reflectivity of the natural cleavage surface, a high-reflection coating is deposited on the non-emission cavity surface, achieving the high-reflectivity effect solely through the arc-shaped Bragg grating. Simultaneously, the curvature of the arc-shaped grating is designed according to the cavity length, making the designed resonant cavity unstable. This unstable cavity design increases the loss of higher-order modes, preventing lasing and reducing the number of modes within the resonant cavity, thereby effectively improving the beam quality and brightness of the semiconductor laser chip.

[0007] The methods include: S101: Provides a light-emitting active region and forms light-confining layers on both sides of the light-emitting active region to form a stacked structure; S102: A portion of the light confinement layer in the stacked structure is removed by etching, and a strip-shaped light-emitting region is defined in the lateral direction to obtain the ridge waveguide; S103: Prepare a thin film layer with high refractive index and high absorption coefficient, and cover the sidewall and upper region of the ridge waveguide with the thin film layer extending to cover a length of 2-6 μm; S104: Remove part of the light confinement layer in the arc-shaped DBR region to form the basic structure for building the Bragg grating; S105: An arc-shaped Bragg grating is constructed in the arc-shaped DBR region using electron beam lithography or nanoimprint lithography, so that the grating etching depth completely penetrates the light-emitting active region. S106: Adjust the curvature of the arc-shaped Bragg grating to match the cavity length to meet the requirements of the unstable cavity. g 1 g 2>1; S107: A low-refractive-index thin film layer of SiOX2 or SiN material is covered on the sidewall of the arc-shaped Bragg grating; S108: For non-light-emitting cavity surfaces, an arc-shaped Bragg grating is used as a high-reflectivity mirror; for non-light-emitting cavity surfaces, a high-reflectivity anti-reflection film is deposited to reduce residual reflectivity.

[0008] It should be further explained that S101 specifically includes the following steps: An underconfinement layer was grown in a metal-organic chemical vapor deposition reaction chamber using an n-type GaAs substrate. Maintaining the same temperature and pressure, a multi-quantum-well light-emitting active layer is compensated on the surface of the lower confinement layer; A p-type upper confinement layer of a predetermined thickness is epitaxially grown on the surface of the multi-quantum-well light-emitting active layer, and surface passivation is performed in the same cavity after the growth is completed. A p-type GaAs contact layer of a predetermined thickness is epitaxially grown on the surface of the upper confinement layer for ohmic contact; The epitaxial wafer is thermally annealed in a nitrogen atmosphere for a predetermined time to eliminate multi-quantum-well interface defects and activate p-type doping, forming a stacked structure.

[0009] It should be further explained that S102 specifically includes the following steps: Photoresist is coated on the upper surface of the stacked structure, and a ridge-shaped photoresist pattern is formed using photolithography. The first dry etching is performed on the photolithographically etched stacked structure to remove part of the light confinement layer and form a preliminary ridge waveguide structure. A hard mask layer is deposited on the surface of the stacked structure after the first etching. The hard mask layer was etched a second time using an ICP dry etching process. The etched layered structure is subjected to wet etching to form the ridge waveguide sidewall.

[0010] It should be further explained that S103 specifically includes the following steps: The surface of the prepared ridge waveguide structure was treated with argon plasma to remove the surface oxide layer and contaminants; A high-refractive-index, high-absorption-coefficient thin film material is deposited on the surface of the ridge waveguide using magnetron sputtering to form an initial continuous thin film layer. Positive photoresist is spin-coated onto the surface of the initial thin film layer, and a mask pattern is formed on the photoresist layer through pre-baking, ultraviolet exposure, post-baking, and development processes. Using reactive ion etching (RIE) with carbon tetrafluoride and oxygen as etching gases, the initial thin film layer is etched into a target shape covering the sidewalls of the ridge waveguide and the 2-6 μm region above it. The film thickness and refractive index were measured using an ellipsometer to verify whether they met the requirements for high refractive index, high absorption coefficient, and elongation.

[0011] It should be further explained that S104 specifically includes the following steps: The chip surface where the arc-shaped DBR region needs to be formed is cleaned to remove surface contaminants; Photoresist is spin-coated onto the cleaned chip surface and then cured using a pre-baking process. Ultraviolet lithography is performed using a pre-designed arc-shaped DBR region mask to define the arc-shaped DBR region pattern; Inductively coupled plasma etching (ICP-C) was used to remove part of the light confinement layer in the arc-shaped DBR region. Residual photoresist was removed using an oxygen plasma stripping process to complete the fabrication of the arc-shaped DBR base structure.

[0012] It should be further explained that S105 specifically includes the following steps: The surface of the light confinement layer etched by S104 in the arc-shaped DBR region was cleaned and dried. If electron beam lithography is used, electron beam photoresist is coated on the surface of the arc-shaped DBR region and then dried; if nanoimprint lithography is used, nanoimprint lithography is coated on the surface of the arc-shaped DBR region, and then the pre-made arc-shaped grating template is aligned and pressed onto the surface of the imprint lithography. In electron beam lithography, the photoresist is scanned and exposed according to the design pattern of the arc-shaped Bragg grating using an electron beam exposure system, and then developed to form a grating pattern mask. In nanoimprint lithography, the imprinted photoresist is thermally cured, and after curing, the template is peeled off to form a grating pattern mask. Using a grating pattern mask as protection, an inductively coupled plasma etching (ICP-RIE) process is employed to etch the light-emitting active region and the underlying light confinement layer of the arc-shaped DBR region, ensuring that the etching depth completely penetrates the light-emitting active region. Remove the photoresist mask or imprinting mask from the arc-shaped DBR area, and then clean the residual impurities on the surface of the arc-shaped Bragg grating formed by etching.

[0013] It should be further explained that S106 specifically includes the following steps: Retrieve the constructed arc-shaped Bragg grating, measure the current arc curvature radius R0, and record the curvature deviation of each grating unit; Based on the resonant cavity length L of the semiconductor laser and the unstable cavity condition g 1 g 2>1, g 1 represents the resonant cavity geometry factor corresponding to the arc grating, which is related to the radius of curvature R0; g 2 represents the small-signal gain coefficient of the output cavity surface. Calculate the target radius of curvature R that meets the conditions. target ; If R0 and R target If the deviation exceeds the preset deviation threshold, adjust the process parameters. According to the adjusted template, the pattern writing and etching in step S105 are repeated: after exposure and development with a new mask in electron beam lithography, ICP etching is performed; after imprinting and curing with a new template in nanoimprinting, etching is performed to form an arc-shaped Bragg grating with the target curvature. The adjusted grating curvature radius was measured again using SEM to verify whether R was achieved. target The condition g1g2>1 was confirmed to be satisfied by simulating the resonant cavity mode using optical simulation software.

[0014] It should be further explained that S107 specifically includes the following steps: The chip structure with an arc-shaped Bragg grating is subjected to surface pretreatment to remove contaminants and native oxide layers from the sidewalls of the grating; Low-refractive-index thin film materials are deposited on the chip surface using plasma-enhanced chemical vapor deposition equipment; By controlling the deposition parameters, a low-refractive-index thin film can be uniformly covered on the sidewall region of the arc-shaped Bragg grating. Rapid thermal annealing of deposited low-refractive-index films was performed to optimize film performance. The thickness and refractive index of the thin film were measured using an ellipsometer to verify whether the film quality met the requirements.

[0015] It should be further explained that S108 specifically includes the following steps: The light-emitting cavity surface of the semiconductor laser chip is cleaned with oxygen plasma. A high-reflectance film material is deposited on the light-emitting cavity surface using an electron beam evaporation deposition process; By monitoring the deposition process, the deposition thickness of the high antireflection film can be controlled within the range of 100-200 nm. The deposited film was subjected to low-temperature annealing in a nitrogen protective atmosphere; An ellipsometer was used to measure the thickness and refractive index of the high antireflection film on the non-light-emitting cavity surface to verify whether the thickness and refractive index were within the preset range.

[0016] According to another embodiment of this application, a semiconductor device is provided, which is fabricated based on the steps of the fabrication method of the unstable cavity semiconductor laser chip.

[0017] As can be seen from the above technical solutions, the present invention has the following advantages: The fabrication method of the unstable cavity semiconductor laser chip provided by this invention utilizes a stacked structure to initially restrict photon propagation in the active region through refractive index differences. A ridge waveguide defines a strip-shaped emitting region laterally, further reducing lateral light leakage. A high-refractive-index, high-absorption-coefficient thin film layer covers the sidewalls and top of the ridge waveguide, enhancing lateral light confinement and absorbing stray light from the periphery of the ridge waveguide, thus improving the directionality of light transmission. Through precise etching and electron beam lithography / nanoimprint processing, an arc-shaped Bragg grating with an etching depth completely penetrating the emitting active region is constructed in the arc-shaped DBR region, ensuring full interaction between the grating and photons in the active region. Compared to traditional naturally cleaved surface mirrors, this improves optical feedback efficiency. A low-refractive-index SiO2-SiN thin film covers the grating sidewalls, forming a significant refractive index difference with the grating semiconductor material, further reducing light leakage at the grating sidewalls while protecting the grating from contamination and extending the stability of optical feedback performance. By adjusting the curvature of the arc-shaped Bragg grating, the resonant cavity satisfies the unstable cavity condition. The divergence characteristics of the unstable cavity can increase the light leakage loss of higher-order modes, prevent the formation of lasing in higher-order modes, reduce the number of intracavity modes, and improve the beam quality of the laser. This invention uses an arc-shaped Bragg grating as a high-reflection mirror on the output cavity surface, while simultaneously depositing a high-reflection coating on the non-output cavity surface to reduce light reflection loss on the non-output cavity surface and improve light output efficiency. Attached Figure Description

[0018] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a top view of the semiconductor device involved in the fabrication method; Figure 2This is a schematic diagram of a front cross-section of a semiconductor device; Figure 3 This is a schematic diagram of a side cross-section of a semiconductor device cut along the light emission direction; Figure 4 A schematic diagram of a Bragg grating; Figure 5 This is a flowchart illustrating the fabrication process of an unstable cavity semiconductor laser chip. Detailed Implementation

[0020] The semiconductor device proposed in this invention introduces an arc-shaped Bragg grating on the non-emitting cavity surface. This Bragg grating acts as a reflector, replacing the natural cleavage surface. To reduce the impact of the residual reflectivity of the natural cleavage surface, a high-reflection coating is deposited on the non-emitting cavity surface, achieving the high-reflectivity effect solely through the arc-shaped Bragg grating. Simultaneously, the curvature of the arc-shaped grating is designed according to the cavity length, making the designed resonant cavity unstable. This unstable cavity design increases the loss of higher-order modes, preventing lasing and reducing the number of modes within the resonant cavity, thereby effectively improving the beam quality and brightness of the semiconductor laser chip.

[0021] like Figures 1 to 4 As shown, the designed and fabricated semiconductor device is a stacked structure, specifically including: a ridge waveguide 110, a thin film layer 102 with high refractive index and high absorption coefficient, an arc-shaped Bragg grating 103, a low refractive index thin film layer 103-1, a light-emitting active layer 104, an anti-reflection film 201 on the light-emitting cavity surface, and an anti-reflection film 202 on the non-light-emitting cavity surface.

[0022] In the stacked structure of this embodiment, there is a light-emitting active region and light-confining layers on both sides thereon. The ridge waveguide 110 defines a strip-shaped light-emitting region in the lateral direction by etching away part of the light-confining layer.

[0023] Thin film layer 102 is a thin film layer 103-1 with high refractive index and high light absorption coefficient covering both sides of the ridge waveguide 110.

[0024] The arc-shaped DBR region is constructed using electron beam lithography or nanoimprint lithography to form an arc-shaped Bragg grating 103. The curvature of the arc is related to the cavity length, ensuring the formation of an unstable cavity structure.

[0025] The ridge waveguide of this invention is covered with a thin film layer with high refractive index and high absorption coefficient on both sides. Simultaneously, the thin film layer covers the sidewalls of the ridge waveguide and extends 2-6 μm above the ridge waveguide. An arc-shaped Bragg grating is disposed within the arc-shaped DBR region. During fabrication, a portion of the light confinement layer is first removed; the Bragg grating is etched to a depth that completely penetrates the light-emitting active region; the arc curvature of the Bragg grating is limited by the cavity length, ensuring that the resonant cavity is unstable; the sidewalls of the Bragg grating are covered with a low refractive index thin film layer of SiO2 or SiN.

[0026] Optionally, a portion of the light confinement layer is first removed from the curved DBR region to ensure a high aspect ratio Bragg grating. The etching depth of the curved Bragg grating completely penetrates the active layer for better light feedback. The curvature of the curved Bragg grating is limited by the cavity length to ensure g1g2>1. The sidewalls of the Bragg grating are covered with a low-refractive-index thin film layer of SiO2 or SiN.

[0027] The fabrication method of the unstable cavity semiconductor laser chip involved in this application will be described in detail below. Specific details such as particular system structures and technologies are presented for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application can also be implemented in other embodiments without these specific details.

[0028] It should be understood that, when used in this specification, terms include indicating the presence of a described feature, integral, step, operation, element, and / or component, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or collections thereof. The terms include, encompass, have, and variations thereof mean including but not limited to, unless otherwise specifically emphasized.

[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0030] Please see Figure 5 The diagram shows a flowchart of a method for fabricating an unstable cavity semiconductor laser chip in a specific embodiment. The method includes: S101: Provides a light-emitting active region and forms light-confining layers on both sides of the light-emitting active region to form a stacked structure.

[0031] In some embodiments, the quantum well structure of the light-emitting active region can generate photons through carrier recombination, thereby emitting light. The refractive index of the light confinement layer differs from that of the light-emitting active region, and the principle of total internal reflection is used to confine photons within the active region, reducing light leakage to the outside.

[0032] Specifically, S101 includes the following steps: Step S1011: Select an n-type GaAs substrate and sequentially grow an n-type Al0.45Ga0.55As lower confinement layer with a thickness of 1.5μm-2.0μm in the metal-organic chemical vapor deposition reaction chamber; Step S1012: Maintaining the same temperature and pressure, continuously grow a strain-compensated multi-quantum-well light-emitting active layer with a thickness of In0.2Ga0.8As / GaAsP on the surface of the lower confinement layer; Step S1013: Continue to epitaxially grow a p-type Al0.45Ga0.55As upper confinement layer of a predetermined thickness on the surface of the multi-quantum-well light-emitting active layer. After the growth is completed, passivate the surface by introducing a mixture of AsH3 and PH3 gas into the same cavity. Step S1014: Epitaxially grow a p-type GaAs contact layer of a predetermined thickness on the surface of the upper confinement layer for ohmic contact; Step S1015: The epitaxial wafer is thermally annealed in a nitrogen atmosphere for a preset time to eliminate multi-quantum well interface defects and activate p-type doping to form a stacked structure.

[0033] In some embodiments, step S1011 provides a low-loss, high-carrier-confinement lower confinement layer through in-situ reflectivity monitoring closed-loop control, providing a low-loss optical confinement framework for the unstable cavity. Step S1012 employs 5 pairs of coupled wells with a well width of 8 nm, a barrier width of 10 nm, a growth rate of 0.7 mL / s, and a 2-s interface pause to reduce the interface roughness to <0.2 nm. This yields a light-emitting active region with high differential gain and low threshold current density. Step S1013, based on in-situ cleaning, introduces a 3:1 AsH3 / PH3 mixed gas to passivate the interface state density. This reduces nonradiative recombination and improves internal quantum efficiency. Step S1014 controls the relationship between the hole concentration p and resistivity ρ of GaAs:Zn, providing a low-resistivity ohmic contact layer, reducing series resistance, and improving electro-optical conversion efficiency. Step S1015 employs RTA (Rapid Thermal Annealing) to suppress As precipitation. This activates doping and repairs the quantum well interface.

[0034] Step S102: Remove part of the light confinement layer in the stacked structure by etching process, and define a strip light-emitting region in the lateral direction to obtain the ridge waveguide.

[0035] S102 specifically includes the following steps: Step S1021: Coat the upper surface of the stacked structure with photoresist and use photolithography to form a ridge-shaped photoresist pattern.

[0036] Step S1022: Perform the first dry etching on the photolithographic stacked structure to remove part of the light confinement layer and form a preliminary ridge waveguide structure.

[0037] Step S1023: Deposit a hard mask layer on the surface of the stacked structure after the first etching to improve the etching accuracy and sidewall quality.

[0038] Step S1024: Perform a second etching of the hard mask layer using the ICP dry etching process.

[0039] Step S1025: Perform wet etching on the etched stacked structure to form the ridge waveguide sidewall.

[0040] As can be seen, step S1021 uses photoresist to protect the area to be etched using photolithography, exposing the unprotected areas to subsequent etching processes. The formation of the ridge-shaped photoresist pattern is achieved through photoresist exposure and development. Step S1022 utilizes dry etching technology, selectively removing the areas not protected by photoresist using plasma to form a preliminary ridge waveguide structure. Step S1023 deposits a hard mask material on the surface after the first etching. This material has high etching selectivity and can protect the etched areas from subsequent etching. The hard mask is made of SiO2, SiN, or metal materials and is formed through chemical vapor deposition or physical vapor deposition processes. This improves etching precision and sidewall quality, reduces lateral etching during the etching process, and makes the sidewalls of the ridge waveguide smoother. Step S1024 generates high-density plasma using inductively coupled plasma technology based on ICP dry etching. By controlling the cavity pressure, ICP etching power, RF etching power, and etching time, precise etching of the optical confinement layer can be achieved to form a ridge waveguide structure. Step S1025 uses a wet etching method to slightly etch the etched surface with a chemical solution, removing the micro-roughness generated during the etching process and making the sidewalls of the ridge waveguide smoother. This further reduces the sidewall roughness of the ridge waveguide and improves its optical performance.

[0041] Step S103: Prepare a thin film layer with high refractive index and high absorption coefficient, and cover the sidewall and upper region of the ridge waveguide with the thin film layer extending to a length of 2-6 μm.

[0042] S103 specifically includes the following steps: Step S1031: The surface of the ridge waveguide structure prepared in step S102 is subjected to argon plasma treatment to remove the surface oxide layer and contaminants, thereby enhancing the adhesion of subsequent thin films.

[0043] Step S1032: Using magnetron sputtering, a thin film material with high refractive index and high light absorption coefficient is deposited on the surface of the ridge waveguide to form an initial continuous thin film layer.

[0044] Optionally, the thin film material with high refractive index and high absorption coefficient can be titanium dioxide (TiO2) or tantalum pentoxide (Ta2O5).

[0045] Step S1033: Spin-coat positive photoresist onto the surface of the initial thin film layer, and form a mask pattern on the photoresist layer through pre-baking, ultraviolet exposure, post-baking, and development processes.

[0046] Step S1034: Using reactive ion etching (RIE) with carbon tetrafluoride and oxygen as etching gases, the initial thin film layer is etched into a target shape covering the ridge waveguide sidewall and the 2-6 μm region above it.

[0047] Step S1035: Measure the film thickness and refractive index using an ellipsometer to verify whether it meets the requirements for high refractive index, high absorption coefficient and elongation.

[0048] In step S1031 of this embodiment, active particles in argon plasma can be used to treat the oxide layer and organic contaminants on the ridge waveguide surface, decomposing them into volatile gases, exposing a fresh semiconductor surface, and increasing surface energy. Step S1032 considers magnetron sputtering, which uses a magnetic field to confine argon ions, causing them to bombard the TiO2 target at high speed. The sputtered TiO2 atoms deposit and crystallize on the ridge waveguide surface, forming a continuous oxide film. Step S1033 defines the area where the film needs to be retained using a mask pattern, namely the 2-6 μm extension above the ridge waveguide and the sidewall coverage area. Step S1034 combines RIE to achieve anisotropic etching, removing only the film in the central ridge waveguide region. In step S1035, an ellipsometer measures the phase change of light reflection on the film surface, calculates the thickness and refractive index, and displays the film morphology; a spectrophotometer measures the light transmittance to infer the absorption coefficient. This ensures effective absorption of light leaking from the ridge waveguide sidewalls, enhances optical feedback, and avoids light loss.

[0049] Step S104: Remove part of the light confinement layer in the arc-shaped DBR region to form the basic structure for constructing the Bragg grating.

[0050] S104 of this embodiment specifically includes the following steps: Step S1041: Clean the chip surface where the arc-shaped DBR area needs to be formed to remove surface contaminants.

[0051] Step S1042: Spin-coat photoresist onto the cleaned chip surface and cure the photoresist using a pre-baking process.

[0052] Step S1043: Use a pre-designed arc-shaped DBR region mask to perform ultraviolet lithography to define the arc-shaped DBR region pattern.

[0053] Step S1044: Use inductively coupled plasma etching technology to remove part of the light confinement layer in the arc-shaped DBR region.

[0054] Step S1045: Use oxygen plasma stripping process to remove residual photoresist and complete the fabrication of the arc-shaped DBR base structure.

[0055] In this embodiment, step S1041 removes organic contaminants through organic solvent dissolution and physical ultrasonic oscillation, and activates the surface with oxygen plasma to remove trace residues. This ensures good adhesion between the photoresist and the chip surface. Step S1042: Positive photoresist is spin-coated at 3000 rpm to a thickness of approximately 2 μm. The pre-baking temperature is 100℃-120℃, and the process is continued for a certain period to obtain a uniform, defect-free photoresist layer. Step S1043: Selective exposure using a mask causes a photochemical reaction in the photoresist of the curved DBR region, followed by development to form the desired pattern. Step S1044 utilizes the chemical reaction between active chlorine groups in the plasma and the light confinement layer material, while ion bombardment enhances the anisotropy of the etching. This results in a steep sidewall morphology and controls the etching depth. Step S1045 uses oxygen plasma to decompose the photoresist into volatile products such as carbon dioxide and water vapor.

[0056] S105: An arc-shaped Bragg grating is constructed in the arc-shaped DBR region using electron beam lithography or nanoimprint lithography, so that the grating etching depth completely penetrates the light-emitting active region.

[0057] S105 of this embodiment specifically includes the following steps: Step S1051: Perform surface cleaning and drying on the light confinement layer etched structure prepared in S104 in the arc-shaped DBR region.

[0058] Step S1052: If electron beam lithography is used, electron beam photoresist is coated on the surface of the arc-shaped DBR region and dried; if nanoimprint lithography is used, nanoimprint lithography adhesive is coated on the surface of the arc-shaped DBR region, and then the pre-made arc-shaped grating template is aligned and pressed onto the surface of the imprint lithography adhesive.

[0059] Step S1053: In the electron beam lithography process, the photoresist is scanned and exposed according to the design pattern of the arc-shaped Bragg grating using an electron beam exposure system, and then developed to form a grating pattern mask; in the nanoimprinting process, the imprinted photoresist is thermally cured, and after curing, the template is peeled off to form a grating pattern mask.

[0060] Step S1054: Using a grating pattern mask as protection, the light-emitting active area and the underlying light confinement layer of the arc-shaped DBR region are etched using the inductively coupled plasma etching (ICP-RIE) process to ensure that the etching depth completely penetrates the light-emitting active area.

[0061] Step S1055: Remove the photoresist mask or imprinting mask from the arc-shaped DBR area, and then clean the residual impurities on the surface of the arc-shaped Bragg grating formed by etching.

[0062] It should be noted that in step S1052, the electron beam photoresist is spin-coated to form a uniform thin film, and then dried to remove the solvent to enhance the film stability; the nanoimprint retardant is spin-coated to form a film, and then pressed with a template to replicate the grating pattern of the template. Step S1054, ICP-RIE, combines physical bombardment and chemical etching. Ions in the high-energy plasma bombard the surface of the target region to achieve physical removal, while Cl-based active groups react chemically with the semiconductor material to generate volatile compounds. These two actions work synergistically to achieve etching, ensuring complete penetration through the light-emitting active region and guaranteeing the high aspect ratio of the grating.

[0063] S106: Adjust the curvature of the arc-shaped Bragg grating to match the cavity length to meet the requirements of the unstable cavity. g 1 g 2>1.

[0064] S106 of this embodiment specifically includes the following steps: Step S1061: Retrieve the arc-shaped Bragg grating constructed in step S105, measure the current arc curvature radius R0, and record the curvature deviation of each grating unit.

[0065] Step S1062: Based on the resonant cavity length L of the semiconductor laser and the unstable cavity condition g 1 g 2>1, g 1 represents the resonant cavity geometry factor corresponding to the arc grating, which is related to the radius of curvature R0. g 2 represents the small-signal gain coefficient of the output cavity surface. Calculate the target radius of curvature R that meets the conditions. target .

[0066] Step S1063: If R0 and R target If the deviation exceeds the preset deviation threshold, adjust the process parameters.

[0067] Specifically, if R0 = R target ×1.03, then the deviation is 3%. Electron beam lithography uses an electron beam direct writing system to modify the curvature command of the mask, changing the original mask's radius of curvature from R0 to R. target The curvature of the original template can be modified using focused ion beam (FIB), or a new R-type template can be fabricated. target Curvature of the silicon template.

[0068] The curve parameters of the electron beam mask determine the shape of the photoresist pattern after exposure. Modifying the mask can adjust the curvature of the grating for subsequent etching. By adjusting the template, the curvature can be precisely corrected, thereby improving process efficiency.

[0069] Step S1064: Based on the adjusted template, repeat the pattern writing and etching process of step S105: after exposure and development using a new mask in electron beam lithography, perform ICP etching; after imprinting and curing using a new template in nanoimprint lithography, perform etching to form an arc-shaped Bragg grating with the target curvature.

[0070] Step S1065: Measure the adjusted grating curvature radius again using SEM to verify whether R is achieved. target The condition g1g2>1 was confirmed to be satisfied by simulating the resonant cavity mode using optical simulation software.

[0071] In step S1065 of this embodiment, SEM measurement verifies whether the curvature meets the standard; optical simulation predicts the mode characteristics of the resonant cavity by solving Maxwell's equations, confirming whether the unstable cavity condition is met. Thus, the performance of the adjusted grating is verified from both experimental and simulation perspectives, ensuring the realization of the unstable cavity.

[0072] S107: A low-refractive-index thin film layer of SiOX2 or SiN material is covered on the sidewall of the arc-shaped Bragg grating.

[0073] In some embodiments, S107 specifically includes the following steps: Step S1071: Perform surface pretreatment on the chip structure with the arc-shaped Bragg grating to remove contaminants and the natural oxide layer from the sidewalls of the grating.

[0074] Step S1072: Deposit a low-refractive-index thin film material on the chip surface using a plasma-enhanced chemical vapor deposition (PECVD) device.

[0075] Step S1073: By controlling the deposition parameters, the low refractive index film is uniformly covered to cover the sidewall region of the arc-shaped Bragg grating.

[0076] Step S1074: Perform rapid thermal annealing on the deposited low-refractive-index film to optimize film performance.

[0077] Step S1075: Measure the film thickness and refractive index using an ellipsometer to verify whether the film quality meets the requirements.

[0078] In this embodiment, the S107 pretreatment removes contaminants and the native oxide layer, ensuring a tight bond between the thin film and the grating sidewalls. Steps S1072-S1073, using PECVD equipment and parameter control, precisely deposit low-refractive-index SiO2 or SiN thin films, ensuring uniform coverage of the grating sidewalls. This creates a stable refractive index difference with the grating semiconductor material, enhancing lateral confinement of photons in the grating region and reducing light leakage loss at the grating sidewalls. The rapid thermal annealing process in S1074 improves the film's density. Finally, the ellipsometer inspection in S1075 promptly filters out films with insufficient thickness or refractive index, ensuring that the film quality of each chip meets design requirements. The entire S107 process not only protects the curved Bragg grating with its curvature adjusted in S106 but also enhances the grating's optical function through the optimized low-refractive-index thin film.

[0079] S108: For non-light-emitting cavity surfaces, an arc-shaped Bragg grating is used as a high-reflectivity mirror; for non-light-emitting cavity surfaces, a high-reflectivity anti-reflection film is deposited to reduce residual reflectivity.

[0080] S108 specifically includes the following steps: Step S1081: Perform oxygen plasma cleaning treatment on the light-emitting cavity surface of the semiconductor laser chip.

[0081] Step S1082: Deposit a high-reflection coating material on the light-emitting cavity surface using an electron beam evaporation deposition process.

[0082] Step S1083: By monitoring the deposition process, control the deposition thickness of the high antireflection film within the range of 100-200 nm.

[0083] Step S1084: Under a nitrogen protective atmosphere, perform low-temperature annealing on the deposited film.

[0084] Step S1085: Use an ellipsometer to measure the thickness and refractive index of the high antireflection film on the non-light-emitting cavity surface to verify whether the thickness is within the preset thickness range and whether the refractive index is within the preset refractive index range.

[0085] In this embodiment, S108 uses an ellipsometer to detect the thickness and refractive index, which can promptly screen out products that do not meet the preset requirements, ensuring that the antireflection film performance of each chip is consistent, guaranteeing the stability of batch production of devices, effectively improving the light output efficiency of the laser, reducing intracavity loss, and ensuring the reliability and performance consistency of the device in long-term operation through multi-stage quality control.

[0086] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

[0087] In the description of this invention, it should be noted that the terms upper, lower, inner, outer front end, rear end, both ends, one end, and the other end, etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limiting this invention. In addition, the terms first and second are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0088] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms installation, setting, connection, etc., should be interpreted broadly. For example, connection can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be a connection within two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0089] The above description of the disclosed embodiments enables those skilled in the art to make or use the invention. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the invention. Therefore, the invention is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for fabricating an unstable cavity semiconductor laser chip, characterized in that, The methods include: S101: Provides a light-emitting active region and forms light-confining layers on both sides of the light-emitting active region to form a stacked structure; S102: A portion of the light confinement layer in the stacked structure is removed by etching, and a strip-shaped light-emitting region is defined in the lateral direction to obtain the ridge waveguide; S103: Prepare a thin film layer with high refractive index and high absorption coefficient, and cover the sidewall and upper region of the ridge waveguide with the thin film layer extending to cover a length of 2-6 μm; S104: Remove part of the light confinement layer in the arc-shaped DBR region to form the basic structure for building the Bragg grating; S105: An arc-shaped Bragg grating is constructed in the arc-shaped DBR region using electron beam lithography or nanoimprint lithography, so that the grating etching depth completely penetrates the light-emitting active region. S106: Adjust the curvature of the arc-shaped Bragg grating to match the cavity length to meet the requirements of the unstable cavity. g 1 g 2>1; S107: A low-refractive-index thin film layer of SiOX2 or SiN material is covered on the sidewall of the arc-shaped Bragg grating; S108: For non-light-emitting cavity surfaces, an arc-shaped Bragg grating is used as a high-reflectivity mirror; for non-light-emitting cavity surfaces, a high-reflectivity anti-reflection film is deposited to reduce residual reflectivity.

2. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S101 specifically includes the following steps: An underconfinement layer was grown in a metal-organic chemical vapor deposition reaction chamber using an n-type GaAs substrate. Maintaining the same temperature and pressure, a multi-quantum-well light-emitting active layer is compensated on the surface of the lower confinement layer; A p-type upper confinement layer of a predetermined thickness is epitaxially grown on the surface of the multi-quantum-well light-emitting active layer, and surface passivation is performed in the same cavity after the growth is completed. A p-type GaAs contact layer of a predetermined thickness is epitaxially grown on the surface of the upper confinement layer for ohmic contact; The epitaxial wafer is thermally annealed in a nitrogen atmosphere for a predetermined time to eliminate multi-quantum-well interface defects and activate p-type doping, forming a stacked structure.

3. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S102 specifically includes the following steps: Photoresist is coated on the upper surface of the stacked structure, and a ridge-shaped photoresist pattern is formed using photolithography. The first dry etching is performed on the photolithographically etched stacked structure to remove part of the light confinement layer and form a preliminary ridge waveguide structure. A hard mask layer is deposited on the surface of the stacked structure after the first etching. The hard mask layer was etched a second time using an ICP dry etching process. The etched layered structure is subjected to wet etching to form the ridge waveguide sidewall.

4. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S103 specifically includes the following steps: The surface of the prepared ridge waveguide structure was treated with argon plasma to remove the surface oxide layer and contaminants; A high-refractive-index, high-absorption-coefficient thin film material is deposited on the surface of the ridge waveguide using magnetron sputtering to form an initial continuous thin film layer. Positive photoresist is spin-coated onto the surface of the initial thin film layer, and a mask pattern is formed on the photoresist layer through pre-baking, ultraviolet exposure, post-baking, and development processes. Using reactive ion etching (RIE) with carbon tetrafluoride and oxygen as etching gases, the initial thin film layer is etched into a target shape covering the sidewalls of the ridge waveguide and the 2-6 μm region above it. The film thickness and refractive index were measured using an ellipsometer to verify whether they met the requirements for high refractive index, high absorption coefficient, and elongation.

5. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S104 specifically includes the following steps: The chip surface where the arc-shaped DBR region needs to be formed is cleaned to remove surface contaminants; Photoresist is spin-coated onto the cleaned chip surface and then cured using a pre-baking process. Ultraviolet lithography is performed using a pre-designed arc-shaped DBR region mask to define the arc-shaped DBR region pattern; Inductively coupled plasma etching (ICP-C) was used to remove part of the light confinement layer in the arc-shaped DBR region. Residual photoresist was removed using an oxygen plasma stripping process to complete the fabrication of the arc-shaped DBR base structure.

6. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S105 specifically includes the following steps: The surface of the light confinement layer etched by S104 in the arc-shaped DBR region was cleaned and dried. If electron beam lithography is used, electron beam photoresist is coated on the surface of the arc-shaped DBR region and then dried; If nanoimprinting technology is used, nanoimprinting adhesive is coated on the surface of the arc-shaped DBR area, and then the pre-made arc-shaped grating template is aligned and pressed onto the surface of the imprinting adhesive. In electron beam lithography, the photoresist is scanned and exposed according to the design pattern of the arc-shaped Bragg grating using an electron beam exposure system, and then developed to form a grating pattern mask. In the nanoimprinting process, the imprinting adhesive is thermally cured after pressing, and the template is peeled off after curing to form a grating pattern mask; Using a grating pattern mask as protection, an inductively coupled plasma etching (ICP-RIE) process is employed to etch the light-emitting active region and the underlying light confinement layer of the arc-shaped DBR region, ensuring that the etching depth completely penetrates the light-emitting active region. Remove the photoresist mask or imprinting mask from the arc-shaped DBR area, and then clean the residual impurities on the surface of the arc-shaped Bragg grating formed by etching.

7. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S106 specifically includes the following steps: Retrieve the constructed arc-shaped Bragg grating, measure the current arc curvature radius R0, and record the curvature deviation of each grating unit; Based on the resonant cavity length L of the semiconductor laser and the unstable cavity condition g 1 g 2>1, g 1 represents the resonant cavity geometry factor corresponding to the arc grating, which is related to the radius of curvature R0; g 2 represents the small-signal gain coefficient of the output cavity surface. Calculate the target radius of curvature R that meets the conditions. target ; If R0 and R target If the deviation exceeds the preset deviation threshold, adjust the process parameters. According to the adjusted template, the pattern writing and etching in step S105 are repeated: after exposure and development with a new mask in electron beam lithography, ICP etching is performed; after imprinting and curing with a new template in nanoimprinting, etching is performed to form an arc-shaped Bragg grating with the target curvature. The adjusted grating curvature radius was measured again using SEM to verify whether R was achieved. target The condition g1g2>1 was confirmed to be satisfied by simulating the resonant cavity mode using optical simulation software.

8. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S107 specifically includes the following steps: The chip structure with an arc-shaped Bragg grating is subjected to surface pretreatment to remove contaminants and native oxide layers from the sidewalls of the grating; Low-refractive-index thin film materials are deposited on the chip surface using plasma-enhanced chemical vapor deposition equipment; By controlling the deposition parameters, a low-refractive-index thin film can be uniformly covered on the sidewall region of the arc-shaped Bragg grating. Rapid thermal annealing of deposited low-refractive-index films was performed to optimize film performance. The thickness and refractive index of the thin film were measured using an ellipsometer to verify whether the film quality met the requirements.

9. The method for fabricating an unstable cavity semiconductor laser chip according to claim 1, characterized in that, S108 specifically includes the following steps: The light-emitting cavity surface of the semiconductor laser chip is cleaned with oxygen plasma. A high-reflectance film material is deposited on the light-emitting cavity surface using an electron beam evaporation deposition process; By monitoring the deposition process, the deposition thickness of the high antireflection film can be controlled within the range of 100-200 nm. The deposited film was subjected to low-temperature annealing in a nitrogen protective atmosphere; An ellipsometer was used to measure the thickness and refractive index of the high antireflection film on the non-light-emitting cavity surface to verify whether the thickness and refractive index were within the preset range.

10. A semiconductor device, characterized in that, The semiconductor device is fabricated based on the steps of the fabrication method of the unstable cavity semiconductor laser chip according to any one of claims 1 to 9.

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