A high-precision anti-interference wireless charging current demodulation circuit and method

Abstract

This invention relates to a high-precision anti-interference wireless charging current demodulation circuit and method. The invention includes a CS sampling circuit, comprising a sampling resistor, a first amplification unit, and a second amplification unit; an RC low-pass filter circuit, the input of which is connected to the output of the CS sampling circuit, the RC low-pass filter circuit including a DC blocking capacitor, a DC bias module, and a first filter branch and a second filter branch connected in parallel; a comparator integrator circuit, comprising a comparator circuit and an integrator circuit, the comparator circuit being connected to the outputs of the first and second filter branches respectively, and receiving a threshold voltage providing the inversion point; and an anti-spiking filter circuit, the input of which is connected to the output of the integrator circuit, comprising a coupled first RC delay circuit, a first inverting circuit, a second RC delay circuit, a second inverting circuit, and an SR latch. This invention enables the output current decoding waveform to have the advantage of being resistant to power supply disturbances, avoiding the possibility of false inversions during current decoding.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, and in particular to a high-precision anti-interference wireless charging current demodulation circuit and method. Background Technology

[0002] Wireless charging systems, as a new type of power transmission method, are gradually gaining popularity in consumer and automotive applications due to their simplicity, convenience, and efficiency. The principle is mainly based on the magnetic induction of an inductor coil. The transmitting end converts DC power into AC current, while the receiving end converts the received AC power back into DC power, thus achieving power transmission.

[0003] During wireless charging, under a fixed voltage, the transmitted power primarily depends on the operating frequency's position relative to the coil's resonant point. Under the Qi protocol, the coil's operating frequency is typically around 100kHz to 200kHz. Once the transmitting and receiving chips successfully communicate and power transmission begins, the receiver sends a 2kHz modulation frequency. This 2kHz modulation signal manifests as AC signal fluctuations in the bus current. The transmitting end needs to convert these AC fluctuations on the power bus into a 2kHz voltage signal for output, completing power communication with the receiver. This process is called current decoding.

[0004] Traditional demodulation methods involve sampling the bus current, converting it to voltage, amplifying it by a certain factor, passing it through a low-pass filter composed of capacitors and resistors, and then decoding it using a traditional hysteresis comparator. This method works correctly when the current signal is of high quality (high power and stable current). However, if the input signal power is low, or if there is varying degrees of interference on the power supply during system application, decoding errors are likely to occur, leading to power transmission interruptions. Summary of the Invention

[0005] Therefore, the present invention provides a high-precision anti-interference wireless charging current demodulation circuit, which makes the output current decoding waveform have the advantage of resisting power supply disturbances and avoids the situation where the current decoding is prone to false flipping.

[0006] To address the aforementioned technical problems, this invention provides a high-precision anti-interference wireless charging current demodulation circuit, comprising: The CS sampling circuit includes a sampling resistor, a first amplification unit, and a second amplification unit. The sampling resistor converts the bus current into a voltage signal, which is then amplified by a fixed factor by the first amplification unit and then amplified again by a fixed factor by the second amplification unit to obtain a sampled voltage signal. An RC low-pass filter circuit is provided, with its input terminal connected to the output terminal of the CS sampling circuit. The RC low-pass filter circuit includes a DC blocking capacitor, a DC bias module, and a first filter branch and a second filter branch connected in parallel. The DC bias module provides a DC operating point for the DC-blocked AC signal. The DC blocking capacitor filters out the DC component from the sampled voltage signal, retaining only the AC component. The first filter branch retains the AC component below a preset first cutoff frequency to obtain a first filtered signal. The second filter branch retains the AC component below a preset second cutoff frequency to obtain a second filtered signal. The first cutoff frequency is greater than the second cutoff frequency, resulting in an amplitude difference between the first filtered signal and the second filtered signal. The comparator integrator circuit includes a comparator circuit and an integrator circuit. The comparator circuit is connected to the output terminals of the first filter branch and the second filter branch, respectively, and receives a threshold voltage that provides the inversion point. The comparator circuit is used to compare the first filter signal and the second filter signal to obtain a comparison output signal. The input terminal of the integrator circuit is connected to the output terminal of the comparator circuit and is used to integrate the comparison output signal to obtain an integrated output signal. The anti-spiking filter circuit, whose input is connected to the output of the integrator circuit, includes a first RC delay circuit, a first inverting circuit, a second RC delay circuit, a second inverting circuit, and an SR latch coupled together. The anti-spiking filter circuit is used to RC delay the rising and falling edges of the integrated output signal, respectively, and then latch it through the SR to recover the decoded signal.

[0007] In one embodiment of the present invention, the first amplification unit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3; The two ends of the sampling resistor Rsense are connected to the first bus current sampling terminal CSP and the first bus current sampling terminal CSN, respectively. One end of the sampling resistor Rsense is connected to the emitter of the first transistor Q1 through the first resistor R1; The other end of the sampling resistor Rsense is connected to the emitter of the second transistor Q2 through the second resistor R2; The bases of the first transistor Q1 and the second transistor Q2 are respectively connected to the base voltage vb; The collectors of the first transistor Q1 and the second transistor Q2 are connected together and then grounded; The second resistor R2 is grounded between the emitter of the second transistor Q2; The second amplification unit includes an operational amplifier AMP, a fourth resistor R4, and a fifth resistor R5; One end of the third resistor R3 is connected between the first resistor R1 and the emitter of the first transistor Q1, and the other end of the third resistor R3 is grounded. The positive input terminal of the operational amplifier AMP is connected between the first resistor R1 and the third resistor R3; The output of the operational amplifier AMP is connected to one end of the fifth resistor R5 through the fourth resistor R4, and the other end of the fifth resistor R5 is grounded. The negative input terminal of the operational amplifier AMP is connected between the fourth resistor R4 and the fifth resistor R5.

[0008] In one embodiment of the present invention, the first filter branch includes a sixth resistor R6 and a first capacitor C1; The second filter branch includes a seventh resistor R7 and a second capacitor C2; The RC low-pass filter circuit also includes an eighth resistor R8; The output of the operational amplifier AMP is connected to one end of the sixth resistor R6 through the DC blocking capacitor C0, and the other end of the sixth resistor R6 is grounded through the first capacitor C1. The output of the DC bias module is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded through the second capacitor C2. One end of the eighth resistor R8 is connected between the DC blocking capacitor C0 and the sixth resistor R6; The other end of the eighth resistor R8 is connected to the output terminal of the DC bias module; The first filtered signal is output between the sixth resistor R6 and the first capacitor C1; The second filtered signal is output between the seventh resistor R7 and the second capacitor C2.

[0009] In one embodiment of the present invention, the first filtering branch retains only signals below 10kHz; the second filtering branch retains only signals below 2kHz.

[0010] In one embodiment of the present invention, the comparator circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, and a second NMOS transistor NM2; The integrating circuit includes a third NMOS transistor NM3, a fifth PMOS transistor PM5, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, and a first inverter inv1. The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are each connected to the power supply voltage VDD. The drain of the third PMOS transistor PM3 is connected to the source of the first PMOS transistor PM1; The gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4. The drain of the fourth PMOS transistor PM4 is connected to the source of the second PMOS transistor PM2; The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2; The gate connection bias voltage vbp of the first PMOS transistor PM1; The drain of the first PMOS transistor PM1 is connected to the gate of the third PMOS transistor PM3 and the drain of the first NMOS transistor NM1, respectively. The drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2; The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected together and then grounded; The first filtered signal is connected to the gate of the first NMOS transistor NM1; The second filtered signal is connected to the gate of the second NMOS transistor NM2; The gate of the fifth PMOS transistor PM5, one end of the ninth resistor R9, one end of the third capacitor C3, and the gate of the third NMOS transistor NM3 are respectively connected between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2. The drain of the fifth PMOS transistor PM5, the other end of the ninth resistor R9, the other end of the third capacitor C3, and the drain of the third NMOS transistor NM3 are respectively connected to the input terminal of the first inverter inv1. The output terminal of the first inverter inv1 outputs an integral output signal; The source of the third NMOS transistor NM3 is grounded through the tenth resistor R10.

[0011] In one embodiment of the present invention, the first RC delay circuit includes a sixth PMOS transistor PM6, a fourth NMOS transistor NM4, an eleventh resistor R11, a fourth capacitor C4, and a fifth capacitor C5. The second RC delay circuit includes a seventh PMOS transistor PM7, a fifth NMOS transistor NM5, a twelfth resistor R12, a sixth capacitor C6, and a seventh capacitor C7; The first inverter circuit includes a second inverter inv2, and the second inverter circuit includes a third inverter inv3; The output of the integrator circuit is connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the input of the second inverter inv2. The drain of the sixth PMOS transistor PM6 is connected to the drain of the fourth NMOS transistor NM4 and the other end of the eleventh resistor R11. The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD, and the source of the fourth NMOS transistor NM4 is grounded. The gate of the sixth PMOS transistor PM6 is connected to the first upper branch node voltage VP1; The gate of the fourth NMOS transistor NM4 is connected to the first lower branch node voltage VN1; One end of the fourth capacitor C4 and one end of the fifth capacitor C5 are respectively connected to the input terminal of the second inverter inv2; The other end of the fourth capacitor C4 is connected to the power supply voltage VDD, and the other end of the fifth capacitor C5 is grounded. One end of the twelfth resistor R12 is connected to the output terminal of the second inverter inv2; The other end of the twelfth resistor R12 is connected to the input terminal of the third inverter inv3; The drain of the seventh PMOS transistor PM7 is connected to the drain of the fifth NMOS transistor NM5 and the other end of the twelfth resistor R12, respectively. The source of the seventh PMOS transistor PM7 is connected to the power supply voltage VDD, and the source of the fifth NMOS transistor NM5 is grounded. The gate of the seventh PMOS transistor PM7 is connected to the second upper branch node voltage VP2; The gate of the fifth NMOS transistor NM5 is connected to the second lower branch node voltage VN2; One end of the sixth capacitor C6 and one end of the seventh capacitor C7 are respectively connected to the input terminal of the third inverter inv3; The other end of the sixth capacitor C6 is connected to the power supply voltage VDD, and the other end of the seventh capacitor C7 is grounded.

[0012] In one embodiment of the present invention, the anti-spiking filter circuit further includes a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, an AND gate nand, and an OR gate nor; The output of the integrator circuit is connected to the input of the fourth inverter inv4; The output of the fourth inverter inv4 is connected to the first input of the AND gate nand and the first input of the OR gate nor. The output of the third inverter inv3 is connected to the second input of the AND gate nand and the second input of the OR gate nor; The output of the AND gate NAND is connected to the input of the fifth inverter inv5 and the first input of the SR latch, respectively. The output of the OR gate NOR is connected to the input of the sixth inverter, INV6. The output of the sixth inverter inv6 is connected to the second input of the SR latch.

[0013] This invention also provides a high-precision anti-interference wireless charging current demodulation method, based on the aforementioned high-precision anti-interference wireless charging current demodulation circuit, the demodulation method comprising: The S1 and CS sampling circuits sample the bus current, convert the sampled current into a voltage signal through a sampling resistor, amplify the voltage signal by a fixed factor through the first amplification unit, and then amplify the voltage signal again by a fixed factor through the second amplification unit to obtain the sampled voltage signal. S2. The sampled voltage signal is input into an RC low-pass filter circuit. The DC component is filtered out by a DC blocking capacitor, leaving only the AC component. A DC bias module provides a DC operating point for the DC-blocked AC component. Simultaneously, the AC component is filtered by a first filter branch and a second filter branch connected in parallel. The first filter branch retains the AC component below a preset first cutoff frequency to obtain a first filtered signal, and the second filter branch retains the AC component below a preset second cutoff frequency to obtain a second filtered signal. The first cutoff frequency is greater than the second cutoff frequency, so that the first filtered signal and the second filtered signal have an amplitude difference in the target frequency band. S3. Input the first filtered signal and the second filtered signal into the comparison circuit, and set the comparison inversion point with the threshold voltage to compare the first filtered signal and the second filtered signal to obtain the comparison output signal; S4. Input the comparison output signal into the integration circuit, perform integration processing on the comparison output signal, so that the integrated output signal increases or decreases in a ramp-like manner when the comparison output flips, thereby suppressing transient jumps caused by power supply disturbances and input signal glitches, and obtaining the integrated output signal. S5. Input the integral output signal into the anti-spiking filter circuit, perform RC delay processing on the rising and falling edges of the integral output signal respectively, and latch the delayed rising and falling edges through the SR latch to recover and output a stable current decoding signal.

[0014] The technical solution of the present invention has the following advantages compared with the prior art: This invention discloses a high-precision anti-interference wireless charging current demodulation circuit and method. By sampling the change in load current and converting it into an internal sampling voltage, the amplified voltage signal can be used as a current sampling signal input to an MCU for processing, and also as the input to an integral comparator for current decoding. The current decoding waveform output by the integral comparator has strong anti-power supply disturbance capability, remaining stable even when the system operating environment has voltage fluctuations or noise interference. This significantly reduces the probability of false flips during current decoding and improves decoding reliability. This circuit can be applied to wireless charging transmitter control chips and has a wider range of applications. Attached Figure Description

[0015] To make the content of this invention easier to understand, the invention will be further described in detail below with reference to specific embodiments and accompanying drawings.

[0016] Figure 1 This is a schematic diagram of the high-precision anti-interference wireless charging current demodulation circuit of the present invention.

[0017] Figure 2 This is a schematic diagram of the CS sampling principle of the present invention.

[0018] Figure 3 This is a schematic diagram of the comparison circuit and the integrator circuit of this invention.

[0019] Figure 4 This is the schematic diagram of the anti-spiking filter circuit of the present invention.

[0020] Figure 5 These are waveform diagrams of each node in the system of this invention. Detailed Implementation

[0021] The present invention will be further described below with reference to the accompanying drawings and specific embodiments, so that those skilled in the art can better understand and implement the present invention. However, the embodiments described are not intended to limit the present invention.

[0022] In this invention, when directions (up, down, left, right, front, and back) are described, it is only for the convenience of describing the technical solution of this invention, and does not indicate or imply that the technical features referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this invention.

[0023] In this invention, "several" means one or more, "multiple" means two or more, "greater than," "less than," "exceeding," etc., are understood to exclude the stated number; "above," "below," "within," etc., are understood to include the stated number. In the description of this invention, the terms "first" and "second" are used only to distinguish technical features and should not be construed as indicating or implying relative importance, or implicitly indicating the number of indicated technical features, or implicitly indicating the order of the indicated technical features.

[0024] In this invention, unless otherwise explicitly defined, the terms "setting," "installing," and "connecting" should be interpreted broadly. For example, they can refer to a direct connection or an indirect connection through an intermediate medium; a fixed connection, a detachable connection, or an integrally formed connection; a mechanical connection, an electrical connection, or a connection capable of mutual communication; or the internal connection of two components or the interaction between two components. Those skilled in the art can reasonably determine the specific meaning of the above terms in this invention based on the specific content of the technical solution.

[0025] Reference Figure 1 As shown, a high-precision anti-interference wireless charging current demodulation circuit of the present invention includes: The CS (Current Sense) sampling circuit includes a sampling resistor, a first amplification unit, and a second amplification unit. The sampling resistor converts the bus current into a voltage signal. After being amplified by a fixed factor by the first amplification unit, the signal is amplified again by a fixed factor by the second amplification unit to obtain the sampling voltage signal V_CS. By amplifying the signal again, it has stronger driving capability and signal stability.

[0026] An RC low-pass filter circuit is provided, with its input terminal connected to the output terminal of the CS sampling circuit. The RC low-pass filter circuit includes a DC blocking capacitor, a DC bias module, and a first filter branch and a second filter branch connected in parallel. The DC bias module provides a DC operating point for the DC-blocked AC signal. The DC blocking capacitor filters out the DC component from the sampled voltage signal, retaining only the AC component. The first filter branch retains the AC component below a preset first cutoff frequency to obtain a first filtered signal. The second filter branch retains the AC component below a preset second cutoff frequency to obtain a second filtered signal. The first cutoff frequency is greater than the second cutoff frequency, resulting in an amplitude difference between the first filtered signal and the second filtered signal. The comparator integrator circuit includes a comparator circuit and an integrator circuit. The comparator circuit is connected to the output terminals of the first filter branch and the second filter branch, respectively, and receives a threshold voltage vth that provides the inversion point. The comparator circuit is used to compare the first filter signal and the second filter signal to obtain a comparison output signal. The input terminal of the integrator circuit is connected to the output terminal of the comparator circuit and is used to integrate the comparison output signal to obtain an integrated output signal. The anti-spiking filter circuit, whose input is connected to the output of the integrator circuit, includes a first RC delay circuit, a first inverting circuit, a second RC delay circuit, a second inverting circuit, and an SR latch coupled together. The anti-spiking filter circuit is used to RC delay the rising and falling edges of the integrated output signal, respectively, and then latch it through the SR to recover the decoded signal.

[0027] With the above setup, the circuit samples the bus current and amplifies the sampled signal into a voltage signal. After extracting the AC component of the voltage signal through a DC blocking capacitor, a low-pass RC filter circuit (low-pass filter) filters out high-frequency noise. A comparator circuit and an integrator circuit then demodulate the voltage signal. Finally, an anti-spiking filter circuit delays the demodulated signal before outputting it. This scheme effectively improves the anti-interference capability of the current demodulation process and avoids erroneous switching caused by power supply disturbances.

[0028] An RC low-pass filter circuit filters the input signal, retaining the 2kHz frequency band signal and filtering out the 2kHz frequency band signal.

[0029] The comparator and integrator circuits compare and integrate the two RC-filtered signals. The integrator circuit accumulates the output of the comparator circuit, causing the output voltage to change in a ramp-like manner. This effectively suppresses false flips caused by transient interference during the gradual rise or fall of the voltage, thus improving the stability of the decoding process.

[0030] The anti-spiking filter circuit applies rising and falling delays to the integrated decoding result. The matched RC delay circuit ensures that the effective frequency of the output signal remains in the range of approximately 2 kHz, while suppressing brief spikes or glitches, further reducing the risk of misinterpretation.

[0031] In one embodiment, refer to Figure 2 As shown, the first amplification unit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3; The two ends of the sampling resistor Rsense are connected to the first bus current sampling terminal CSP and the first bus current sampling terminal CSN, respectively. One end of the sampling resistor Rsense is connected to the emitter of the first transistor Q1 through the first resistor R1; The other end of the sampling resistor Rsense is connected to the emitter of the second transistor Q2 through the second resistor R2; The bases of the first transistor Q1 and the second transistor Q2 are respectively connected to the base voltage vb; The collectors of the first transistor Q1 and the second transistor Q2 are connected together and then grounded; The second resistor R2 is grounded between the emitter of the second transistor Q2; The second amplification unit includes an operational amplifier AMP, a fourth resistor R4, and a fifth resistor R5; One end of the third resistor R3 is connected between the first resistor R1 and the emitter of the first transistor Q1, and the other end of the third resistor R3 is grounded. The positive input terminal of the operational amplifier AMP is connected between the first resistor R1 and the third resistor R3; The output of the operational amplifier AMP is connected to one end of the fifth resistor R5 through the fourth resistor R4, and the other end of the fifth resistor R5 is grounded. The negative input terminal of the operational amplifier AMP is connected between the fourth resistor R4 and the fifth resistor R5.

[0032] It should be noted that the resistance of the sampling resistor Rsense is Rsense, the resistance of the first resistor R1 and the second resistor R2 is both R0, the resistance of the third resistor R3 is K0×R0, the resistance of the fifth resistor R5 is R2, the resistance of the fourth resistor R4 is K1×R2, and the sampling current is Isense.

[0033] The CS sampling circuit first converts the sampled current into a voltage Isense×Rsense and amplifies it by a fixed factor K0. At the same time, it provides a DC bias so that when Isense=0, the output bias voltage is I1×K0×R0. The actual sampling voltage Vsense = K0×Isense×Rsense + I1×K0×R0. The amplified sampling voltage is then further amplified by K1 times by a closed-loop operational amplifier with a fixed factor to ensure that the signal output by the CS sampling circuit has sufficient driving capability and signal strength to meet the demodulation requirements of the subsequent circuits.

[0034] In one embodiment, refer to Figure 1 As shown, the first filter branch includes a sixth resistor R6 and a first capacitor C1; The second filter branch includes a seventh resistor R7 and a second capacitor C2; The RC low-pass filter circuit also includes an eighth resistor R8; The output of the operational amplifier AMP is connected to one end of the sixth resistor R6 through the DC blocking capacitor C0, and the other end of the sixth resistor R6 is grounded through the first capacitor C1. The output of the DC bias module (DC module) is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded through the second capacitor C2; the DC module provides the DC operating voltage, and the Vth module provides the threshold voltage for the comparison circuit to switch. One end of the eighth resistor R8 is connected between the DC blocking capacitor C0 and the sixth resistor R6; The other end of the eighth resistor R8 is connected to the output terminal of the DC bias module; The first filtered signal is output between the sixth resistor R6 and the first capacitor C1; The second filtered signal is output between the seventh resistor R7 and the second capacitor C2.

[0035] In one embodiment, the first filtering branch retains only signals below 10kHz; the second filtering branch retains only signals below 2kHz.

[0036] It should be noted that the RC low-pass filter circuit uses a DC blocking capacitor C0 and two low-pass filter branches with different cutoff frequencies. The DC blocking capacitor C0 filters out the DC component in the amplified signal, retaining only the AC component, and provides the DC operating point for the DC-blocked signal through a DC bias module (DC module). The two low-pass filter branches are used to filter out high-frequency components above 10kHz and 2kHz, respectively, resulting in an amplitude difference between the two signals in the 2kHz frequency band. The threshold voltage vth is used to determine the threshold value of this amplitude difference.

[0037] The comparator circuit compares two filtered signals. Since the two signals have different frequency bands and amplitudes, a threshold voltage (vth) is used to set the flip-off point of the comparator circuit. When the current is low, the comparator circuit output stabilizes at a fixed voltage, keeping the integrator circuit at a low output level. When the current increases and reaches the flip-off condition of the comparator circuit, due to the integration characteristics of the integrator circuit, the output voltage does not jump instantaneously, but gradually increases to the flip-off level. This method effectively suppresses transient jumps caused by power supply disturbances or short-term input voltage glitches, preventing the comparator circuit from erroneously flipping.

[0038] In one embodiment, refer to Figure 3 As shown, the comparator circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, and a second NMOS transistor NM2; The integrating circuit includes a third NMOS transistor NM3, a fifth PMOS transistor PM5, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, and a first inverter inv1. The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are each connected to the power supply voltage VDD. The drain of the third PMOS transistor PM3 is connected to the source of the first PMOS transistor PM1; The gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4. The drain of the fourth PMOS transistor PM4 is connected to the source of the second PMOS transistor PM2; The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2; The gate connection bias voltage vbp of the first PMOS transistor PM1; The drain of the first PMOS transistor PM1 is connected to the gate of the third PMOS transistor PM3 and the drain of the first NMOS transistor NM1, respectively. The drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2; The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected together and then grounded; The first filtered signal is connected to the gate of the first NMOS transistor NM1; The second filtered signal is connected to the gate of the second NMOS transistor NM2; The gate of the fifth PMOS transistor PM5, one end of the ninth resistor R9, one end of the third capacitor C3, and the gate of the third NMOS transistor NM3 are respectively connected between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2. The drain of the fifth PMOS transistor PM5, the other end of the ninth resistor R9, the other end of the third capacitor C3, and the drain of the third NMOS transistor NM3 are respectively connected to the input terminal of the first inverter inv1. The output terminal of the first inverter inv1 outputs an integral output signal; The source of the third NMOS transistor NM3 is grounded through the tenth resistor R10.

[0039] It should be noted that the comparator circuit compares the two signals after RC filtering. Unlike traditional comparators, this invention connects an integrator circuit in series at the output of the comparator circuit. When the current is stable, the comparator circuit output remains at the set DC point, keeping the integrator circuit at a low level. When the current fluctuates, due to the effect of the capacitor (third capacitor C3) in the integrator circuit, the rising and falling edges of the comparator circuit output slowly rise or fall, gradually reaching the integrator circuit's switching threshold. This method can effectively suppress erroneous switching of the comparator circuit caused by power supply disturbances or low input signal amplitude.

[0040] In one embodiment, the first RC delay circuit includes a sixth PMOS transistor PM6, a fourth NMOS transistor NM4, an eleventh resistor R11, a fourth capacitor C4, and a fifth capacitor C5. The second RC delay circuit includes a seventh PMOS transistor PM7, a fifth NMOS transistor NM5, a twelfth resistor R12, a sixth capacitor C6, and a seventh capacitor C7; The first inverter circuit includes a second inverter inv2, and the second inverter circuit includes a third inverter inv3; The output of the integrator circuit is connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the input of the second inverter inv2. The drain of the sixth PMOS transistor PM6 is connected to the drain of the fourth NMOS transistor NM4 and the other end of the eleventh resistor R11. The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD, and the source of the fourth NMOS transistor NM4 is grounded. The gate of the sixth PMOS transistor PM6 is connected to the first upper branch node voltage VP1; The gate of the fourth NMOS transistor NM4 is connected to the first lower branch node voltage VN1; One end of the fourth capacitor C4 and one end of the fifth capacitor C5 are respectively connected to the input terminal of the second inverter inv2; The other end of the fourth capacitor C4 is connected to the power supply voltage VDD, and the other end of the fifth capacitor C5 is grounded. One end of the twelfth resistor R12 is connected to the output terminal of the second inverter inv2; The other end of the twelfth resistor R12 is connected to the input terminal of the third inverter inv3; The drain of the seventh PMOS transistor PM7 is connected to the drain of the fifth NMOS transistor NM5 and the other end of the twelfth resistor R12, respectively. The source of the seventh PMOS transistor PM7 is connected to the power supply voltage VDD, and the source of the fifth NMOS transistor NM5 is grounded. The gate of the seventh PMOS transistor PM7 is connected to the second upper branch node voltage VP2; The gate of the fifth NMOS transistor NM5 is connected to the second lower branch node voltage VN2; One end of the sixth capacitor C6 and one end of the seventh capacitor C7 are respectively connected to the input terminal of the third inverter inv3; The other end of the sixth capacitor C6 is connected to the power supply voltage VDD, and the other end of the seventh capacitor C7 is grounded.

[0041] In one embodiment, the anti-spiking filter circuit further includes a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, an AND gate nand, and an OR gate nor; The output of the integrator circuit is connected to the input of the fourth inverter inv4; The output of the fourth inverter inv4 is connected to the first input of the AND gate nand and the first input of the OR gate nor. The output of the third inverter inv3 is connected to the second input of the AND gate nand and the second input of the OR gate nor; The output of the AND gate NAND is connected to the input of the fifth inverter inv5 and the first input of the SR latch, respectively. The output of the OR gate NOR is connected to the input of the sixth inverter, INV6. The output of the sixth inverter inv6 is connected to the second input of the SR latch.

[0042] The anti-spiking filter circuit provides matched rise and fall delays for the signal output from the integrator circuit, further shielding against brief interference flips. Its working mechanism is as follows: four switches control two inverters, causing the NMOS and PMOS transistors of the two inverters to conduct cross-conduct. The delay effect of resistors and capacitors generates matched edge delays, thereby improving the stability of the current demodulated signal and further reducing the possibility of false flips.

[0043] Specifically, when the integral output signal INTE_OUT is high, the voltages of the first upper branch node VP1 and the first lower branch node VN1 are low, while the voltages of the second lower branch node VN2 and the second upper branch node VP2 are high. When the rising edge of the integral output signal INTE_OUT arrives, the voltages of the first upper branch node VP1 and the second upper branch node VP2 go high, while the voltages of the first lower branch node VN1 and the second lower branch node VN2 go low, and a fixed-time delay is achieved through RC.

[0044] When the integral output signal INTE_OUT is low, the voltages of the first upper branch node VP1 and the first lower branch node VN1 are high, while the voltages of the second lower branch node VN2 and the second upper branch node VP2 are low. When the falling edge of the integral output signal INTE_OUT arrives, the voltages of the first upper branch node VP1 and the second upper branch node VP2 also go high, while the voltages of the first lower branch node VN1 and the second lower branch node VN2 go low, and are then delayed for a fixed time using an RC delay. Subsequently, the SR latch latches the rising and falling edges processed by the RC delay, thereby recovering and outputting a stable decoded signal.

[0045] The overall work process is as follows: The S1 and CS sampling circuits sample the bus current, convert the sampled current into a voltage signal through a sampling resistor, amplify the voltage signal by a fixed factor through the first amplification unit, and then amplify the voltage signal again by a fixed factor through the second amplification unit to obtain the sampled voltage signal. S2. The sampled voltage signal is input into an RC low-pass filter circuit. The DC component is filtered out by a DC blocking capacitor, leaving only the AC component. A DC bias module provides a DC operating point for the DC-blocked AC component. Simultaneously, the AC component is filtered by a first filter branch and a second filter branch connected in parallel. The first filter branch retains the AC component below a preset first cutoff frequency to obtain a first filtered signal, and the second filter branch retains the AC component below a preset second cutoff frequency to obtain a second filtered signal. The first cutoff frequency is greater than the second cutoff frequency, so that the first filtered signal and the second filtered signal have an amplitude difference in the target frequency band. S3. Input the first filtered signal and the second filtered signal into the comparison circuit, and set the comparison inversion point with the threshold voltage to compare the first filtered signal and the second filtered signal to obtain the comparison output signal; S4. Input the comparison output signal into the integration circuit, perform integration processing on the comparison output signal, so that the integrated output signal increases or decreases in a ramp-like manner when the comparison output flips, thereby suppressing transient jumps caused by power supply disturbances and input signal glitches, and obtaining the integrated output signal. S5. Input the integral output signal into the anti-spiking filter circuit, perform RC delay processing on the rising and falling edges of the integral output signal respectively, and latch the delayed rising and falling edges through the SR latch to recover and output a stable current decoding signal.

[0046] Figure 1 The waveforms of each node are as follows Figure 5 As shown: I_VIN is the bus current signal, containing both DC and AC components; V_CS is the sampled and amplified voltage signal; COMP_IN is the waveform of V_CS after RC filtering, and is compared with the DC level DC_vth; COMP_OUT is the output voltage of the comparator circuit, and its rise and fall exhibit a ramp-like change due to the effect of the subsequent integrator circuit; INTE_OUT is the integrated voltage waveform; IDM_OUT is the output waveform after processing by the anti-spiking filter circuit, including matching delays for the rising and falling edges of INTE_OUT, thereby obtaining a stable decoding output.

[0047] Those skilled in the art will understand that embodiments of the present invention can be provided as methods, systems, or computer program products. Therefore, the present invention can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention can take the form of a computer program product embodied on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0048] This invention is described with reference to flowchart illustrations and / or block diagrams of methods, apparatus (systems), and computer program products according to embodiments of the invention. It will be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, generate instructions for implementing the flowchart illustrations and / or block diagrams. Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.

[0049] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing device to function in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.

[0050] These computer program instructions may also be loaded onto a computer or other programmable data processing equipment to cause a series of operational steps to be performed on the computer or other programmable equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.

[0051] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to examples, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A high-precision anti-interference wireless charging current demodulation circuit, characterized in that, include: The CS sampling circuit includes a sampling resistor, a first amplification unit, and a second amplification unit. The sampling resistor converts the bus current into a voltage signal, which is then amplified by a fixed factor by the first amplification unit and then amplified again by a fixed factor by the second amplification unit to obtain a sampled voltage signal. An RC low-pass filter circuit is provided, with its input terminal connected to the output terminal of the CS sampling circuit. The RC low-pass filter circuit includes a DC blocking capacitor, a DC bias module, and a first filter branch and a second filter branch connected in parallel. The DC bias module provides a DC operating point for the DC-blocked AC signal. The DC blocking capacitor filters out the DC component from the sampled voltage signal, retaining only the AC component. The first filter branch retains the AC component below a preset first cutoff frequency to obtain a first filtered signal. The second filter branch retains the AC component below a preset second cutoff frequency to obtain a second filtered signal. The first cutoff frequency is greater than the second cutoff frequency, resulting in an amplitude difference between the first filtered signal and the second filtered signal. The comparator integrator circuit includes a comparator circuit and an integrator circuit. The comparator circuit is connected to the output terminals of the first filter branch and the second filter branch, respectively, and receives a threshold voltage that provides the inversion point. The comparator circuit is used to compare the first filter signal and the second filter signal to obtain a comparison output signal. The input terminal of the integrator circuit is connected to the output terminal of the comparator circuit and is used to integrate the comparison output signal to obtain an integrated output signal. The anti-spiking filter circuit, whose input terminal is connected to the output terminal of the integrator circuit, includes a first RC delay circuit, a first inverting circuit, a second RC delay circuit, a second inverting circuit, and an SR latch coupled together. The anti-spiking filter circuit is used to RC delay the rising edge and falling edge of the integrated output signal respectively, latch it through the SR latch, and recover it into a decoded signal.

2. The high-precision anti-interference wireless charging current demodulation circuit according to claim 1, characterized in that, The first amplification unit includes a first transistor Q1, a second transistor Q2, a first resistor R1, a second resistor R2, and a third resistor R3; The two ends of the sampling resistor Rsense are connected to the first bus current sampling terminal CSP and the first bus current sampling terminal CSN, respectively. One end of the sampling resistor Rsense is connected to the emitter of the first transistor Q1 through the first resistor R1; The other end of the sampling resistor Rsense is connected to the emitter of the second transistor Q2 through the second resistor R2; The bases of the first transistor Q1 and the second transistor Q2 are respectively connected to the base voltage vb; The collectors of the first transistor Q1 and the second transistor Q2 are connected together and then grounded; The second resistor R2 is grounded between the emitter of the second transistor Q2; The second amplification unit includes an operational amplifier AMP, a fourth resistor R4, and a fifth resistor R5; One end of the third resistor R3 is connected between the first resistor R1 and the emitter of the first transistor Q1, and the other end of the third resistor R3 is grounded. The positive input terminal of the operational amplifier AMP is connected between the first resistor R1 and the third resistor R3; The output of the operational amplifier AMP is connected to one end of the fifth resistor R5 through the fourth resistor R4, and the other end of the fifth resistor R5 is grounded. The negative input terminal of the operational amplifier AMP is connected between the fourth resistor R4 and the fifth resistor R5.

3. The high-precision anti-interference wireless charging current demodulation circuit according to claim 2, characterized in that, The first filter branch includes a sixth resistor R6 and a first capacitor C1; The second filter branch includes a seventh resistor R7 and a second capacitor C2; The RC low-pass filter circuit also includes an eighth resistor R8; The output of the operational amplifier AMP is connected to one end of the sixth resistor R6 through the DC blocking capacitor C0, and the other end of the sixth resistor R6 is grounded through the first capacitor C1. The output of the DC bias module is connected to one end of the seventh resistor R7, and the other end of the seventh resistor R7 is grounded through the second capacitor C2. One end of the eighth resistor R8 is connected between the DC blocking capacitor C0 and the sixth resistor R6; The other end of the eighth resistor R8 is connected to the output terminal of the DC bias module; The first filtered signal is output between the sixth resistor R6 and the first capacitor C1; The second filtered signal is output between the seventh resistor R7 and the second capacitor C2.

4. The high-precision anti-interference wireless charging current demodulation circuit according to claim 1, characterized in that, The first filtering branch retains only signals below 10kHz; the second filtering branch retains only signals below 2kHz.

5. The high-precision anti-interference wireless charging current demodulation circuit according to claim 1, characterized in that, The comparator circuit includes a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a fourth PMOS transistor PM4, a first NMOS transistor NM1, and a second NMOS transistor NM2; The integrating circuit includes a third NMOS transistor NM3, a fifth PMOS transistor PM5, a ninth resistor R9, a tenth resistor R10, a third capacitor C3, and a first inverter inv1. The sources of the third PMOS transistor PM3, the fourth PMOS transistor PM4, and the fifth PMOS transistor PM5 are each connected to the power supply voltage VDD. The drain of the third PMOS transistor PM3 is connected to the source of the first PMOS transistor PM1; The gate of the third PMOS transistor PM3 is connected to the gate of the fourth PMOS transistor PM4. The drain of the fourth PMOS transistor PM4 is connected to the source of the second PMOS transistor PM2; The gate of the first PMOS transistor PM1 is connected to the gate of the second PMOS transistor PM2; The gate connection bias voltage vbp of the first PMOS transistor PM1; The drain of the first PMOS transistor PM1 is connected to the gate of the third PMOS transistor PM3 and the drain of the first NMOS transistor NM1, respectively. The drain of the second PMOS transistor PM2 is connected to the drain of the second NMOS transistor NM2; The sources of the first NMOS transistor NM1 and the second NMOS transistor NM2 are connected together and then grounded; The first filtered signal is connected to the gate of the first NMOS transistor NM1; The second filtered signal is connected to the gate of the second NMOS transistor NM2; The gate of the fifth PMOS transistor PM5, one end of the ninth resistor R9, one end of the third capacitor C3, and the gate of the third NMOS transistor NM3 are respectively connected between the drain of the second PMOS transistor PM2 and the drain of the second NMOS transistor NM2. The drain of the fifth PMOS transistor PM5, the other end of the ninth resistor R9, the other end of the third capacitor C3, and the drain of the third NMOS transistor NM3 are respectively connected to the input terminal of the first inverter inv1. The output terminal of the first inverter inv1 outputs an integral output signal; The source of the third NMOS transistor NM3 is grounded through the tenth resistor R10.

6. The high-precision anti-interference wireless charging current demodulation circuit according to claim 1, characterized in that, The first RC delay circuit includes a sixth PMOS transistor PM6, a fourth NMOS transistor NM4, an eleventh resistor R11, a fourth capacitor C4, and a fifth capacitor C5; The second RC delay circuit includes a seventh PMOS transistor PM7, a fifth NMOS transistor NM5, a twelfth resistor R12, a sixth capacitor C6, and a seventh capacitor C7; The first inverter circuit includes a second inverter inv2, and the second inverter circuit includes a third inverter inv3; The output of the integrator circuit is connected to one end of the eleventh resistor R11, and the other end of the eleventh resistor R11 is connected to the input of the second inverter inv2. The drain of the sixth PMOS transistor PM6 is connected to the drain of the fourth NMOS transistor NM4 and the other end of the eleventh resistor R11. The source of the sixth PMOS transistor PM6 is connected to the power supply voltage VDD, and the source of the fourth NMOS transistor NM4 is grounded. The gate of the sixth PMOS transistor PM6 is connected to the first upper branch node voltage VP1; The gate of the fourth NMOS transistor NM4 is connected to the first lower branch node voltage VN1; One end of the fourth capacitor C4 and one end of the fifth capacitor C5 are respectively connected to the input terminal of the second inverter inv2; The other end of the fourth capacitor C4 is connected to the power supply voltage VDD, and the other end of the fifth capacitor C5 is grounded. One end of the twelfth resistor R12 is connected to the output terminal of the second inverter inv2; The other end of the twelfth resistor R12 is connected to the input terminal of the third inverter inv3; The drain of the seventh PMOS transistor PM7 is connected to the drain of the fifth NMOS transistor NM5 and the other end of the twelfth resistor R12, respectively. The source of the seventh PMOS transistor PM7 is connected to the power supply voltage VDD, and the source of the fifth NMOS transistor NM5 is grounded. The gate of the seventh PMOS transistor PM7 is connected to the second upper branch node voltage VP2; The gate of the fifth NMOS transistor NM5 is connected to the second lower branch node voltage VN2; One end of the sixth capacitor C6 and one end of the seventh capacitor C7 are respectively connected to the input terminal of the third inverter inv3; The other end of the sixth capacitor C6 is connected to the power supply voltage VDD, and the other end of the seventh capacitor C7 is grounded.

7. A high-precision anti-interference wireless charging current demodulation circuit according to claim 6, characterized in that, The anti-spiking filter circuit also includes a fourth inverter inv4, a fifth inverter inv5, a sixth inverter inv6, an AND gate nand, and an OR gate nor; The output of the integrator circuit is connected to the input of the fourth inverter inv4; The output of the fourth inverter inv4 is connected to the first input of the AND gate nand and the first input of the OR gate nor. The output of the third inverter inv3 is connected to the second input of the AND gate nand and the second input of the OR gate nor; The output of the AND gate NAND is connected to the input of the fifth inverter inv5 and the first input of the SR latch, respectively. The output of the OR gate NOR is connected to the input of the sixth inverter, INV6. The output of the sixth inverter inv6 is connected to the second input of the SR latch.

8. A high-precision anti-interference wireless charging current demodulation method, characterized in that, Based on the high-precision anti-interference wireless charging current demodulation circuit according to any one of claims 1-7, the demodulation method includes: The S1 and CS sampling circuits sample the bus current, convert the sampled current into a voltage signal through a sampling resistor, amplify the voltage signal by a fixed factor through the first amplification unit, and then amplify the voltage signal again by a fixed factor through the second amplification unit to obtain the sampled voltage signal. S2. The sampled voltage signal is input into an RC low-pass filter circuit. The DC component is filtered out by a DC blocking capacitor, leaving only the AC component. A DC bias module provides a DC operating point for the DC-blocked AC component. Simultaneously, the AC component is filtered by a first filter branch and a second filter branch connected in parallel. The first filter branch retains the AC component below a preset first cutoff frequency to obtain a first filtered signal, and the second filter branch retains the AC component below a preset second cutoff frequency to obtain a second filtered signal. The first cutoff frequency is greater than the second cutoff frequency, so that the first filtered signal and the second filtered signal have an amplitude difference in the target frequency band. S3. Input the first filtered signal and the second filtered signal into the comparison circuit, and set the comparison inversion point with the threshold voltage to compare the first filtered signal and the second filtered signal to obtain the comparison output signal; S4. Input the comparison output signal into the integration circuit, perform integration processing on the comparison output signal, so that the integrated output signal increases or decreases in a ramp-like manner when the comparison output flips, thereby suppressing transient jumps caused by power supply disturbances and input signal glitches, and obtaining the integrated output signal. S5. Input the integral output signal into the anti-spiking filter circuit, perform RC delay processing on the rising and falling edges of the integral output signal respectively, and latch the delayed rising and falling edges through the SR latch to recover and output a stable current decoding signal.

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