A high linearity radio frequency auxiliary path

Abstract

The application provides a high linearity radio frequency auxiliary channel, which comprises a pre-distortion compensation module and a Cascode circuit, wherein the pre-distortion compensation module is connected with the Cascode circuit. The application improves the compression point without changing the process, and enables the circuit to work in a larger radio frequency acceptance range.

Description

Technical Field

[0001] This invention relates to the field of radio frequency technology, and particularly to the field of radio frequency signal reception. Background Technology

[0002] Currently, the importance of low-noise amplifiers (LNAs) in RF receiver links is increasing, with a plethora of LNAs being used in various application scenarios. They are typically used in the front-end receiver link to amplify signals from antennas or other low-intensity signal sources for subsequent processing and demodulation. Since the LNA is the first stage in a wireless communication system, significant interference signals may exist at its input. Therefore, sufficiently high linearity is essential to prevent intermodulation distortion caused by interference signals from corrupting the carrier signal. At present, the linearity requirements for LNAs are becoming increasingly stringent. While there are many circuits that improve the IIP3 capability of LNAs, circuits that improve the P1dB compression point of LNAs have not been reported.

[0003] In view of this, the present invention is proposed. Summary of the Invention

[0004] The purpose of this invention is to provide a high-linearity radio frequency auxiliary path, which improves linearity by adjusting the compensation of the Cascode circuit through a pre-distortion compensation unit.

[0005] To achieve the above objectives, the present invention is implemented through the following technical solution: A high linearity radio frequency auxiliary path is provided, including a pre-distortion compensation module and a Cascode circuit, wherein the pre-distortion compensation module is connected to the Cascode circuit; The Cascode circuit is used to provide a gain signal to the radio frequency signal; The pre-distortion compensation module is used to provide a negative third-order nonlinear component to adjust the positive third-order nonlinear component in the gain signal of the Cascode circuit. The Cascode circuit includes a first MOSFET, a second MOSFET, a first inductor, a second inductor, a third inductor, a first resistor, a second resistor, a second capacitor, a third capacitor, and a fourth capacitor; In this configuration, one end of the second inductor is connected to VDD, and the other end of the second inductor is connected to the drain of the second MOSFET; the gate of the second MOSFET is connected to one end of the second resistor and one end of the third capacitor, and the source of the second MOSFET is connected to the drain of the first MOSFET; the gate of the first MOSFET is connected to one end of the second capacitor, one end of the first resistor, and one end of the first capacitor, and the source of the first MOSFET is connected to one end of the first inductor and the other end of the second capacitor; the other end of the first inductor is grounded. The other end of the third capacitor is grounded; the other end of the first capacitor is connected to one end of the third inductor. The other end of the first resistor serves as the first input terminal, the other end of the second resistor serves as the second input terminal, and the other end of the third inductor serves as the input terminal to receive radio frequency signals. One end of the fourth capacitor is connected to the drain of the second MOSFET, and the other end of the fourth capacitor serves as the output terminal. The pre-distortion compensation module includes a fifth capacitor, a third MOSFET, and a third resistor; wherein, one end of the fifth capacitor is connected to the drain of the second MOSFET, one end of the fourth capacitor, and the other end of the second inductor, respectively; the other end of the fifth capacitor is connected to the drain and gate of the third MOSFET, respectively; the gate and drain of the third MOSFET are connected; the source of the third MOSFET is connected to one end of the third resistor; and the other end of the third resistor is connected to one end of the second capacitor, one end of the first resistor, and the gate of the first MOSFET, respectively. The first, second, and third MOSFETs are all PMOS transistors; When the amplitude of the RF signal is less than the P1db compression point of the Cascode circuit, the third MOSFET is turned off; when the amplitude of the RF signal is greater than or equal to the P1db compression point of the Cascode circuit, the third MOSFET operates in the negative third-order nonlinear region.

[0006] Furthermore, the Cascode circuit also includes a fourth MOS transistor; The drain of the fourth MOSFET is connected to the source of the second MOSFET; the source of the fourth MOSFET is grounded; the gate of the fourth MOSFET is connected to the drain of both the first MOSFET and the fourth MOSFET; the fourth MOSFET is a PMOS.

[0007] Furthermore, it also includes a bias circuit, which includes a bandgap reference circuit and a current mirror unit. The bandgap reference circuit is connected to the first input terminal and the second input terminal through the current mirror unit.

[0008] Furthermore, it also includes an ESD protection module, which acts as a temporary fast discharge path when a pulse appears in the signal. The ESD protection module includes two diodes connected in reverse parallel. The number of ESD protection modules is two. One ESD protection module is connected at one end to one end of the third inductor and the other end of the first capacitor, and the other end is grounded. The other ESD protection module is connected at one end to the output terminal and the other end of the fourth capacitor, and the other end is grounded.

[0009] Furthermore, it also includes a fourth MOSFET, which is used to shunt the first and second MOSFETs to counteract the nonlinear effects of the Cascode circuit. The fourth MOS transistor is a PMOS transistor; the drain of the fourth MOS transistor is connected to the source of the second MOS transistor and the gate of the fourth MOS transistor, respectively, the gate of the fourth MOS transistor is also connected to the drain of the first MOS transistor, and the source of the fourth MOS transistor is grounded.

[0010] Compared with the prior art, the present invention achieves the following technical effects: This invention improves the compression point without changing the process, enabling the circuit to operate over a wider radio frequency acceptance range. Attached Figure Description

[0011] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the description will be briefly introduced below. Obviously, the drawings described below are one embodiment of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort: Figure 1 This is a schematic diagram of the high linearity radio frequency auxiliary path structure in this embodiment; Figure 2 This is a transient simulation waveform diagram for a small signal input in this embodiment; Figure 3 This is a transient simulation waveform diagram for a large signal input in this embodiment; Figure 4 This is a harmonic simulation (HB) analysis diagram for this embodiment; Figure 5 This is a schematic diagram of the compression point performance simulation in this embodiment.

[0012] Figure reference numerals: Cascode circuit 10, pre-distortion compensation module 20; The first MOSFET is M1, the second MOSFET is M2, the third MOSFET is M3, and the fourth MOSFET is M4. First inductor L1, second inductor L2, third inductor L3; The first resistor is R1, the second resistor is R2, and the third resistor is R3; First capacitor C1, second capacitor C2, third capacitor C3, fourth capacitor C4, fifth capacitor C5; First input terminal Vg1, second input terminal Vg2, signal input terminal Vin; output terminal Vout. Detailed Implementation

[0013] The following detailed description, in conjunction with the accompanying drawings and specific embodiments, further illustrates the solution proposed by the present invention. The advantages and features of the present invention will become clearer from the following description. It should be noted that the drawings are in a very simplified form and use non-precise proportions, used only to facilitate and clearly illustrate the embodiments of the present invention. Please refer to the drawings to make the objectives, features, and advantages of the present invention more apparent and understandable. It should be understood that the structures, proportions, sizes, etc., depicted in the accompanying drawings are only for illustrative purposes to aid those skilled in the art and are not intended to limit the implementation conditions of the present invention. Therefore, they have no substantial technical significance. Any modifications to the structure, changes in proportions, or adjustments to the size, without affecting the effects and objectives achieved by the present invention, should still fall within the scope of the technical content disclosed in the present invention.

[0014] Figure 1 A schematic diagram of the high linearity radio frequency auxiliary path structure of this embodiment is shown. Figure 1 As shown, the high linearity RF auxiliary path in this embodiment includes a Cascode circuit 10 and a pre-distortion compensation module 20.

[0015] The Cascode circuit 10 is used to provide a gain signal to the radio frequency signal; the pre-distortion compensation module 20 is used to provide a negative third-order nonlinear component to adjust the positive third-order nonlinear component in the gain signal provided by the Cascode circuit 10; the Cascode circuit 10 includes a first MOS transistor M1, a second MOS transistor M2, a first inductor L1, a second inductor L2, a third inductor L3, a first resistor R1, a second resistor R2, a second capacitor C2, a third capacitor C3 and a fourth capacitor C4. In this configuration, one end of the second inductor L2 is connected to VDD, and the other end of the second inductor L2 is connected to the drain of the second MOSFET M2. The gate of the second MOSFET M2 is connected to one end of the second resistor R2 and one end of the third capacitor C3, and the source of the second MOSFET M2 is connected to the drain of the first MOSFET M1. The gate of the first MOSFET M1 is connected to one end of the second capacitor C2, one end of the first resistor R1, and one end of the first capacitor C1, and the source of the first MOSFET M1 is connected to one end of the first inductor L1 and the other end of the second capacitor C2. The other end of the first inductor L1 is grounded. The other end of the third capacitor C3 is grounded. The other end of the first capacitor C1 is connected to one end of the third inductor L3. The other end of the first resistor R1 serves as the first input terminal Vg1, and the other end of the second resistor R2 serves as the second input terminal Vg2. The other end of the third inductor L3 serves as the signal input terminal Vin to receive radio frequency signals. One end of the fourth capacitor C4 is connected to the drain of the second MOSFET M2, and the fourth... The other end of capacitor C4 serves as the output terminal Vout; the pre-distortion compensation module 20 includes a fifth capacitor C5, a third MOSFET M3, and a third resistor R3; one end of the fifth capacitor C5 is connected to the drain of the second MOSFET M2, one end of the fourth capacitor C4, and the other end of the second inductor L2, respectively; the other end of the fifth capacitor C5 is connected to the drain and gate of the third MOSFET M3, respectively; the gate and drain of the third MOSFET M3 are connected, the source of the third MOSFET M3 is connected to one end of the third resistor R3, and the other end of the third resistor R3 is connected to one end of the second capacitor C2, one end of the first resistor R1, and the gate of the first MOSFET M1, respectively; the first MOSFET M1, the second MOSFET M2, and the third MOSFET M3 are all PMOS; when the amplitude of the RF signal is less than the P1db compression point, the third MOSFET M3 is cut off; when the amplitude of the RF signal is greater than or equal to the P1db compression point, the third MOSFET M3 operates in the negative third-order nonlinear region.

[0016] exist Figure 1In the circuit shown, the third inductor L3, the first capacitor C1, and the second inductor L2 form the input matching network, while the fourth capacitor C4 forms the output matching network. The fifth capacitor acts as a DC blocking capacitor to maintain the DC voltage at the drain of the second MOSFET. The RF input signal flows through the input matching network, then through the first MOSFET M1 and the second MOSFET M2, and finally is output through the output matching network.

[0017] The third MOSFET M3 is a diode-connected type, and its source is used to sense the current of the first MOSFET M1. When the input voltage is too high, the output voltage is connected to the gate of the third MOSFET M3 through the fifth capacitor C5, thereby turning on the third MOSFET M3; when the input voltage is too low, the third MOSFET is in the off state.

[0018] Preferably, in this embodiment, by adjusting the width-to-length ratio (W / L) of the third MOS transistor, it is made to operate in the negative third-order nonlinear region, thereby providing a negative third-order nonlinear component at point A, which cancels out (vector superposition) the positive third-order nonlinear component of the gain signal generated by the Cascode circuit, ultimately improving the linearity of the entire low-noise amplifier (LNA).

[0019] In low-power designs, the bias voltage is typically slightly higher than the threshold voltage (Vth) to achieve a smaller operating current. Under this condition, the third-order coefficients in the gain signal of the Cascode circuit are usually positive. In this embodiment, the third MOSFET M3 operates in the negative third-order coefficient region to compensate for the third-order nonlinear component. The transient simulation results of the circuit are as follows: Figure 2-5 As shown, when the input voltage is small ( Figure 2 As shown), the third MOSFET M3 is always in the off state; when the input voltage is large ( Figure 3 As shown, the third MOSFET M3 exhibits half-wave conduction and half-wave cutoff characteristics, operating in the negative third-order coefficient region. During the negative half-cycle of the input signal, since the amplification factor of the cascode structure is negative, the corresponding output signal is in the positive half-cycle. At this time, the source of the third MOSFET M3 senses the gate voltage of the first MOSFET M1, forming a voltage difference exceeding the threshold voltage with the output node VA. This causes the gate-source voltage (Vgs) of the third MOSFET M3 to exceed the threshold voltage, turning on the auxiliary path and forming a shunt with the main path. In this embodiment, by adjusting the dimensions of the third MOSFET M3 to operate in the negative third-order coefficient region and vector-superimposing it with the amplified signal from the cascode circuit, nonlinear compensation is achieved. The waveform at node VA shows that its positive half-cycle waveform exhibits characteristics highly similar to a trigonometric function.

[0020] To quantify the third-order harmonic suppression capability, harmonic simulation (HB) can be used for analysis. For example... Figure 4As shown, a single-tone signal is injected at the input terminal, and its third harmonic component is captured at the output port. Simulation results show that when the input signal amplitude is large, the feedforward distortion compensation (FDC) structure effectively suppresses the third harmonic component and has good nonlinear compensation capability.

[0021] Preferably, this embodiment also includes an ESD protection module, which serves as a temporary fast discharge path when a pulse occurs in the signal. The ESD protection module includes two diodes connected in reverse parallel. like Figure 1 As shown, there are two ESD protection modules. One ESD protection module is connected at one end to one end of the third inductor and the other end of the first capacitor, and the other end is grounded. The other ESD protection module is connected at one end to the output terminal and the other end of the fourth capacitor, and the other end is grounded.

[0022] Preferably, this embodiment also includes a fourth MOS transistor M4, which is used to shunt the first MOS transistor M1 and the second MOS transistor M2 to counteract the nonlinear effect of the Cascode circuit 10.

[0023] The fourth MOSFET M4 is a PMOS; the drain of the fourth MOSFET M4 is connected to the source of the second MOSFET M2 and the gate of the fourth MOSFET M4, respectively. The gate of the fourth MOSFET M4 is also connected to the drain of the first MOSFET M1, and the source of the fourth MOSFET M4 is grounded.

[0024] For a linear system, if the input is Acosωt, the output is y(t) = αAcosωt, where α is the amplification factor of the linear system. However, as the frequency increases, the capacitive and inductive characteristics of the circuit gradually become dominant, and many nonlinear characteristics will emerge. In nonlinear, memoryless systems, the input / output characteristics can be approximated as...

[0025] Where, α i Consider the gain of the i-th harmonic of the system; for example, α1 is the small-signal gain of the system. For the simplest common-source amplifier circuit, α1 = -g at low frequencies. m R D The first term in the formula is the DC component caused by second-order nonlinearity, and the second term is α1A+3α2A. 3 / 4 represents the fundamental gain of this system. Compared with a linear system, it has an additional 3α²A gain. 3 / 4, and the gain changes more significantly as the input signal amplitude A increases. Where, if α1α3>0, then |α1+3α3A 2 / 4|>|α1|, resulting in an additional gain of |3α3A compared to a linear system.2 The term / 4| results in a gain expansion phenomenon; conversely, if |α1α3<0|, the gain is additionally reduced by |3α3A compared to a linear system. 2 The / 4| term results in gain compression.

[0026] The 1dB input gain compression point (P1dB) is an important metric for linearity. It is defined as the input power at which the actual output power drops by 1dB compared to the ideal output gain, i.e.:

[0027] Solving for:

[0028] If α3 approaches 0 infinitely, the compression point will theoretically approach infinity.

[0029] In LNAs, linearity is mostly determined by the current i. d With voltage v gs The changing functional relationship is related and can be written as:

[0030] Therefore, α is the DC characteristic of the MOSFET. m The nth harmonic gain α is i d With v gs The changing n-1th order partial derivative:

[0031] Based on the above principle, the technique of derivative superposition is used to shunt the current from M1 and M2 on the main circuit through the M4 transistor, and the size of M4 is adjusted so that the higher-order partial derivative coefficient of the total current tends to 0, thereby improving the linearity.

[0032] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0033] Although the present invention has been described in detail through the preferred embodiments above, it should be understood that the above description should not be considered as a limitation of the present invention. Various modifications and substitutions to the present invention will be apparent to those skilled in the art after reading the above description. Therefore, the scope of protection of the present invention should be defined by the appended claims.

Claims

1. A high linearity radio frequency auxiliary path, characterized in that, It includes a pre-distortion compensation module and a Cascode circuit, wherein the pre-distortion compensation module is connected to the Cascode circuit; The Cascode circuit is used to provide a gain signal to the radio frequency signal; The pre-distortion compensation module is used to provide a negative third-order nonlinear component to adjust the positive third-order nonlinear component in the gain signal of the Cascode circuit. The Cascode circuit includes a first MOSFET, a second MOSFET, a first inductor, a second inductor, a third inductor, a first resistor, a second resistor, a second capacitor, a third capacitor, and a fourth capacitor; In this configuration, one end of the second inductor is connected to VDD, and the other end of the second inductor is connected to the drain of the second MOSFET; the gate of the second MOSFET is connected to one end of the second resistor and one end of the third capacitor, and the source of the second MOSFET is connected to the drain of the first MOSFET; the gate of the first MOSFET is connected to one end of the second capacitor, one end of the first resistor, and one end of the first capacitor, and the source of the first MOSFET is connected to one end of the first inductor and the other end of the second capacitor; the other end of the first inductor is grounded. The other end of the third capacitor is grounded; the other end of the first capacitor is connected to one end of the third inductor. The other end of the first resistor serves as the first input terminal, the other end of the second resistor serves as the second input terminal, and the other end of the third inductor serves as the input terminal to receive radio frequency signals. One end of the fourth capacitor is connected to the drain of the second MOSFET, and the other end of the fourth capacitor serves as the output terminal. The pre-distortion compensation module includes a fifth capacitor, a third MOSFET, and a third resistor; wherein, one end of the fifth capacitor is connected to the drain of the second MOSFET, one end of the fourth capacitor, and the other end of the second inductor, respectively; the other end of the fifth capacitor is connected to the drain and gate of the third MOSFET, respectively; the gate and drain of the third MOSFET are connected; the source of the third MOSFET is connected to one end of the third resistor; and the other end of the third resistor is connected to one end of the second capacitor, one end of the first resistor, and the gate of the first MOSFET, respectively. The first, second, and third MOSFETs are all PMOS transistors; When the amplitude of the RF signal is less than the P1db compression point of the Cascode circuit, the third MOSFET is turned off; when the amplitude of the RF signal is greater than or equal to the P1db compression point of the Cascode circuit, the third MOSFET operates in the negative third-order nonlinear region.

2. The high linearity radio frequency auxiliary path as described in claim 1, characterized in that, The Cascode circuit also includes a fourth MOS transistor; The drain of the fourth MOSFET is connected to the source of the second MOSFET; the source of the fourth MOSFET is grounded; the gate of the fourth MOSFET is connected to the drain of the first MOSFET and the drain of the fourth MOSFET respectively; the fourth MOSFET is a PMOS.

3. The high linearity radio frequency auxiliary path as described in claim 1, characterized in that, It also includes a bias circuit, which includes a bandgap reference circuit and a current mirror unit. The bandgap reference circuit is connected to the first input terminal and the second input terminal through the current mirror unit.

4. The high linearity radio frequency auxiliary path as described in claim 1, characterized in that, It also includes an ESD protection module, which serves as a temporary fast discharge path when a pulse occurs in the signal; The ESD protection module includes two diodes connected in reverse parallel. The number of ESD protection modules is two. One ESD protection module is connected at one end to one end of the third inductor and the other end of the first capacitor, and the other end is grounded. The other ESD protection module is connected at one end to the output terminal and the other end of the fourth capacitor, and the other end is grounded.

5. The high linearity radio frequency auxiliary path as described in claim 1, characterized in that, It also includes a fourth MOSFET, which is used to shunt the first and second MOSFETs to counteract the nonlinear effects of the Cascode circuit; The fourth MOS transistor is a PMOS transistor; the drain of the fourth MOS transistor is connected to the source of the second MOS transistor and the gate of the fourth MOS transistor, respectively, the gate of the fourth MOS transistor is also connected to the drain of the first MOS transistor, and the source of the fourth MOS transistor is grounded.

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