Heterogeneous multi-core chip power consumption state control system and heterogeneous multi-core chip

Abstract

The application provides a heterogeneous multi-core chip power consumption state control system and a heterogeneous multi-core chip, wherein the system hardware power consumption management module is arranged to receive power consumption state requests of each sub power supply domain, send driving signals to the corresponding sub power supply domain according to a preset hardware time sequence to make the corresponding sub power supply domain enter a target state, and generate a PMU control signal; and then the power supply management module drives the internal voltage regulator to perform corresponding adjustment operation according to the PMU control signal. The application does not need a special control processor (SCP), directly controls the power consumption state of each sub power supply domain in the heterogeneous multi-core SoC by using a pure hardware system hardware power consumption management module, eliminates software processing delay, has fast response speed, and significantly reduces the static power consumption of the power consumption management module itself, is particularly suitable for ultra-low power consumption scenes, and realizes hardware level inrush current protection during the multi-core power-on process.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design technology, and in particular to a power consumption state control system for a heterogeneous multi-core chip and a heterogeneous multi-core chip. Background Technology

[0002] In modern high-performance, low-power system-on-chip (SoC) designs, heterogeneous multi-core architecture has become mainstream. This architecture integrates multiple processor cores (such as CPUs, DSPs, AI accelerators, etc.) with different functions and performance to work together to meet the performance and power consumption requirements of different application scenarios. To achieve the ultimate energy efficiency ratio, fine-grained power management is crucial.

[0003] In this context, the entire SoC is typically divided into multiple independent power domains, with each core and its tightly coupled peripherals forming a sub-power domain. By independently controlling the power supply and clock of each sub-power domain, idle subsystems can be dynamically placed into light sleep, deep sleep, or even shutdown states based on task load during system operation, thereby minimizing overall power consumption.

[0004] Currently, a dedicated System Control Processor (SCP) is used for centralized power management. Each heterogeneous core (such as AP CPU0, MCU CPU1, DSP, etc.) is treated as a subsystem. When they wish to enter or exit a low-power state, they send a request to the SCP via shared memory or a message queue. The firmware running on the SCP is responsible for collecting and arbitrating all requests from the subsystems. Then, based on a preset system-level power consumption strategy, it makes unified decisions and controls the voltage regulators (such as DC-DC converters and LDOs) and clock generation unit in the Power Management Unit (PMU) to adjust the power and clock states of each subsystem, thereby coordinating the overall power consumption of the chip.

[0005] However, this method is suitable for situations with a small number of subsystems and requires limited power consumption variations without the need for rapid transitions. In current SoC chips, the number of heterogeneous multi-cores is increasing, and the power consumption variations of each core are also becoming more frequent. This software-based power management approach is no longer suitable. On the one hand, the software complexity of the System Power Management Processor (SCP) increases rapidly with the number of cores. On the other hand, in some extreme power consumption scenarios, the software cannot respond quickly to power control requests, and the slow scenario switching can easily lead to missed opportunities to enter low-power scenarios, thus limiting the supported power consumption scenarios and reducing the overall low-power performance.

[0006] Furthermore, the System Control Processor (SCP) is itself part of the system and also consumes a portion of the power. For some ultra-low power applications, especially wearable devices sensitive to quiescent current, the SCP itself requires power management, increasing design complexity and thus limiting the application of the solution. Summary of the Invention

[0007] In view of the shortcomings of the prior art described above, the purpose of this invention is to provide a heterogeneous multi-core chip power state control system and a heterogeneous multi-core chip, in order to solve the technical problems of slow response speed, high software complexity, high power consumption and surge current risk of existing heterogeneous multi-core chip power management using traditional system controller processors (SCP).

[0008] To achieve the above and other related objectives, the present invention provides a heterogeneous multi-core chip power consumption state control system. The method includes: multiple heterogeneous sub-power domains; a system hardware power management module, located within the normally-on power domain of the chip, for receiving power consumption state requests from each sub-power domain, sending drive signals to the corresponding sub-power domain according to a preset hardware timing sequence to cause the corresponding sub-power domain to enter a target state, and generating PMU control signals; and a power management module, internally containing multiple voltage regulators, for driving the corresponding voltage regulators to perform corresponding adjustment operations according to the PMU control signals.

[0009] In one embodiment of the present invention, each sub-power domain includes: a sub-power domain functional module and a sub-power domain low-power control interface unit; wherein, the sub-power domain functional module includes: a core processor, a direct memory access controller, an on-chip memory, a specific IP functional module, and a clock / reset management module; the sub-power domain power control interface unit provides a physical control interface between the sub-power domain and the system hardware power management module, including: a power switch enabled by the system hardware power management module, an isolation unit, a clock / reset control interface unit, and a memory power control interface unit.

[0010] In one embodiment of the present invention, each sub-power domain includes: a sub-power domain functional module and a sub-power domain low-power control interface unit; wherein, the sub-power domain functional module includes: a core processor, a direct memory access controller, an on-chip memory, a specific IP functional module, and a clock / reset management module; the sub-power domain power control interface unit provides a physical control interface between the sub-power domain and the system hardware power management module, including: a power switch enabled by the system hardware power management module, an isolation unit, a clock / reset control interface unit, and a memory power control interface unit.

[0011] In one embodiment of the present invention, the system hardware power management module includes: a sub-power domain power state machine corresponding to each sub-power domain, a system-level power state aggregation logic module, a system-level power state machine, and multiple timing generators equipped for different shared resources of each sub-power domain; wherein, each sub-power domain power state machine is used to receive power state requests from each sub-power domain and send drive signals to the corresponding sub-power domain according to a preset hardware timing sequence to cause the corresponding sub-power domain to enter a target state; the states of the sub-power domain power state machine include: off state, deep sleep state, light sleep state, and normal operation state; the system-level power state aggregation logic module is used to calculate the system-level aggregated power state based on the states output by each sub-power domain power state machine according to a preset aggregation rule; the system-level power state machine is used to record the current system-level power state and trigger the corresponding timing generator; each timing generator is used to generate a precisely timed PMU control pulse after being triggered and send it to the power management module.

[0012] In one embodiment of the present invention, the sub-power domain power consumption state machine includes: a sub-power domain logic power consumption control state machine, configured to, upon receiving a power consumption state request from the corresponding sub-power domain, initiate a state transition and send one or more of the enable signals of the isolation unit and the clock / reset control unit to the corresponding sub-power domain according to a preset hardware timing sequence; and a sub-power domain memory power consumption control state machine, configured to, upon receiving a power consumption state request from the corresponding sub-power domain, initiate a state transition and send an enable signal of the memory power consumption control unit to control the power consumption state of all internal memory units of the heterogeneous sub-power domain.

[0013] In one embodiment of the present invention, when each sub-power domain power state machine receives a sleep request sent by the corresponding sub-power domain, the state machine starts to jump, sends a drive signal to the corresponding sub-power domain according to a preset hardware timing sequence, causes the corresponding sub-power domain to enter the target sleep state, and outputs the corresponding state to the system-level power state aggregation logic module. The system-level power state aggregation logic module calculates the system-level aggregated power state according to the state output by each sub-power domain power state machine based on a preset aggregation rule, receives the system-level aggregated power state through the system-level power state machine, and triggers the corresponding timing generator to generate a series of precise timing control signals to control the corresponding adjustment operation of the voltage regulator in the power management module.

[0014] In one embodiment of the present invention, the system hardware power consumption management module further includes: a system wake-up source mapping module and a power-on sequence arbitrator; wherein, the system wake-up source mapping module is used to receive the wake-up signal of the system wake-up source, match the heterogeneous sub-power domains configured to be woken up by the system wake-up source and generate corresponding sub-power domain wake-up request signals, and form a system-level wake-up request; the power-on sequence arbitrator is used to receive the wake-up request signals of each sub-power domain and arbitrate to determine the power-on sequence, so that the power consumption state machine of each sub-power domain sends drive signals to the heterogeneous sub-power domains in sequence to wake up the corresponding sub-power domains.

[0015] In one embodiment of the present invention, when the system wake-up source mapping module receives the wake-up signal of the system wake-up source, it matches the heterogeneous sub-power domain configured for wake-up by the system wake-up source and generates a corresponding sub-power domain wake-up request signal, and forms a system-level wake-up request to be sent to the system-level power state machine. When the system-level power state machine receives the system-level wake-up request, it drives the current system-level power state to jump from the corresponding sleep state to the normal working state, triggers the timing generator to generate a precisely timed PMU control pulse and sends it to the power management module, so that each resource falls back to the normal working state. Then, the system-level power state machine jumps to the normal working state and sets the PMU power recovery complete signal. When the power-on sequence arbitrator receives the PMU power recovery complete signal, it starts to accept the wake-up request signals of each sub-power domain, and makes an arbitration to determine the power-on sequence, so that the power state machine of each sub-power domain controls each sub-power domain to be powered on in sequence.

[0016] In one embodiment, the aggregation rule includes: taking the highest power consumption state among the received states of each sub-power domain as the system-level aggregated power consumption state; wherein, the states of the heterogeneous sub-power domains are arranged in descending order of power consumption as: normal operation state, light sleep state, deep sleep state, and off state.

[0017] In one embodiment, the system hardware power management module sets up a partial sub-power domain power status aggregation module according to each resource shared by the partial heterogeneous sub-power domains, so as to calculate the partial sub-power domain power aggregation state according to the state of the heterogeneous sub-power domains sharing the corresponding resources based on a preset aggregation rule; when the system-level power state machine receives the system-level aggregated power status output by the system-level power status aggregation logic module, it triggers the timing generators configured for the resources shared by all heterogeneous sub-power domains; when the system-level power state machine receives the partial sub-power domain power aggregation state output by the partial sub-power domain power status aggregation module, it triggers the timing generators configured for the resources shared by the partial heterogeneous sub-power domains.

[0018] To achieve the above and other related objectives, the present invention provides a heterogeneous multi-core chip, including: the heterogeneous multi-core chip power consumption state control system.

[0019] As described above, this invention is a heterogeneous multi-core chip power consumption state control system and a heterogeneous multi-core chip, which has the following beneficial effects: This invention receives power consumption state requests from each sub-power domain through a system hardware power management module, sends drive signals to the corresponding sub-power domain according to a preset hardware timing sequence to bring the corresponding sub-power domain into the target state, and generates PMU control signals; then, the power management module drives the internal voltage regulator to perform corresponding adjustment operations according to the PMU control signals. This invention does not require a dedicated control processor (SCP). The system hardware power management module, implemented purely in hardware, directly controls the power consumption state of each sub-power domain in the heterogeneous multi-core SoC, eliminating software processing latency, providing fast response speed, and significantly reducing the static power consumption of the power management module itself. It is particularly suitable for ultra-low power consumption scenarios and achieves hardware-level surge current protection during multi-core power-up. Attached Figure Description

[0020] Figure 1 The diagram shown is a structural schematic of a heterogeneous multi-core chip power consumption state control system according to an embodiment of the present invention.

[0021] Figure 2 The diagram shown is a structural schematic of a heterogeneous multi-core chip power consumption state control system according to an embodiment of the present invention.

[0022] Figure 3 The diagram shown is a structural schematic of a sub-power domain in one embodiment of the present invention.

[0023] Figure 4 The diagram shown is a structural schematic of a system hardware power management module according to an embodiment of the present invention.

[0024] Figure 5 The diagram shown is a structural schematic of a sub-power domain power consumption state machine according to an embodiment of the present invention.

[0025] Figure 6 The diagram shown is a schematic representation of the system-level power consumption state aggregation effect in one embodiment of the present invention.

[0026] Figure 7 The diagram shown is a schematic representation of system-level power consumption state aggregation in one embodiment of the present invention.

[0027] Figure 8 The diagram shown is a special case of system-level power state aggregation extension in one embodiment of the present invention.

[0028] Figure 9 The diagram shown is a schematic of chip system-level sleep and wake-up management in one embodiment of the present invention.

[0029] Figure 10 The diagram shows the effect of chip system-level surge protection in one embodiment of the present invention.

[0030] Figure 11 The diagram shown is a structural schematic of a heterogeneous multi-core chip according to an embodiment of the present invention.

[0031] Figure 12 The diagram shown is a structural schematic of an electronic terminal according to an embodiment of the present invention. Detailed Implementation

[0032] The following specific examples illustrate the implementation of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, unless otherwise specified, the following embodiments and features described therein can be combined with each other.

[0033] It should be noted that in the following description, reference is made to the accompanying drawings, which illustrate several embodiments of the invention. It should be understood that other embodiments may also be used, and changes in mechanical composition, structure, electrical system, and operation may be made without departing from the spirit and scope of the invention. The following detailed description should not be considered limiting, and the scope of the embodiments of the invention is defined only by the claims of the published patents. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. Spatially related terms, such as “upper,” “lower,” “left,” “right,” “below,” “below,” “lower part,” “above,” “upper part,” etc., may be used herein to illustrate the relationship between one element or feature shown in the figures and another element or feature.

[0034] Throughout this specification, when it is said that a part is "connected" to another part, this includes not only "direct connection" but also "indirect connection" by placing other elements in between. Furthermore, when it is said that a part "includes" a certain constituent element, unless otherwise stated otherwise, this does not exclude other constituent elements, but rather means that other constituent elements may also be included.

[0035] The terms "first," "second," and "third," etc., used herein are for the purpose of describing various parts, components, regions, layers, and / or segments, but are not limiting. These terms are used only to distinguish one part, component, region, layer, or segment from others. Therefore, the "first part," "component," "region," "layer," or "segment" described below may refer to a "second part," "component," "region," "layer," or "segment" without departing from the scope of this invention.

[0036] Furthermore, as used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context indicates otherwise. It should be further understood that the terms “comprising,” “including,” indicate the presence of the stated feature, operation, element, component, item, kind, and / or group, but do not preclude the presence, occurrence, or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms “or” and “and / or” as used herein are interpreted as inclusive, or mean any one or any combination thereof. Thus, “A, B, or C” or “A, B, and / or C” means “any one of: A; B; C; A and B; A and C; B and C; A, B, and C.” Exceptions to this definition arise only when combinations of elements, functions, or operations are inherently mutually exclusive in some manner.

[0037] This invention provides a power status control system for heterogeneous multi-core chips. A dedicated system hardware power management module receives power status requests from each sub-power domain, sends drive signals to the corresponding sub-power domains according to a preset hardware timing sequence to bring them into a target state, and generates PMU control signals. The power management module then drives the internal voltage regulator to perform corresponding adjustment operations based on the PMU control signals. This invention eliminates the need for a dedicated control processor (SCP), using a purely hardware-based system hardware power management module to directly control the power status of each sub-power domain in the heterogeneous multi-core SoC. This eliminates software processing latency, provides fast response speed, and significantly reduces the static power consumption of the power management module itself. It is particularly suitable for ultra-low power consumption scenarios and provides hardware-level surge current protection during multi-core power-up.

[0038] Before providing a further detailed description of the present invention, the nouns and terms used in the embodiments of the present invention are explained, and the nouns and terms used in the embodiments of the present invention are subject to the following interpretations:

[0039] <1> SoC (System-on-Chip): System-on-a-chip;

[0040] <2> PMU (Power Management Unit): The power management unit is responsible for providing the various voltages required by the chip, such as LDO and DC-DC.

[0041] <3> PMM (Power Management Module): Power management module;

[0042] <4> SCP (System Control Processor): A dedicated processor used for power management in the prior art.

[0043] <5> CPU (Central Processing Unit): The central processing unit;

[0044] <6> DSP (Digital Signal Processor): A digital signal processor;

[0045] <7> LDO (Low Dropout Regulator): Low dropout linear regulator;

[0046] <8> DCDC (DC-to-DC converter): A direct-to-current converter;

[0047] <9> WFI (Wait For Interrupt): Wait for an interrupt, a processor instruction that puts the processor into a low-power state;

[0048] <10> FSM (Finite State Machine): A finite state machine;

[0049] <11> XTAL (Crystal Oscillator): Crystal oscillator;

[0050] <12> PLL (Phase-Locked Loop): A phase-locked loop;

[0051] <13> LF-RCO (Low Frequency RC Oscillator): A low-frequency RC oscillator;

[0052] <14> HF-RCO (High Frequency RC Oscillator): A high-frequency RC oscillator;

[0053] <15> DMA (Direct Memory Access);

[0054] <16> SRAM (Static Random Access Memory): Static random access memory;

[0055] <17> ROM (Read-Only Memory): Read-only memory.

[0056] The present invention will now be described in detail with reference to the accompanying drawings, so that those skilled in the art can readily implement it. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0057] like Figure 1This invention presents a schematic diagram of a heterogeneous multi-core chip power consumption state control system according to an embodiment of the present invention.

[0058] The system includes:

[0059] Multiple heterogeneous sub-power domains; wherein, the chip is divided into multiple independent power domains according to function, and each power domain can be powered on or off independently. For example, Figure 2 The diagram illustrates the voltage domains of the CORE0, CORE1, and CORE2 subsystems. The CORE0 subsystem can be a high-performance application processor (AP), CORE1 can be a Bluetooth (BT) or WiFi subsystem responsible for wireless communication, and CORE2 can be a dedicated audio processing DSP subsystem. The power state of each sub-power domain is directly controlled by the system's hardware power management module. It should be noted that this solution can use larger modules as sub-power domains, or it can perform finer-grained divisions, such as dividing different computing units (e.g., FPU, NN) within a large CPU core into independent sub-domains and incorporating them into the PMM's management system.

[0060] The system hardware power management module (PMM) is a purely hardware-implemented logic module located within the chip's normally-on power domain. A normally-on power domain is one that remains powered unless the entire chip is completely powered down. This ensures that the PMM can still function normally, responding to wake-up events or managing system states, even when all other sub-power domains are powered down. The PMM receives power status requests from each sub-power domain, sends drive signals to the corresponding sub-power domains according to a preset hardware timing sequence to bring them into the target state, and generates PMU control signals.

[0061] The Power Management Unit (PMU) contains various voltage regulators, such as DC-DC converters (DCDC_MEM, DCDC_LOGIC) for efficient power supply and low-dropout linear regulators (LDO_LOGIC) for providing stable, low-noise voltage. The PMU controls the corresponding voltage regulators to perform various regulation operations based on PMU control signals, such as enabling, disabling, and regulating the voltage of each regulator.

[0062] In one embodiment, such as Figure 3 Each sub-power domain includes:

[0063] The sub-power domain functional modules include: a core processor (such as an ARM CPU or a RISC-V CPU), a direct memory access controller (DMA), on-chip memory (SRAM / ROM), and several specific IP functional modules related to the subsystem's functions (such as WiFi MAC layer logic, Bluetooth baseband logic, etc.). These modules are interconnected via an internal bus. In addition, the sub-power domain includes its own clock reset management module. The entire sub-power domain, as a whole, can be independently controlled for power and clock cycles.

[0064] The sub-power domain low-power control interface unit provides a physical control interface between the sub-power domain and the PMM to adapt to independent power management chip scenarios. These interface signals are all directly generated by the PMM hardware and are used to finely control the power consumption state of the sub-power domain.

[0065] The sub-power domain low-power control interface unit includes:

[0066] Power Switch: Typically composed of PMOS transistors, the power switch is used to physically connect or disconnect the power supply to the sub-power domain. Its enable signals PS_eb_major and PS_eb_minor (primary and secondary power switch enable) are controlled by the PMM.

[0067] Isolation Cell: When a sub-power domain is to be powered down, all its output signals need to be clamped to a defined state (such as logic 0 or logic 1) to prevent uncertain level signals from leaking to other still-operating power domains and causing system malfunctions. The isolation cell's enable signal, Isolation_en, is pulled high by the PMM before power-down and pulled low after power-up.

[0068] Clock / Reset Control Interface Unit: CGM_EN is the clock gating enable signal, used to stop the subsystem clock in Lightsleep mode. RST_N is a low-active reset signal, used by the PMM to reset the subsystem.

[0069] Memory Power Control Interface Unit: For SRAM or ROM macrocells within the sub-power domain, the PMM also directly controls their low-power pins. The PD pin is used to put the memory into power-down mode, and the RET pin is used to switch the memory cell to an extremely low-power retention power supply when the logic circuit is powered off, thereby retaining the data stored therein. This is called retention mode.

[0070] In addition to using dedicated parallel signal lines, these interfaces can also communicate via a lightweight serial bus (such as I2C / SPI or a custom protocol). Through this set of sophisticated hardware control interfaces, the PMM can perform precise timing control on the power-on / off, clock switching, and state holding behaviors of each power domain.

[0071] In one embodiment, such as Figure 4 The system hardware power consumption management module includes:

[0072] Each sub-power domain is assigned a separate, hardware-implemented sub-power domain power state machine (PowerFSM), such as the CORE0 power state machine, CORE1 power state machine, and CORE3 power state machine. Each Power FSM is responsible for managing the lifecycle of its corresponding subsystem. Internally, the Power FSM is a state machine with states including: normal operation (ON), light sleep (LIGHTSLEEP), deep sleep (DEEPSLEEP_RET), and off (OFF). Upon receiving a request, the FSM will drive the aforementioned drive signals such as PS_en, CGM_EN, and Isolation_en according to the request type and preset hardware timing, causing the sub-power domain to enter the target state.

[0073] The system-level power consumption state aggregation logic module is used to collect the output states of the power consumption state machines of all sub-power domains in real time, and calculate the system-level aggregated power consumption state according to the preset aggregation rules.

[0074] A system-level power state machine is used to record the current system-level power state and trigger the corresponding timing generator;

[0075] Multiple timing generators are provided for the different shared resources in each sub-power domain, such as the PMMLDO sequencer (controlling the PMM's own LDO), the DC-DCLDO sequencer (controlling the shared DC-DC and LDO), and the XTAL / PLL sequencer (controlling the crystal oscillator and PLL). When triggered, these timing generators generate a series of precisely timed control pulses to gradually and safely turn the corresponding PMU analog modules on or off, or change their output voltages. The timing generator can be a hardwired state machine or a more flexible microcode-based microengine. The latter allows for modification of power timings after chip manufacturing by updating the microcode, providing greater flexibility.

[0076] In one embodiment, such as Figure 5 The sub-power domain power consumption state machine includes:

[0077] The sub-power domain logic power consumption control state machine is used to start transitioning when a power consumption state request is received from the corresponding sub-power domain. The state machine sends one or more of the enable signals of the isolation unit and the clock / reset control unit to the corresponding sub-power domain according to the preset hardware timing.

[0078] The sub-power domain memory power control state machine initiates transitions upon receiving a power state request from the corresponding sub-power domain, driving the memory power control unit to manage the power state of all memory cells within the heterogeneous sub-power domain. Specifically, the power management of the random access memory (RAM) and read-only memory (ROM) within the sub-power domain is directly handled by the sub-power domain core. To achieve more refined power control, the sub-power domain memory power control state machine allows for individual setting and adjustment of the power state of each independent memory cell (memory block, instance) within the corresponding sub-power domain. This ensures that each memory block is in an appropriate power mode under different sub-power domain power states, including normal operation (ON), data retention (RETENTION), and complete power-off (OFF). Furthermore, to mitigate potential inrush current issues, the sub-power domain memory power control state machine features a sequential recovery function, supporting each memory block to gradually recover to the power-on (ON) state in a predetermined order, ensuring the stability and reliability of the entire sub-power domain during power adjustment.

[0079] For a specific example, after the subsystem CPU executes instructions such as WFI, these instructions are automatically generated by hardware and sent to the PMM via signal lines such as sleep_req (sleep request) and sleep_type (sleep type code). When the sub-power domain logic power control state machine pulls CGM_EN low, the main clock of the subsystem is turned off, the subsystem power supply remains on, and the internal logic and RAM are not lost.

[0080] Combining the above heterogeneous multi-core chip power state control system architecture, low-power state management of sub-power domains can be achieved. The specific implementation method is as follows:

[0081] Sleep requests for each sub-power domain can be initiated individually based on their respective application load states. First, the type of power state and clock source state required to enter sleep mode must be determined, and the type of power state and clock state required to exit sleep mode must be estimated. Then, the request is initiated using the core's WFI instruction. The WFI instruction is typically supported in common CPU (such as ARM, RISC-V) or DSP core instruction sets.

[0082] To achieve fine-grained management, a set of power consumption states is defined for each sub-power domain. Each sub-power domain can independently enter the following power consumption states (arranged in ascending order of power consumption):

[0083] In the OFF state, the sub-power domain is completely de-energized and no state is retained.

[0084] Deep sleep (DEEPSLEEP) is a power-off state, but it retains the state information of registers and RAM; light sleep (LIGHTSLEEP) maintains power supply and state, only turning off the sub-power domain clock, while necessary clock sources remain on.

[0085] Normal operating state (ON), at which time the sub-power domain is fully functional.

[0086] The heterogeneous sub-power domain offers flexible clock source usage, allowing for the selection of appropriate power consumption and latency combinations based on different scenario requirements. Among them, the LF-RCO (low-frequency RC) clock source has the lowest power consumption and is always available, serving as the main operating clock in power-off or ultra-low power modes; the HF-RCO (high-frequency RC) clock source has slightly lower power consumption, with a startup latency typically below 10µs, suitable for energy-saving scenarios requiring low latency and low precision; the XTAL (crystal oscillator) clock source has higher power consumption but excellent precision, although its startup latency is typically above 1ms, and is mostly used in high-precision timing scenarios; the PLL clock source has the highest power consumption but provides the highest performance, with a startup latency of approximately 10–20µs. Due to its high power consumption, power control units typically avoid using PLL clocks.

[0087] Regarding typical configuration rules, different operating modes have clear clock source configuration requirements. In the shutdown mode, only the LF-RCO clock source is retained; in the sleep mode (deep sleep, light sleep), the LF-RCO clock source is retained, and the HF-RCO or XTAL clock source is retained depending on the specific scenario. The PLL clock source is usually disabled; in the normal operation mode, a combination of LF-RCO, XTAL, and PLL clock source configuration is used.

[0088] In one embodiment, when the power control state machine of each sub-power domain receives a sleep request (light sleep request or deep sleep request) from the corresponding sub-power domain, it immediately initiates a state transition process. Following this, it sequentially drives signals such as power switch (ps_en), clock gating (cgm_en), reset (rst_n), and isolation control (isolation_en). This series of operations will cause the corresponding sub-power domain to smoothly enter the target sleep state. Simultaneously, the state machine also outputs corresponding state information (chip_in_light_sleep and chip_in_deep_sleep, etc.) to the system-level power state aggregation logic module. After receiving the states output by the power state machines of each sub-power domain, the system-level power state aggregation logic module performs precise calculations of the system-level aggregated power state according to pre-set aggregation rules. The calculated system-level aggregated power state is transmitted to the system-level power state machine. Upon receiving the system-level aggregated power state, the system-level power state machine quickly triggers the corresponding timing generator. The timing generator then generates a series of precisely timed control pulses, which will precisely control the adjustment operation of the corresponding voltage regulator in the power management module, ensuring that the entire system achieves efficient and stable operation in terms of power consumption control.

[0089] Specifically, in the scenario of entering a lightsleep state: when a sub-power domain has no pending tasks during a specific period, it can send a request to the power management module (PMM) to enter the lightsleep state via a pre-defined interface. Upon receiving the request, the PMM immediately starts the hardware state machine and automatically gates the clock of the sub-power domain through hardware logic, precisely controlling the supply of the clock signal. Typically, the PMM puts the random access memory (RAM) within the sub-power domain into a RETENTION state, reducing power consumption while ensuring no data loss. Furthermore, depending on actual needs, the PMM can selectively disable the read-only memory (ROM) within the sub-power domain to further reduce energy consumption.

[0090] Scenario for entering Deep Sleep state: If a sub-power domain needs to sleep for an extended period to conserve energy, it can send a request to the PMM to enter Deep Sleep state. Upon receiving the request, the PMM will execute operations according to precise hardware timing: First, it will isolate the output signals of the sub-power domain to prevent interference with other parts; then, it will turn off the power switch of the sub-power domain, de-energizing its logic components. Simultaneously, the PMM will trigger the sub-power domain's memory power control state machine, ensuring that the RAM within the sub-power domain enters the RETENTION state, keeping the RAM on a dedicated low-power hold-up power supply, reducing power consumption while ensuring data recovery.

[0091] Scenarios for entering the OFF state: When a sub-power domain needs to completely stop working and enter a fully powered-off state, its operation timing is similar to entering a deep sleep state. However, during this process, the PMM will trigger the sub-power domain memory power control state machine to ensure that the RAM inside the sub-power domain enters the SHUTDOWN state, so that the RAM completely stops working and achieves maximum energy saving.

[0092] In one embodiment, a typical System-on-Chip (SoC) architecture typically contains multiple sub-power domains, such as CORE0, CORE1, CORE2, etc., which may share the same voltage regulator. From a low-power design perspective, it is crucial for each sub-power domain to always maintain a low-power state. Once a sub-power domain experiences an idle period, it should be switched to an acceptable lower-power state as soon as possible to reduce energy consumption. For the low-dropout linear regulator (LDO) that powers all these sub-power domains, its output voltage must be able to meet the highest voltage requirement of all sub-power domains currently using it. Generally, this voltage aggregation method for shared LDOs is suitable for scenarios with multiple shared voltage regulators, such as... Figure 6 As shown on the left. It's easy to see that while performing voltage aggregation for each voltage regulator individually is theoretically feasible, tracking multiple aggregation results simultaneously complicates the system. Therefore, a simpler approach is to first aggregate the power states of multiple subsystems, such as... Figure 7 .

[0093] First, the four power consumption states of each sub-voltage domain, namely OFF, DEEPSLEEP_RET, LIGHTSLEEP, and ON, need to be mapped to a specific voltage requirement value.

[0094] ON state: In this state, the sub-power domain requires a normal operating voltage to maintain the normal operation of its various functions, such as 0.8V.

[0095] LIGHTSLEEP state: In this state, the logic portion of the sub-power domain and the random access memory (RAM) are not in an active state, but their internal state needs to be retained. Therefore, the RAM or part of the logic requires a low retention voltage to maintain the state, such as 0.55V.

[0096] DEEPSLEEP_RET state: In this state, most of the logic is gated or turned off, but RAM or some logic also requires a low retention voltage to maintain the state, such as 0.55V.

[0097] OFF state: The subsystem is completely stopped and its voltage requirement is 0V.

[0098] Based on the above definition, the system-level aggregated power state is defined as the maximum power state of each sub-core within the system. The power states of each sub-core are arranged in the order of (ON > LIGHTSLEEP > DEEPSLEEP > OFF).

[0099] The specific aggregation rules are as follows:

[0100] Normal operating state (CHIP_ON) rule: The system-level aggregate power consumption state is in the operating state (CHIP_ON) when at least one of the sub-power domains is in the ON state. This means that the system as a whole is in normal operating mode and needs to provide normal operating voltage to meet the functional requirements of each subsystem.

[0101] Light Sleep State Rule: If the maximum power consumption state of each sub-power domain is Light Sleep, meaning all sub-power domains are in Light Sleep, Deep Sleep, or OFF state, and at least one sub-power domain is in Light Sleep, then the system-level aggregated power consumption state is in Light Sleep state. In this case, the power management module (PMM) will reduce the shared digital voltages (such as LDO_CORE and DCDC_MEM) to the minimum holding voltage (0.55V), switch the crystal oscillator (XTAL) to low-power mode, and shut down non-essential resources such as the phase-locked loop (PLL) to maximize idle power savings.

[0102] Deep Sleep State (DEEPSLEEP_RET) Rule: When the maximum power consumption state of each sub-power domain is DEEPSLEEP_RET, meaning all subsystems are in either DEEPSLEEP_RET or OFF state, and at least one subsystem is in DEEPSLEEP_RET state (not OFF state), then the system-level aggregated power consumption state is in deep sleep state. At this time, because RAM needs to maintain its state, the LDO_CORE and DCDC_MEM powering the digital core via PMM need to remain enabled to provide the voltage required for RETENTION.

[0103] OFF State Rule: When all sub-power domains are in the OFF state, the system-level aggregated power state is in the OFF state. At this time, without the need for RAM to maintain the state, the PMM can completely shut down the LDO_CORE and DCDC_MEM that power the digital core, and only retain the PMMLDO that powers a very small number of always-on logics, thereby achieving the shutdown power level.

[0104] After determining the system-level aggregated power consumption state CHIP_PWR_STATE using the above method, the changes in CHIP_PWR_STATE can be tracked, and the timing control of all corresponding voltage regulators can be triggered according to the state changes to achieve precise management and optimization of system power consumption.

[0105] like Figure 6 As can be seen, aggregation greatly simplifies the direct control mapping relationship between the sub-power domain core and PMU resources, reduces control complexity, and enables each subsystem to adjust shared resources in real time according to actual needs. Thus, under the premise of meeting system performance, it optimizes the power consumption management of shared PMU resources and clock sources, minimizing power consumption.

[0106] It should be noted that using the maximum power consumption state among the received states of each sub-power domain as the aggregation rule for system-level aggregated power consumption state is only one specific implementation of power consumption state aggregation. Other aggregation rules can be designed according to different application scenarios and optimization goals.

[0107] In one embodiment, other aggregation rules can be those that maximize power efficiency while ensuring voltage meets functional safety requirements. Different subsystems vary significantly in size and load; by aggregating their power consumption states and expected loads, the optimal efficiency mode for PMU resources can be matched more precisely. Especially in applications with extremely high battery life requirements, such as TWS (True Wireless Stereo), the system can proactively switch to this aggregation strategy when low battery is detected to extend usage time and reduce overall energy consumption. For example, DC-DC converters support using PFM mode to improve efficiency under light loads and switching to PWM to ensure performance under heavy loads; LDOs also offer multiple modes, allowing them to enter a low-power state under low loads. While these switching methods are partially automated, combining them with subsystem requests and providing more precise efficiency demand trigger points through PMM aggregation logic will more effectively achieve optimized management of dynamic power supply modes.

[0108] In one embodiment, the system hardware power management module employs a more refined and flexible power management strategy. Specifically, each core may typically issue power requests to multiple power rails based on its own power consumption requirements, but not every sub-core will require all voltage regulators. For various resources shared by some heterogeneous sub-power domains, the system hardware power management module includes separate power consumption state aggregation modules for each sub-power domain. The main function of these modules is to calculate the state of the heterogeneous sub-power domains sharing corresponding resources according to preset aggregation rules, thereby deriving the aggregated power consumption state of the sub-power domains. This triggers the timing generators configured for the resources shared by the heterogeneous sub-power domains, achieving refined power optimization and demonstrating the flexibility and scalability of this aggregation mechanism.

[0109] When the system-level power state machine receives the system-level aggregated power state output from the system-level power state aggregation logic module, it immediately triggers the timing generators configured for the resources shared by all heterogeneous sub-power domains. When the system-level power state machine receives the partial sub-power domain power aggregated state output from the partial sub-power domain power state aggregation module, it triggers the timing generators configured for the resources shared by some heterogeneous sub-power domains. This hierarchical triggering mechanism enables the system to perform precise timing control on shared resources of different ranges of sub-power domains, further optimizing power management. Figure 8 Taking the case in the example, only the two sub-cores, CORE0 and CORE1, access the external flash memory, which requires the power supply LDO_FLASH to be enabled. CORE2, however, does not need to access the external flash memory. A clever approach can be used: duplicate a partial sub-power domain power consumption state aggregation module and mask the original CORE2 requests. The partial sub-power domain power consumption state aggregation module will always consider CORE2 to be in the OFF state.

[0110] Table 1: Power Consumption Status of Each Sub-Power Domain

[0111] LIGHTSLEEP 0.0v LIGHTSLEEP 0.0v ON 0.0v 0.0v CHIP_ON

[0112] As clearly shown in Table 1, although CORE2 is in the ON working state and the system's aggregated power consumption state is also CHIP_ON, the LDO_FLASH aggregation state is OFF because CORE2 does not access the external flash memory, and therefore can be turned off. This operation not only eliminates the leakage power consumption of the FLASH in the IDLE state but also reduces the leakage of the LDO_FLASH itself, thus achieving a refined power consumption optimization goal. At the same time, this case fully demonstrates the flexible and scalable nature of this aggregation mechanism, enabling flexible adjustment and optimization according to different system requirements and resource usage.

[0113] Based on the above heterogeneous multi-core chip power state control system architecture, sub-power domain sleep / wake management can be achieved through the heterogeneous multi-core chip power state control system. The specific implementation method is as follows:

[0114] In one embodiment, the system-level general wake-up source supports flexible configuration mapping, and can be set to wake up only one or more specific sub-power domains. Taking a GPIO wake-up event as an example, it can be configured to wake up only the CORE0 sub-power domain. When this GPIO wake-up event occurs, the system wake-up source mapping module generates a CORE0 sub-power domain wake-up request signal, while the CORE1 and CORE2 sub-power domains remain in deep sleep, avoiding unnecessary global wake-ups and significantly reducing power consumption during the wake-up process.

[0115] like Figure 9 The system hardware power consumption management module also includes: a system wake-up source mapping module and a power-on sequence arbitrator;

[0116] The system wake-up source mapping module receives the wake-up signal from the corresponding system wake-up source when a wake-up event occurs. It then matches the heterogeneous sub-power domains mapped to be woken up by the system wake-up source to generate corresponding sub-power domain wake-up request signals. Once any sub-power domain wake-up request signal is generated, the system wake-up source mapping module activates it, forming a system-level wake-up request. This request serves as the trigger signal for the system-level power state machine state transition, driving the system to transition from various sleep states to working states, ensuring the system can respond to external events promptly.

[0117] The power-on sequence arbitrator is responsible for receiving wake-up request signals from each sub-power domain and arbitrating them according to preset rules to determine the power-on sequence of each sub-power domain. During the entire chip power-on process, the PMM also uses the arbitrator to ensure that each sub-power domain is powered on in sequence, further suppressing the impact of chip-level inrush current. After the power-on sequence arbitrator, when different cores simultaneously initiate wake-up requests, the actual power-on sequence of the different cores is staggered. This minimizes the potential impact of excessive inrush current during the power-on process from the system control level, as shown in Figure 10.

[0118] In one embodiment, when waking from deep sleep or during a cold start, simultaneously powering on a large number of memories (such as RAM and ROM) can generate a huge inrush current. This inrush current can interfere with the power supply of other sub-power domains on the same system power rail, and in severe cases, may even cause logic errors, leading to system malfunction. The Power Management Controller (PMM) maintains a set of power consumption states and power-on sequences for all RAM and ROM macrocells within a sub-power domain. When the sub-power domain needs to wake up from a power-off state, the PMM's internal sequencer will sequentially turn on the power switches (PGEN / RET signals) of each RAM / ROM cell at very short time intervals (e.g., a few high-speed clock cycles) according to a preset order, allowing these cells to return from a power-off or state-holding state to a power-on state. In this way, the inrush current is dispersed over a period of time, effectively avoiding instantaneous current peaks and ensuring power supply stability. Moreover, this sequence and interval can be flexibly configured through registers.

[0119] In one embodiment, such as Figure 9 When a system wake-up source (such as an external interrupt, timer timeout, etc.) generates a wake-up signal, the system wake-up source mapping module accurately locates the sub-power domain corresponding to the wake-up source according to the pre-set mapping configuration. The system wake-up source mapping module immediately generates a sub-power domain wake-up request signal for the corresponding sub-power domain. As soon as any subsystem wake-up request signal is generated, the system-level wake-up request is immediately initiated.

[0120] After receiving a system-level wake-up request, the system-level power state machine drives the system to transition to the working state strictly according to preset logic, based on the current sleep state (light sleep, deep sleep, etc.). The transition between different sleep states triggers a series of timing generator operation sequences targeting XTAL (crystal oscillator) and PMU (power management unit) resources.

[0121] The timing generator sequence generates PMU control pulses according to a precise time plan and order, and sends them to the power management module. These pulses precisely control the power management module to provide appropriate voltage and current to various resources, gradually restoring resources such as XTAL and PMU to normal operating conditions. When the timing generator sequence completes all preset operations, the system sleep state machine jumps to normal operating state and sets the "PMU power restoration complete" signal, indicating that the system's power supply, clock, and other basic resources are ready.

[0122] After receiving the "PMU power restoration complete" signal, the power-on sequence arbitrator begins receiving wake-up request signals from each sub-power domain. It processes these requests according to preset arbitration rules. If parallel wake-up requests exist, meaning multiple sub-power domains simultaneously issue power-on requests, the arbitrator will strictly grant the wake-up requests of each sub-power domain in sequence according to the order. This orderly power-on arrangement effectively prevents inrush current problems caused by multiple sub-power domains powering on simultaneously, ensuring the stability and reliability of the power system.

[0123] Once all awakened subsystems have completed their power-on operations according to the power-on sequence determined by arbitration, the entire system successfully enters normal operating status. At this point, the circuit modules corresponding to each sub-power domain operate stably, the processor core executes instructions efficiently, the memory modules read and write data quickly, the peripheral interfaces communicate normally with external devices, and the system can process various tasks and data normally.

[0124] like Figure 11 This illustration shows a structural schematic of a heterogeneous multi-core chip according to an embodiment of the present invention. The chip includes: a heterogeneous multi-core chip power consumption state control system as described in the above embodiment, comprising:

[0125] Multiple heterogeneous sub-power domains;

[0126] The system hardware power management module is located in the normally open power domain of the chip. It is used to receive power status requests from each sub-power domain, send drive signals to the corresponding sub-power domain according to the preset hardware timing to make the corresponding sub-power domain enter the target state, and generate PMU control signals.

[0127] The power management module contains multiple voltage regulators, which are used to drive the corresponding voltage regulators to perform corresponding regulation operations according to the PMU control signals.

[0128] Since the implementation principle of the heterogeneous multi-core chip power state control system has been described in the previous embodiments, it will not be repeated here.

[0129] The heterogeneous multi-core chip power consumption state control system provided in this embodiment of the invention can be implemented on the terminal side or the server side. For the hardware structure of the electronic terminal, please refer to [link to relevant documentation]. Figure 12This is a schematic diagram of an optional hardware structure of an electronic terminal 1000 provided in an embodiment of the present invention. The terminal 1000 can be a mobile phone, computer device, tablet device, personal digital processing device, factory back-end processing device, etc. The terminal 1000 includes: at least one processor 1001, a memory 1002, at least one network interface 10010, and a user interface 1009. The various components in the device are coupled together through a bus system 1005. It is understood that the bus system 1005 is used to realize the connection and communication between these components. In addition to a data bus, the bus system 1005 also includes a power bus, a control bus, and a status signal bus. However, for clarity, in... Figure 12 The general will label all buses as bus systems.

[0130] The user interface 1009 may include a monitor, keyboard, mouse, trackball, clicker, button, touchpad, or touch screen.

[0131] It is understood that memory 1002 can be volatile memory or non-volatile memory, or both. Non-volatile memory can be read-only memory (ROM) or programmable read-only memory (PROM), which serves as an external cache. By way of example, but not limitation, many forms of RAM are available, such as static random access memory (SRAM) and synchronous static random access memory (SSRAM). The memories described in the embodiments of this invention are intended to include, but are not limited to, these and any other suitable categories of memory.

[0132] In this embodiment of the invention, the memory 1002 is used to store various types of data to support the operation of the terminal 1000. Examples of this data include: any executable program for operation on the terminal 1000, such as the operating system 10021 and application programs 10022; the operating system 10021 contains various system programs, such as the framework layer, core library layer, driver layer, etc., for implementing various basic services and handling hardware-based tasks. The application program 10022 may contain various applications, such as a media player, browser, etc., for implementing various application services. The heterogeneous multi-core chip power consumption state control system provided in this embodiment of the invention can be included in the application program 10022.

[0133] The methods disclosed in the above embodiments of the present invention can be applied to or implemented by the processor 1001. The processor 1001 may be an integrated circuit chip with signal processing capabilities. In the implementation process, each step of the above method can be completed by the integrated logic circuit of the hardware in the processor 1001 or by instructions in the form of software. The processor 1001 may be a general-purpose processor, a digital signal processor (DSP), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The processor 1001 can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of the present invention. The general-purpose processor 1001 may be a microprocessor or any conventional processor, etc. The steps of the accessory optimization method provided in the embodiments of the present invention can be directly reflected as being executed by a hardware decoding processor, or being executed by a combination of hardware and software modules in the decoding processor. The software module may be located in a storage medium, which is located in a memory. The processor reads the information in the memory and combines it with its hardware to complete the steps of the aforementioned method.

[0134] In an exemplary embodiment, the terminal 1000 may be used to execute the aforementioned method by one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), or complex programmable logic devices (CPLDs).

[0135] Those skilled in the art will understand that all or part of the steps of the above-described method embodiments can be implemented using computer program-related hardware. The aforementioned computer program can be stored in a computer-readable storage medium. When executed, the program performs the steps of the above-described method embodiments; and the aforementioned storage medium includes various media capable of storing program code, such as ROM, RAM, magnetic disks, or optical disks.

[0136] In the embodiments provided in this application, the computer-readable and writable storage medium may include read-only memory, random access memory, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, flash memory, USB flash drive, portable hard drive, or any other medium capable of storing desired program code in the form of instructions or data structures and accessible by a computer. Additionally, any connection may be appropriately referred to as a computer-readable medium. For example, if instructions are transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are included in the definition of medium. However, it should be understood that computer-readable and writable storage media and data storage media do not include connections, carrier waves, signals, or other transient media, but are intended for non-transient, tangible storage media. The disks and optical discs used in the application include compact optical discs (CDs), laser optical discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, where disks typically copy data magnetically, while optical discs use lasers to copy data optically.

[0137] The present invention has the following advantages over the prior art:

[0138] 1. This invention provides a hardware power management architecture that eliminates the need for a dedicated control processor (SCP). It employs a purely hardware-implemented power management module (PMM) to directly and precisely control the power consumption state of each sub-power domain in a heterogeneous multi-core SoC. Unlike traditional SCP solutions that rely on software processing and inevitably incur processing latency (often exceeding 100μs), this architecture, thanks to its efficient hardware operation, achieves a response time of less than 10μs, enabling rapid response to power management needs. Simultaneously, it significantly reduces the static power consumption of the power management module itself. In ultra-low power scenarios, such as when powered off, the system current can be less than 10μA, greatly meeting the requirements of low-power applications and providing strong support for the development of energy-efficient devices. This invention completely removes the power-intensive SCP and its related software, greatly simplifying system design and eliminating the need for software developers to write and maintain complex central power control code, thereby shortening the development cycle and reducing the risk of errors.

[0139] 2. The PMU built-in hardware logic of this invention collects power consumption status requests from multiple sub-power domains sharing the same power rail in real time. These requests cover various states such as ON, LIGHTSLEEP, DEEPSLEEP, and OFF. Based on preset aggregation rules, the hardware logic quickly generates system-level power consumption status. Based on this status, it drives the PMU resources for optimized adjustment, such as precise control of the voltage regulator and clock source. This decentralized power management logic achieves fine-grained control of shared resources, avoiding the coordination difficulties that may arise from centralized management. At the same time, it significantly improves the scalability of the system. When adding a subsystem, there is no need to modify the core logic, reducing the difficulty and cost of system upgrades and expansions.

[0140] 3. This invention equips each sub-power domain with an independent hardware power state machine (Power FSM), which autonomously initiates power state requests through dedicated interfaces (such as SLEEP_REQ and SLEEP_PWR_TYPE). Under the synergistic effect of the aggregation mechanism, the sequencer within the PMM precisely controls the power switches, clock gating, and isolation units according to a preset sequence. This distributed design avoids the performance bottlenecks that may arise from centralized processing. Each sub-power domain can process power state requests in parallel, resulting in faster response times. Moreover, it requires no complex software support, reducing the workload of software programming and debugging, simplifying system design complexity, and improving system development efficiency and reliability.

[0141] 4. This invention flexibly maps system-level wake-up sources (such as GPIO interrupts and RTC timers) to specific sub-power domains through hardware configuration, supporting on-demand wake-up. This flexible mapping mechanism avoids power waste caused by global wake-up and reduces unnecessary energy consumption. During the wake-up process, it effectively reduces energy consumption, adapting to the application needs of various scenarios, such as power-sensitive mobile devices and embedded systems, thus improving the system's energy utilization efficiency.

[0142] 5. The PMM of this invention incorporates an arbiter and a timing generator, activating sub-power domains or their internal memory units (such as RAM / ROM) one by one through a preset power-on sequence. During multi-core power-on, this orderly activation method allows the current to rise smoothly, avoiding inrush currents caused by simultaneous power-on. Compared with traditional solutions, this mechanism effectively suppresses voltage fluctuations, reduces damage to system hardware caused by voltage surges, improves system stability and reliability, ensures stable operation of the system under various working conditions, and reduces the risk of system failure.

[0143] In summary, the heterogeneous multi-core chip power consumption state control system and heterogeneous multi-core chip of the present invention receive power consumption state requests from each sub-power domain through a system hardware power management module. The module sends drive signals to the corresponding sub-power domains according to a preset hardware timing sequence to bring them into the target state and generates PMU control signals. The power management module then drives the internal voltage regulator to perform corresponding adjustment operations based on the PMU control signals. This invention eliminates the need for a dedicated control processor (SCP). The system hardware power management module, implemented entirely in hardware, directly controls the power consumption state of each sub-power domain in the heterogeneous multi-core SoC, eliminating software processing latency, providing fast response, and significantly reducing the static power consumption of the power management module itself. It is particularly suitable for ultra-low power consumption scenarios and achieves hardware-level surge current protection during multi-core power-up. Therefore, this invention effectively overcomes the various shortcomings of existing technologies and has high industrial application value.

[0144] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the invention. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in the present invention should still be covered by the claims of the present invention.

Claims

1. A heterogeneous multi-core chip power state control system, comprising: The system includes: Multiple heterogeneous sub-power domains; The system hardware power management module is located in the normally open power domain of the chip. It is used to receive power status requests from each sub-power domain, send drive signals to the corresponding sub-power domain according to the preset hardware timing to make the corresponding sub-power domain enter the target state, and generate PMU control signals. The power management module contains multiple voltage regulators, which are used to drive the corresponding voltage regulators to perform corresponding regulation operations according to the PMU control signals. The system hardware power consumption management module includes: a sub-power domain power consumption state machine set for each sub-power domain, a system-level power consumption state aggregation logic module, a system-level power consumption state machine, and multiple timing generators equipped for different shared resources of each sub-power domain. Each sub-power domain power state machine is used to receive power state requests from each sub-power domain and send drive signals to the corresponding sub-power domain according to a preset hardware timing sequence to make the corresponding sub-power domain enter the target state; the states of the sub-power domain power state machine include: off state, deep sleep state, light sleep state, and normal working state. The system-level power consumption state aggregation logic module is used to calculate the system-level aggregated power consumption state based on the state output by the power consumption state machine of each sub-power domain according to the preset aggregation rules. A system-level power state machine is used to record the current system-level power state and trigger the corresponding timing generator; Each timing generator, when triggered, generates a precise timing PMU control signal to be sent to the power management module.

2. The heterogeneous multi-core chip power state control system of claim 1, wherein, Each sub-power domain includes: a sub-power domain functional module and a sub-power domain low-power control interface unit; wherein, the sub-power domain functional module includes: a core processor, a direct memory access controller, on-chip memory, specific IP functional modules, and a clock / reset management module; the sub-power domain low-power control interface unit provides a physical control interface between the sub-power domain and the system hardware power management module, including: a power switch enabled by the system hardware power management module, an isolation unit, a clock / reset control interface unit, and a memory power consumption control interface unit.

3. The heterogeneous multi-core chip power consumption state control system according to claim 1, characterized in that, The sub-power domain power consumption state machine includes: The sub-power domain logic power consumption control state machine is used to start transitioning when a power consumption state request is received from the corresponding sub-power domain. The state machine sends one or more of the enable signals of the isolation unit and the clock / reset control unit to the corresponding sub-power domain according to the preset hardware timing. The sub-power domain memory power control state machine is used to start transitioning when a power status request from the corresponding sub-power domain is received. It sends an enable signal to the memory power control unit to control the power status of all memory cells within the heterogeneous sub-power domain.

4. The heterogeneous multi-core chip power consumption state control system according to claim 1, characterized in that, When each sub-power domain power state machine receives a sleep request from the corresponding sub-power domain, the state machine begins to transition, sending drive signals to the corresponding sub-power domain according to a preset hardware timing sequence. This causes the corresponding sub-power domain to enter the target sleep state and outputs the corresponding state to the system-level power state aggregation logic module. The system-level power state aggregation logic module calculates the system-level aggregated power state based on the states output by each sub-power domain power state machine according to preset aggregation rules. The system-level power state machine receives the system-level aggregated power state and triggers the corresponding timing generator to generate a series of precisely timed control pulses, controlling the corresponding adjustment operations of the voltage regulator in the power management module.

5. The heterogeneous multi-core chip power consumption state control system according to claim 1, characterized in that, The system hardware power consumption management module also includes: a system wake-up source mapping module and a power-on sequence arbiter; The system wake-up source mapping module is used to receive the wake-up signal of the system wake-up source, match the heterogeneous sub-power domain configured to be woken up by the system wake-up source and generate the corresponding sub-power domain wake-up request signal, and form a system-level wake-up request. The power-on sequence arbitrator is used to receive wake-up request signals from each sub-power domain and arbitrate them to determine the power-on sequence, so that the power state machines of each sub-power domain send drive signals to the heterogeneous sub-power domains in sequence to wake up the corresponding sub-power domains.

6. The heterogeneous multi-core chip power consumption state control system according to claim 1, characterized in that, When the system wake-up source mapping module receives the wake-up signal from the system wake-up source, it matches the heterogeneous sub-power domain configured for wake-up by the system wake-up source and generates a corresponding sub-power domain wake-up request signal. It then forms a system-level wake-up request and sends it to the system-level power state machine. When the system-level power state machine receives the system-level wake-up request, it drives the current system-level power state to jump from the corresponding sleep state to the normal working state. It triggers the timing generator to generate a precisely timed PMU control pulse and sends it to the power management module, causing each resource to fall back to the normal working state. After that, the system-level power state machine jumps to the normal working state and sets the PMU power recovery complete signal. When the power-on sequence arbitrator receives the PMU power recovery complete signal, it starts to accept wake-up request signals from each sub-power domain, and makes arbitration to determine the power-on sequence, so that the power state machine of each sub-power domain controls each sub-power domain to power on in sequence.

7. The heterogeneous multi-core chip power consumption state control system according to claim 4, characterized in that, The aggregation rules include: taking the highest power consumption state among the received states of each sub-power domain as the system-level aggregated power consumption state; wherein, the states of heterogeneous sub-power domains are arranged in descending order of power consumption as: normal operation state, light sleep state, deep sleep state, and off state.

8. The heterogeneous multi-core chip power consumption state control system according to claim 1, characterized in that, In the system hardware power management module, a partial sub-power domain power status aggregation module is set up according to each resource shared by the partial heterogeneous sub-power domains. The power status aggregation of the partial sub-power domains is calculated according to the preset aggregation rules for the status of the heterogeneous sub-power domains sharing the corresponding resources. When the system-level power state machine receives the system-level aggregated power status output by the system-level power status aggregation logic module, the timing generators configured for the resources shared by all heterogeneous sub-power domains are triggered.

9. A heterogeneous multi-core chip, characterized in that, The chip includes: a heterogeneous multi-core chip power state control system as described in any one of claims 1 to 8.

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