arithmetic circuit
By integrating the arithmetic circuit design of floating-point division root remainder and integer division root remainder, the problem of high hardware cost of SRT algorithm is solved, and the circuit achieves low power consumption and high versatility.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- GUANGDONG LEAPFIVE TECH CO LTD
- Filing Date
- 2026-01-12
- Publication Date
- 2026-07-21
AI Technical Summary
In existing technologies, the SRT algorithm requires different circuits for floating-point operations and integer operations, resulting in high hardware costs.
An arithmetic circuit was designed, which integrates floating-point division with integer division by combining an input module, a floating-point conversion module, a calculation module, and an output module. This includes floating-point conversion, splitting, normalization, and SRT iterative operation, reducing the power consumption and area of the circuit.
This invention integrates the functions of floating-point division with integer division with root remainder, reducing hardware costs and improving the versatility and performance of the circuit.
Smart Images
Figure CN121501243B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of electronic technology, and more particularly to an operational circuit. Background Technology
[0002] The Sweeney-Robertson-Tocher (SRT) algorithm is a digital iterative algorithm based on subtraction. It iteratively obtains results of a certain width and then adds these results together to obtain the final result. However, when using the SRT algorithm for floating-point and integer arithmetic, each operation requires a separate SRT circuit, resulting in high hardware costs. Summary of the Invention
[0003] To address the shortcomings of existing technologies, this application provides an arithmetic circuit that integrates floating-point division with integer division, thereby reducing circuit power consumption and area, and lowering hardware costs.
[0004] To address the above problems, this application provides an operational circuit, which includes:
[0005] The input module is configured to output the initial operands;
[0006] A floating-point conversion module, the first end of which is connected to the input module;
[0007] The calculation module is connected at its first end to the floating-point conversion module and the input module, respectively.
[0008] The output module connects to the second end of the calculation module;
[0009] When the initial operand is an integer, the floating-point conversion module is configured to perform floating-point conversion on the initial operand to output the first operand; the calculation module is configured to perform division, modulo, or square root operations using the first operand.
[0010] When the initial operand is a floating-point number, the calculation module is configured to perform division, modulo, or square root operations using the initial operand.
[0011] The output module is configured to output the calculation results after the calculation module has completed its calculations.
[0012] In one embodiment, the computing circuit further includes a first splitting module;
[0013] The first end of the first splitting module is connected to the input module, and the second end of the first splitting module is connected to the first end of the floating-point conversion module and the input end of the calculation module, respectively.
[0014] When the initial operand is an integer, the first splitting module is configured to split the initial operand according to the bit width of the initial operand to obtain the second operand, and the floating-point conversion module is configured to perform floating-point conversion on the second operand to output the first operand;
[0015] When the initial operand is a floating-point number, the first splitting module is configured to split the initial operand according to the precision mode of the initial operand to output the third operand, and the calculation module is configured to perform division, modulo, or square root operations on the third operand.
[0016] In one embodiment, the first splitting module includes a bit splitting module and a bit output module;
[0017] The first end of the bit splitting module is connected to the first end of the input module and the first end of the floating-point conversion module, respectively; the second end of the bit splitting module is connected to the first end of the bit output module, and the second end of the bit output module is connected to the calculation module.
[0018] When the initial operand is an integer, the bit splitting module is configured to split the fourth operand into the precision mode of the fourth operand after floating-point conversion of the second operand to generate the first operand; the bit output module is configured to output the first operand according to the precision mode of the first operand.
[0019] When the initial operand is a floating-point number, the bit splitting module is configured to split the initial operand according to the precision mode of the initial operand to generate the third operand, and the bit output module is configured to output the third operand according to the precision mode of the third operand.
[0020] In one embodiment, the computing circuit further includes a second splitting module and a leading zero detection module;
[0021] Wherein, the first end of the second splitting module is connected to the second end of the first splitting module, the second end of the second splitting module is connected to the first end of the leading zero detection module, and the second end of the leading zero detection module is connected to the first end of the calculation module;
[0022] When the initial operand is a floating-point number, the second splitting module is configured to split the third operand to output the mantissa of the third operand, and the leading zero detection module is configured to perform leading zero detection on the mantissa of the third operand and output the leading zero detection result of the third operand to the calculation module.
[0023] In one embodiment, the calculation module includes a normalization module, a first selection module, and a first exponent calculation module;
[0024] The first end of the normalization module is connected to the second end of the leading zero detection module. The second end of the normalization module is connected to the first input end of the first selection module and the first end of the first exponent calculation module. The first end of the first exponent calculation module and the second input end of the first selection module are both connected to the second end of the second splitting module.
[0025] The normalization module is configured to normalize the mantissa of the third operand based on the leading zero detection result to generate the normalized mantissa of the third operand; the first selection module is configured to output the normalized mantissa input from the first input terminal or the second input terminal;
[0026] The first exponent calculation module is configured to perform division exponentiation or first-stage square root exponentiation on the exponent of the third operand based on the normalization result; or / and,
[0027] The first exponent calculation module is configured to perform a subtraction operation on the exponent of the first operand output by the first splitting module.
[0028] In one embodiment, the calculation module further includes a second exponent calculation module;
[0029] The second exponent calculation module is connected to the second end of the first exponent calculation module and is configured to perform a second-stage square root exponent calculation on the exponent of the third operand.
[0030] In one embodiment, the arithmetic circuit further includes a special floating-point detection module and a floating-point anomaly detection module;
[0031] Among them, the first end of the special floating-point detection module is connected to the second end of the first splitting module, and the second end of the special floating-point detection module is connected to the first end of the floating-point anomaly detection module and the first end of the first selection module respectively;
[0032] The special floating-point detection module is configured to perform special value detection on the third operand, output the first type of data to the floating-point anomaly detection module, and output the second type of data to the first selection module; the floating-point anomaly detection module is configured to perform anomaly detection on the first type of data.
[0033] In one embodiment, the calculation module further includes a second selection module and an SRT iteration module;
[0034] The first end of the second selection module is connected to the second end of the first splitting module and the second end of the first selection module, the second end of the second selection module is connected to the first end of the SRT iteration module, and the second end of the SRT iteration module is connected to the output module.
[0035] The second selection module is configured to output the mantissa of the first operand or the mantissa of the third operand to the SRT iteration module;
[0036] When the initial operand is an integer, the SRT iteration module is configured to perform division or modulo operations on the mantissa of the first operand within a preset first iteration number, or the SRT iteration module is configured to perform square root operations on the mantissa of the first operand.
[0037] When the initial operand is a floating-point number, the SRT iteration module is configured to perform division or square root operation on the mantissa of the third operand within a preset second iteration number, or the SRT iteration module is configured to perform modulo operation on the mantissa of the third operand.
[0038] In one embodiment, the first number of iterations is determined based on the bit width of the first operand, and the second number of iterations is determined based on the precision mode of the initial operand.
[0039] In one embodiment, the arithmetic circuit further includes an integer anomaly detection module;
[0040] The integer anomaly detection module is connected to the second end of the first splitting module and is configured to perform integer anomaly detection on the second operand.
[0041] The arithmetic circuit provided in this application includes an input module, a floating-point conversion module, a calculation module, and an output module. The input module is configured to output the initial operand. The first end of the floating-point conversion module is connected to the input module. The first end of the calculation module is connected to both the floating-point conversion module and the input module. The output module is connected to the second end of the calculation module. When the initial operand is an integer, the floating-point conversion module is configured to perform floating-point conversion on the initial operand to output the first operand. The calculation module is configured to perform division, remainder, or square root operations using the first operand. When the initial operand is a floating-point number, the calculation module is configured to perform division, remainder, or square root operations using the initial operand. Simultaneously, the output module is configured to output the calculation result after the calculation module has completed its calculation. This integrates the functions of floating-point division with remainder and integer division with remainder, which not only reduces the power consumption and area of the circuit and lowers the hardware cost, but also improves the versatility and performance of the circuit. Attached Figure Description
[0042] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0043] Figure 1 An architectural diagram of the SRT operation circuit provided in an embodiment of this application;
[0044] Figure 2 This is a first schematic block diagram of the SRT operation circuit provided in an embodiment of this application;
[0045] Figure 3 This is a second schematic block diagram of the SRT operation circuit provided in an embodiment of this application. Detailed Implementation
[0046] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.
[0047] It should be understood that, when used in this specification and the appended claims, the terms "comprising" and "including" indicate the presence of the described features, integrals, steps, operations, elements and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or collections thereof.
[0048] It should also be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the scope of the application. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.
[0049] It should also be further understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.
[0050] Furthermore, in this application, unless otherwise explicitly specified or limited in the embodiments, the terms "installation," "connection," "joining," and "fixing" appearing in the embodiments should be interpreted broadly. For example, a connection can be a fixed connection, a detachable connection, or an integral part; it can also be a mechanical connection, an electrical connection, etc. Of course, it can also be a direct connection, or an indirect connection through an intermediate medium, or it can be the internal communication between two components, or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application based on the specific implementation.
[0051] The SRT algorithm is a high-speed digital recursive division algorithm that significantly reduces the number of iterations through redundant number representation and normalization techniques. It is widely used in the design of modern processors and hardware dividers.
[0052] Currently, there are three main factors affecting the performance of the SRT algorithm: the choice of radix, the quotient selection function, and the expression for the partial remainder. The choice of radix determines the number of digits in the result obtained in each loop; the more digits in the result, the fewer loops are required. The SRT algorithm first selects the quotient using a partial dividend and divisor, then subtracts the product of the dividend, divisor, and quotient to obtain the remainder, and finally shifts the remainder to the left.
[0053] The formula for implementing division using the SRT algorithm can be:
[0054]
[0055] Where x is the dividend, d is the divisor, w[j+1] is the partial remainder obtained after the j-th iteration, r is the radix of the SRT algorithm, and q j+1 Let be the quotient obtained in the j-th iteration.
[0056] The steps for implementing division in the SRT algorithm are as follows:
[0057] Step 1: Let the number of iterations be j. Shift the remainders obtained from each iteration to obtain the shifted remainder rw[j].
[0058] Step 2: Select the quotient of the current loop based on the partial remainder and divisor. The quotient selection function must satisfy -d. <w[j]<d;
[0059] Step 3: Multiply the quotient and divisor obtained in the current loop;
[0060] Step 4: Subtract the product of the remainder obtained from the shift from the product of the remainder obtained in Step 3 to obtain the remainder w[j+1] for the next loop, and so on, until the loop ends.
[0061] The formula for the square root operation in the SRT algorithm can be:
[0062]
[0063] Where rw[j] is the partial remainder after shifting, s j+1 Sum[j] is the result obtained in each loop (corresponding to the redundant number set), and Sum[j] is the sum of all results after the loop is completed.
[0064] The steps for implementing the square root operation using the SRT algorithm are as follows:
[0065] Step 1: Let the number of iterations be j. Shift the remainders obtained from the iterations to get the shifted remainders.
[0066] Step 2: Select the root of the current cycle based on the remainder after shifting and the radicand.
[0067] Step 3: Calculate 2Sum[j]*Sj+1 and S2j+1*r - (j+1) using Sj+1, the sum of the first j square roots Sum[j], and the number of iterations j+1.
[0068] Step 4: Partial remainder after shifting, sum of loop results, and Perform addition to obtain the partial remainder w[j+1] for the next loop, and so on.
[0069] However, when using the SRT algorithm for floating-point and integer operations, each operation requires a separate SRT circuit, resulting in higher hardware costs.
[0070] To address this, this application provides an arithmetic circuit comprising an input module, a floating-point conversion module, a calculation module, and an output module. The input module is configured to output an initial operand. The first terminal of the floating-point conversion module is connected to the input module. The first terminal of the calculation module is connected to both the floating-point conversion module and the input module. The output module is connected to the second terminal of the calculation module. When the initial operand is an integer, the floating-point conversion module is configured to perform a floating-point conversion on the initial operand to output a first operand. The calculation module is configured to perform division or modulo operations using the first operand. When the initial operand is a floating-point number, the calculation module is configured to perform division or square root operations using the initial operand. Simultaneously, the output module is configured to output the calculation result after the calculation module has completed its calculation. This integrates the functions of floating-point division square root and integer division modulo, reducing circuit power consumption and area, lowering hardware costs, and improving the circuit's versatility and performance.
[0071] Please see Figure 1 , Figure 1 This is an architectural diagram of the SRT operation circuit provided in an embodiment of this application. The SRT operation circuit can be located between the instruction word scheduling module or decoding module and the result write-back module. At least four SRT operation circuits can be set between the instruction word scheduling module or decoding module and the result write-back module. Each of the four SRT operation circuits corresponds to an SRT iteration module, which are represented by srt1, srt2, srt3 and srt4 respectively. Each SRT iteration module can input single-precision (SP32) floating-point numbers, double-precision (DP) floating-point numbers, int8 integers, int16 integers, int32 integers and int64 integers.
[0072] The SRT arithmetic circuit can perform floating-point and integer division and root operations. For floating-point and integer (vector) division and root instructions, the SRT arithmetic circuit supports single-precision (SP32) and double-precision (DP) floating-point operations as specified by the IEEE 754 standard. For vector instructions, the SRT arithmetic circuit supports 8-bit, 16-bit, 32-bit, and 64-bit. Specifically, it divides the instructions into two main categories: floating-point and vector. Floating-point instructions include single-precision (SP32) and double-precision (DP) floating-point division and root instructions. Vector instructions are divided into vector floating-point and vector fixed-point instructions. Vector floating-point instructions include single- and double-precision floating-point division, root, reciprocal, and square root reciprocal instructions. Vector fixed-point instructions include integer division and remainder instructions. The SRT arithmetic circuit supports 18 instructions.
[0073] In this application, floating-point numbers fully comply with the IEEE 754 standard and support both single-precision (32-bit, SP32) and double-precision (64-bit, DP) formats; integers (vectors) are suitable for integer operations of vector instructions and support four widths: 8-bit, 16-bit, 32-bit, and 64-bit.
[0074] like Figure 2 As shown, this application provides an operational circuit, which includes:
[0075] Input module 110 is configured to output initial operands;
[0076] Floating-point conversion module 120, the first end of floating-point conversion module 120 is connected to input module 110;
[0077] The first end of the calculation module 130 is connected to the floating-point conversion module 120 and the input module 110 respectively.
[0078] Output module 140 is connected to the second end of calculation module 130;
[0079] When the initial operand is an integer, the floating-point conversion module 120 is configured to perform floating-point conversion on the initial operand to output the first operand; the calculation module 130 is configured to perform division, modulo, or square root operations using the first operand.
[0080] When the initial operand is a floating-point number, the calculation module 130 is configured to perform division, modulo, or square root operations using the initial operand.
[0081] Output module 140 is configured to output the calculation results after the calculation module 130 has completed the calculation.
[0082] In this application, the SRT arithmetic circuit can perform integer division, modulo operation, or square root operation without the Riscv instruction configured, and it can also perform floating-point division, square root operation, or modulo operation.
[0083] For details, please refer to Figure 2 and Figure 3 The initial operands can be understood as operand opa (256 bits) and operand opb (256 bits). Input module 110 is configured to output operand opa (256 bits) and operand opb (256 bits) based on the Riscv instruction. If operand opa (256 bits) and operand opb (256 bits) are integers, floating-point conversion module 120 can perform floating-point conversion on operand opa (256 bits) and operand opb (256 bits), while simultaneously calculating... The calculation module 130 uses the SRT algorithm to perform division or modulo operations on the two converted operands (the first operand), and outputs the calculation result through the output module 140. If operands opa (256 bits) and opb (256 bits) are floating-point numbers, the calculation module 130 uses the SRT algorithm to perform division or square root operations on operands opa (256 bits) and opb (256 bits), and outputs the calculation result through the output module 140. The calculation result can be an integer result or a floating-point result.
[0084] It should be noted that the SRT algorithm can be divided into SRT4 algorithm, SRT8 algorithm and SRT16 algorithm. When the calculation module 130 uses the SRT algorithm to perform operations on operands in integer or floating-point format, since the width of the processor's arithmetic unit is usually only 32 bits, 64 bits or 128 bits, the two operands are usually split. The splitting method can be selected according to the actual application, and this application does not make specific limitations.
[0085] Additionally, it should be noted that when implementing the SRT algorithm using the Riscv instruction in this application, division and modulo operations can be performed on integers, but not on square root operations; for floating-point numbers, division and square root operations can be performed, but not on modulo operations.
[0086] In this embodiment, during the process of converting the initial operand from an integer to a floating-point number, the floating-point conversion module 120 splits the initial operand into an exponent exp and a fraction frac. At the same time, it also needs to change the dividend in the initial operand to the format of 0.xxxx, and in special cases to the format of 1.xxxx. The divisor is then changed to the format of 1.xxxx.
[0087] In one embodiment, the arithmetic circuit further includes a first splitting module; wherein, the first end of the first splitting module is connected to the input module 110, and the second end of the first splitting module is connected to the first end of the floating-point conversion module 120 and the input end of the calculation module 130 respectively; when the initial operand is an integer, the first splitting module is configured to split the initial operand according to the bit width of the initial operand to obtain a second operand, and the floating-point conversion module 120 is configured to perform floating-point conversion on the second operand to output the first operand; when the initial operand is a floating-point number, the first splitting module is configured to split the initial operand according to the precision mode of the initial operand to output a third operand, and the calculation module 130 is configured to perform division, modulo, or square root operations on the third operand.
[0088] Specifically, when the initial operands are integers, they can be split according to int8 / 16 / 32 / 64. For int64, it is split into 4 data streams for parallel processing; for int32, it is split into 8 data streams, processing the highest 4 data streams first, and then processing the remaining 4 data streams; for int16, it is split into 16 data streams, divided into 4 groups of 4 data streams, processed in 4 steps, and processed in 4 steps; for int8, it is split into 32 data streams, divided into 8 groups of 4 data streams, processed in 8 steps, and processed in 8 steps.
[0089] When the initial operand is a floating-point number, it can be split according to the precision mode of the initial operand (DP mode and SP32 mode). For floating-point data in DP mode, it is split into 4 data streams for parallel processing; for floating-point data in SP32 mode, it is split into 8 data streams, and the higher 4 data streams are processed first, followed by the remaining 4 data streams.
[0090] It should be noted that, as Figure 3 As shown, when the initial operation data is 256 bits, it can be split into 128 bits first, and then the floating-point splitting mode or the integer splitting mode can be executed.
[0091] In this application, the third operand can be understood as two operands that have already been split and can be directly divided or square rooted.
[0092] In one embodiment, the first splitting module includes a bit splitting module and a bit output module; wherein, the first end of the bit splitting module is connected to the first end of the input module 110 and the first end of the floating-point conversion module 120 respectively, the second end of the bit splitting module is connected to the first end of the bit output module respectively, and the second end of the bit output module is connected to the calculation module 130; when the initial operand is an integer, the bit splitting module is configured to split the fourth operand according to the precision mode of the fourth operand after floating-point conversion of the second operand to generate the first operand; the bit output module is configured to output the first operand according to the precision mode of the first operand; when the initial operand is a floating-point number, the bit splitting module is configured to split the initial operand according to the precision mode of the initial operand to generate the third operand, and the bit output module is configured to output the third operand according to the precision mode of the third operand.
[0093] In this application, the bit splitting module can be understood as a module that splits the high-order and low-order bits of the operand to extract the high-order data in the operand. For example, if the operand consists of operand a_operand (128 bits) and operand b_operand (128 bits), the bit splitting module can split the high-order and low-order bits of operand a_operand (128 bits) and operand b_operand (128 bits). In DP mode, it can output the high 64 bits or low 64 bits of a_operand (128 bits) and b_operand (128 bits) to obtain the first operand or the third operand. In SP32 mode, it splits the high 64 bits or low 64 bits of a_operand (128 bits) and b_operand (128 bits) into two 32-bit data and outputs them to obtain the first operand or the third operand.
[0094] Simultaneously, when the first or third operand is input into the calculation module 130 for calculation, a bit output module is also required for output. The bit output module can be... Figure 3 The values are represented by unpack_high_doublewrod or unpack_low_doublewrod.
[0095] Specifically, in the process of using the bit output module to output the first operand or the third operand, the bit output module is configured to output the first operand according to the precision mode of the first operand or to output the third operand according to the precision mode of the third operand.
[0096] For example, when the bit output module is Figure 3The `unpack_high_doublewrod` module in the code can output the high 64 bits of `a_operand` (128 bits) and `b_operand` (128 bits) in DP mode; in SP32 mode, the high 64 bits of `a_operand` (128 bits) and `b_operand` (128 bits) are split into two 32-bit data sets for output; when the high 64 bits of the high 64 bits are... Figure 3 When unpacking low-doublewrod in DP mode, the lower 64 bits of a_operand and b_operand (128 bits) are output; in SP32 mode, the lower 64 bits of a_operand and b_operand are split into two 32-bit data for output.
[0097] In one embodiment, the arithmetic circuit further includes a second splitting module and a leading zero detection module; wherein, the first end of the second splitting module is connected to the second end of the first splitting module, the second end of the second splitting module is connected to the first end of the leading zero detection module, and the second end of the leading zero detection module is connected to the first end of the calculation module 130; when the initial operand is a floating-point number, the second splitting module is configured to split the third operand to output the mantissa of the third operand, and the leading zero detection module is configured to perform leading zero detection on the mantissa of the third operand and output the leading zero detection result of the third operand to the calculation module 130.
[0098] In this embodiment, the second splitting module can be understood as further splitting the third operand to output the mantissa of the third operand. The second splitting module can employ... Figure 3 The split32 / 64 representation in the code allows the second splitting module to input the denormalized mantissa of the third operand, denorm_mantissa, into the leading zero detection module lzd to detect the leading zeros of the mantissa of the third operand.
[0099] It should be noted that, since converting integers (8 / 16 / 32 / 64 bits) to IEEE-754 floating-point numbers does not produce denormalized numbers under normal implementation, the floating-point numbers converted from integers do not need to be checked for leading zeros.
[0100] In one embodiment, the calculation module 130 includes a normalization module, a first selection module, and a first exponent calculation module; wherein, the first end of the normalization module is connected to the second end of the leading zero detection module, the second end of the normalization module is connected to the first input end of the first selection module and the first end of the first exponent calculation module, and the first end of the first exponent calculation module and the second input end of the first selection module are both connected to the second end of the second splitting module; the normalization module is configured to normalize the mantissa of the third operand according to the leading zero detection result to generate a normalized result of the mantissa of the third operand; the first selection module is configured to output the normalized mantissa input from the first input end or the second input end; the first exponent calculation module is configured to perform a division exponent operation or a first-stage square root exponent operation on the exponent of the third operand according to the normalization result; or / and, the first exponent calculation module is configured to perform a subtraction operation on the exponent of the first operand output by the first splitting module.
[0101] In this application, the leading zero detection result of the mantissa of the third operand and the mantissa of the third operand can be input into the normalization module for mantissa shifting processing to obtain the shifted mantissas fm_a_srt0_in and fm_b_srt0_in respectively. This allows the mantissa of the third operand to be in the form of 1.xxx… Simultaneously, the format of the operand needs to be processed according to the specific operation type to facilitate iterative calculation. The mantissa of division is in the interval [1.0, 2.0), and the mantissa of square root is in the interval [1 / 4, 1), thus achieving normalization processing of the mantissa of the third operand, thereby obtaining the normalized mantissa result of the third operand. The normalization result includes the normalized mantissa of the third operand and the mantissa shift amount.
[0102] The second splitting module can input the normalized mantissa of the third operand into the first input terminal of the first selection module. The normalization module can input the normalized mantissa of the third operand in the normalization process into the second input terminal of the first selection module. At the same time, the normalization module can also input the mantissa shift amount in the normalization process into the first exponent calculation module, so that the exponent calculation module 130 can know how much the normalization module shifted the mantissa of the third operand, so as to correctly calculate the final exponent value.
[0103] The first index calculation module can adopt... Figure 3 The expression "exp calculate" is used to represent this. When the first exponent calculation module performs exponent calculation, if it calculates the third operand, it can perform division exponent operation or first-stage square root exponent operation on the exponent of the third operand based on the mantissa displacement in the normalization result.
[0104] The formula for division by exponentiation is:
[0105] Fe_out=(Ea-clza)- (Eb-clzb)+E0=Ea-clza+E0-Eb+clzb
[0106] In this context, Fe_out represents the result of the division exponentiation operation, Ea represents the exponent of operand 'a', clza represents the number of leading zeros in the mantissa of operand 'a', Eb represents the exponent of operand 'b', clzb represents the number of leading zeros in the mantissa of operand 'b', and E0 represents the exponent bias value. When the operand is of data type sp32, E0 = 127; when the operand is of data type dp / sp64, E0 = 1023. For division operations, 'a' divided by 'b', the exponentiation operation between 'a' and 'b' is subtraction.
[0107] The formula for calculating the exponent root is:
[0108] Fe_out=((Eb-clzb)-E0) / 2 + E0 = ((Eb-clzb)+E0) / 2
[0109] Where Fe_out represents the result of the exponentiation operation, Eb represents the exponent of operand b, clzb represents the number of leading zeros in the mantissa of operand b, and E0 represents the bias value of the exponent. When the operand is of sp32 data type, E0=127; when the operand is of dp / sp64 data type, E0=1023. It should be noted that the reason for dividing by 2 in the above formula is that the exponent of the operand being extracted needs to be divided by 2.
[0110] It should be noted that the first exponent calculation module only performs half of the calculation process during the square root exponent calculation, namely the first stage of square root exponent calculation. The other half of the process (the second stage) can be moved to the output module 140.
[0111] Meanwhile, during the exponent calculation process, if the first operand of an integer is being calculated, the first exponent calculation module can perform a subtraction operation on the exponent of the first operand output by the first splitting module. That is, the exponents of the dividend and the divisor are subtracted in the first exponent calculation module, and the decimal parts of the dividend and the divisor are input into the SRT iteration module.
[0112] In one embodiment, the calculation module 130 further includes a second exponent calculation module; wherein the second exponent calculation module is connected to the second end of the first exponent calculation module and is configured to perform a second-stage square root exponent operation on the exponent of the third operand.
[0113] In this application, the second index calculation module can adopt... Figure 3The expression exp calculate: square root, exp / 2 can be understood as the second stage of square root operation. The second exponent calculation module can be set in the output module 140, and the output module 140 can be set with a post-processing module. The second exponent calculation module can be part of the post-processing module.
[0114] In one embodiment, the arithmetic circuit further includes a special floating-point detection module and a floating-point anomaly detection module; wherein, the first end of the special floating-point detection module is connected to the second end of the first splitting module, and the second end of the special floating-point detection module is connected to both the floating-point anomaly detection module and the first end of the first selection module; the special floating-point detection module is configured to perform special value detection on the third operand, output a first type of data to the floating-point anomaly detection module, and output a second type of data to the first selection module; the floating-point anomaly detection module is configured to perform anomaly detection on the first type of data.
[0115] In this application, the special floating-point detection module and the floating-point anomaly detection module can adopt... Figure 3 The `spcl32 / 64` and `exception` in the code indicate that the special floating-point detection module can detect the split floating-point numbers and perform special value detection to determine the data type. This data type can be `nan`, `inf`, `zero`, `denorm`, or `norm`. Specifically, the first type of data, such as floating-point numbers of type `nan`, `inf`, and `zero`, is sent to the floating-point exception detection module for exception detection. If it is a special value, a signal is sent to the state machine `fsm`. The second type of data, such as floating-point numbers of type `denorm` and `norm`, is input to the third input terminal of the first selection module through the first-level register. The third input terminal can be understood as the selection terminal of the first selection module.
[0116] In one embodiment, the calculation module 130 further includes a second selection module and an SRT iteration module; wherein, the first end of the second selection module is connected to the second end of the first splitting module and the second end of the first selection module, the second end of the second selection module is connected to the first end of the SRT iteration module, and the second end of the SRT iteration module is connected to the output module 140; the second selection module is configured to output the mantissa of the first operand or the mantissa of the third operand to the SRT iteration module; when the initial operand is an integer, the SRT iteration module is configured to perform division or remainder operation on the mantissa of the first operand within a preset first iteration number, or the SRT iteration module is configured to perform square root operation on the mantissa of the first operand; when the initial operand is a floating-point number, the SRT iteration module is configured to perform division or square root operation on the mantissa of the third operand within a preset second iteration number, or the SRT iteration module is configured to perform remainder operation on the mantissa of the third operand.
[0117] In this application, the second selection module can determine whether the initial operand is an integer (int) or a floating-point number (float) based on an instruction containing int / float input at its selection terminal. It then chooses to output either the mantissa of the third operand output from the second terminal of the first selection module or the mantissa of the first operand output from the second terminal of the first splitting module, to be input into the SRT iteration module for iterative computation. The SRT iteration module can employ... Figure 3 It can be represented by any one of srt1_iteration(64bit), srt2_iteration(64bit), srt3_iteration(64bit), and srt4_iteration(64bit).
[0118] Specifically, when the initial operand is an integer, the SRT iteration module can be configured to perform division or modulo operations on the mantissa of the first operand within a preset first iteration number.
[0119] The formula for the number of iterations in the division or modulo operation can be: ((lzB-lzA+1) / r)+1, where lzB is the leading zero of the divisor B, lzA is the leading zero of the dividend A, and r is the number of bits in the quotient obtained in each iteration. For example, in the srt4 algorithm, each iteration yields a quotient of 2 bits, so r is 2.
[0120] It should be noted that when the result of the formula is not an integer, the dividend needs to be converted to the format 1.xxxx, and the number of iterations is the integer part truncated from the decimal point. For example, 3.4 will result in 3 iterations, and the dividend needs to be converted to the format 1.xxxx. In a special case, if the calculated number of iterations is 1.5, then the number of iterations is 1.
[0121] When the initial operand is a floating-point number, the SRT iteration module can be configured to perform division or square root operations on the mantissa of the third operand within a preset second iteration number.
[0122] In the division operation instruction, the iterative logic continuously iterates the mantissas of operand a and operand b according to the SRT algorithm, and finally calculates the quotient of the mantissa of operand a divided by the mantissa of operand b; in the square root operation instruction, the iterative logic continuously iterates the mantissa of operand b according to the SRT4 algorithm, and finally calculates the square root of the mantissa of operand b.
[0123] Furthermore, the number of iterations in the SRT iteration module during the square root operation of the mantissa of the first operand can be selected according to the actual application, and this application does not impose specific limitations. Similarly, the number of iterations in the SRT iteration module during the modulo operation of the mantissa of the third operand can also be selected according to the actual application, and this application does not impose specific limitations.
[0124] In one embodiment, the first number of iterations is determined based on the bit width of the first operand, and the second number of iterations is determined based on the precision mode of the initial operand.
[0125] In this application, the number of first iterations can be determined based on the bit width of the first operand. The first operand can be understood as a single integer. For example, the number of iterations for an int64 integer is 1 to 33 times, the number of iterations for an int32 integer is 1 to 17 times, the number of iterations for an int16 integer is 1 to 9 times, and the number of iterations for an int8 integer is 1 to 5 times.
[0126] The number of iterations for division or modulo operations involving 4 int64 integers ranges from 1 to 33; the number of iterations for division or modulo operations involving 8 int32 integers (divided into 2 groups and iterated sequentially) ranges from 2 to 34; the number of iterations for division or modulo operations involving 16 int16 integers (divided into 4 groups and iterated sequentially) ranges from 4 to 36; and the number of iterations for division or modulo operations involving 32 int8 integers (divided into 8 groups and iterated sequentially) ranges from 8 to 40.
[0127] The number of iterations for the second iteration can be determined based on the precision mode of the initial operands. For example, the number of iterations for floating-point division in DP mode is 29, the number of iterations for floating-point division in SP32 mode is 14, the number of iterations for floating-point root operations in DP mode is 28, and the number of iterations for floating-point root operations in SP32 mode is 13.
[0128] The number of iterations for the floating-point division operation in the 4 DP modes is 29, the number of iterations for the floating-point division operation in the 8 SP32 modes is 28 (14*2), the number of iterations for the square root operation of the floating-point numbers in the 4 DP modes is 28, and the number of iterations for the square root operation of the floating-point numbers in the 8 SP32 modes is 26 (13*2).
[0129] In one embodiment, the arithmetic circuit further includes an integer anomaly detection module; wherein the integer anomaly detection module is connected to the second end of the first splitting module and is configured to perform integer anomaly detection on the second operand.
[0130] In this application, the integer anomaly detection module can adopt... Figure 3 The `int exception` parameter represents the integer exception. The integer exception detection module can perform special value detection on the split integer. If the split integer is a special value, a signal is sent to the state machine `fsm` and the iteration is stopped. If the dividend in the split integer is less than the divisor, no iteration is needed, the quotient is 0, and the remainder is the dividend. Other special cases are given in Table 2.
[0131] Table 2
[0132]
[0133] Here, ---- indicates that this situation does not exist; SEW represents the bit width of a single element of the vector. For example, in vector SP32, the element bit width is 32 bits. For Vdivu[vv / vx], the result of the processing in the model is -1. For unsigned numbers, -1 is -2^(XLEN-1) (all 1s). The result of inverting and adding 1 is -1 for signed numbers.
[0134] In one embodiment, the output module 140 includes a mantissa normalization module and a mantissa rounding module; wherein, the first end of the mantissa normalization module is connected to the second end of the calculation module 130, and the second end of the remainder recovery module and the second end of the mantissa normalization module are respectively connected to the first end of the mantissa rounding module; the mantissa normalization module is configured to normalize the mantissa of the division result or the mantissa of the square root result and output the normalized mantissa result, and the mantissa rounding module is configured to round the normalized mantissa result to output a floating-point result.
[0135] Specifically, in the process of rounding the division or square root result after the calculation by the calculation module 130 using the output module 140 and outputting the floating-point result, a mantissa normalization module and a mantissa rounding module can be set in the output module 140. That is, a post-processing function for the calculation result can be set in the output module 140. The mantissa normalization module can normalize the mantissa of the division result or the square root result and output the normalized mantissa result. The mantissa rounding module can round the normalized mantissa result to output the floating-point result. Thus, the output module 140 can realize the mantissa rounding of the division or square root result after the calculation by the calculation module 130 and output the floating-point result.
[0136] In this embodiment, the mantissa normalization module can adopt... Figure 3 The normalize frac in the calculation module 130 means that the mantissa (quotient) generated after the iteration is normalized by the mantissa normalization module, that is, left shift to eliminate leading zeros. For example, if the mantissa is 0.xxxx, then the mantissa is shifted one bit to the left to get the mantissa in the format of 1.xxxx.
[0137] In this application, the rounding module has the functions of both denormalized rounding and normalized rounding, and it can employ... Figure 3 The terms denorm:mantissa round and norm:mantissa round are used to represent this.
[0138] Specifically, in the process of performing denormalized or normalized rounding using the mantissa rounding module, if the initial normalization by the mantissa normalization module causes the exponent to fall below the minimum value, it indicates that the floating-point result will be a very small denormalized number. Therefore, this application needs to shift the mantissa one bit to the right (rather than left) so that the exponent is exactly equal to the minimum value (i.e., the boundary between normalization and denormalization). This can be achieved by using... Figure 3 The `Shift denorm: shift frac toright to make exp = 1` function in the code implements rounding to the shifted mantissa (where the implicit bit is 0, i.e., the mantissa is denormalized). If the exponent does not reach its minimum value, it indicates that the result is a normalized number, and therefore can be rounded. Figure 3 The `norm:mantissa round` directs standard rounding to the normalized mantissa.
[0139] Furthermore, after completing either denormalized or normalized rounding, if the exponent is within the normal range, the system can select to output either a normalized or denormalized result based on the exponent value, and output the normalized or denormalized result as a floating-point result. If the exponent is outside the normal range, i.e., the maximum or minimum range, the system outputs an overflow result or an underflow result, and the flags for special results (NV, DZ, OF, UF, and NX), overflow result, or underflow result are output as floating-point results. Here, an exponent outside the normal range can be understood as overflow or underflow.
[0140] In one embodiment, the output module 140 further includes a remainder recovery module and an integer conversion module; wherein, the first end of the remainder recovery module is connected to the calculation module 130, the second end of the remainder recovery module is connected to the first end of the mantissa rounding module and the first end of the integer conversion module, and the first end of the integer conversion module is connected to the second end of the mantissa normalization module; if the calculation module 130 is configured to perform remainder operation based on the SRT algorithm and using the first operand, the remainder recovery module is configured to perform remainder recovery on the remainder data after the calculation module 130 completes the remainder operation and output the floating-point remainder, the mantissa normalization module is configured to normalize the mantissa after the calculation module 130 completes the remainder operation and output the normalized mantissa result, and the integer conversion module is configured to output the integer result based on the normalized mantissa result, the floating-point remainder, and the exponent result after the calculation module 130 completes the exponent calculation.
[0141] Specifically, after performing a modulo operation based on the SRT algorithm on the first operand, the remainder recovery module restores the original remainder generated by the SRT calculation to ensure that it meets the mathematical definition of being non-negative and less than the divisor, and outputs the obtained compliant floating-point remainder to the integer conversion module. At the same time, the mantissa normalization module normalizes the mantissa obtained by the SRT calculation and sends the normalized mantissa result to the integer conversion module, finally generating and outputting an integer result, which is the integer remainder obtained after performing a modulo operation on the first operand.
[0142] In this embodiment, the remainder recovery module can employ... Figure 3 The "Recovery remainder" indicates that the remainder recovery module can be used to generate the paste bit for the recovered remainder portion to produce the final paste bit X. Simultaneously, the remainder recovery module is also used to select the quotient value, choosing the quotient value based on the sign of the recovered remainder. The value at port res_m0_srt0 is 1 more than that at port res_m1_srt0, which is used to correct for errors in the result. Additionally, the integer conversion module can employ... Figure 3 The `float recovery int` is used to represent this.
[0143] In one embodiment, when the initial operand is a floating-point number, the calculation module 130 is configured to perform division, square root, or remainder operations based on the SRT algorithm using the initial operand, and the output module 140 is configured to round the division, square root, or remainder results after the calculation is completed by the calculation module 130 and output the floating-point results.
[0144] Specifically, when dealing with floating-point operands, i.e., when the initial operand is a floating-point number, the calculation module 130 can perform division, square root, or remainder operations based on the SRT algorithm using the initial operand. The output module 140 can round the division, square root, or remainder result after the calculation by the calculation module 130 and output the floating-point result. The floating-point result can be a quotient or square root in floating-point form.
[0145] It should be noted that the output module 140 can convert floating-point or integer results into... Figure 3 The calculation results are output in the form of "calculate result". Floating-point results, in addition to containing the square root or quotient in floating-point form, also contain the corresponding sign bit and special result (special value); integer results, in addition to containing the square root, quotient, or remainder in integer form, also contain the corresponding sign bit and special result (special value, special result).
[0146] It should also be noted that the first and second terminals mentioned in this application can be understood as the input and output terminals of each module. The connection form of the input and output terminals of each module can be selected according to the actual application, and this application does not make any specific restrictions.
[0147] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any person skilled in the art can easily conceive of various equivalent modifications or substitutions within the technical scope disclosed in this application, and these modifications or substitutions should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.
Claims
1. An operational circuit, characterized in that, include: The input module is configured to output the initial operands; A floating-point conversion module, wherein the first end of the floating-point conversion module is connected to the input module; The calculation module is connected at its first end to the floating-point conversion module and the input module. The output module is connected to the second end of the computing module; Wherein, when the initial operand is an integer, the floating-point conversion module is configured to perform floating-point conversion on the initial operand to split it into floating-point numbers in exponential and decimal forms, and output it as the first operand; the calculation module is configured to perform division, modulo, or square root operations using the first operand; the mantissa of the first operand is not checked for leading zeros; When the initial operand is a floating-point number, the calculation module is configured to perform division, modulo, or square root operations using the initial operand, and the mantissa of the initial operand is checked for leading zeros. The output module is configured to output the calculation result after the calculation module has completed the calculation.
2. The operational circuit according to claim 1, characterized in that, It also includes the first splitting module; Wherein, the first end of the first splitting module is connected to the input module, and the second end of the first splitting module is connected to the first end of the floating-point conversion module and the input end of the calculation module, respectively; When the initial operand is an integer, the first splitting module is configured to split the initial operand according to the bit width of the initial operand to obtain the second operand, and the floating-point conversion module is configured to perform floating-point conversion on the second operand to output the first operand; When the initial operand is a floating-point number, the first splitting module is configured to split the initial operand according to the precision mode of the initial operand to output a third operand, and the calculation module is configured to perform division, modulo, or square root operations on the third operand.
3. The operational circuit according to claim 2, characterized in that, The first splitting module includes a bit splitting module and a bit output module; Wherein, the first end of the bit splitting module is connected to the first end of the input module and the first end of the floating-point conversion module respectively, the second end of the bit splitting module is connected to the first end of the bit output module respectively, and the second end of the bit output module is connected to the calculation module; When the initial operand is an integer, the bit splitting module is configured to split the fourth operand according to the precision mode of the fourth operand after floating-point conversion of the second operand to generate the first operand; the bit output module is configured to output the first operand according to the precision mode of the first operand. When the initial operand is a floating-point number, the bit splitting module is configured to split the initial operand according to the precision mode of the initial operand to generate the third operand, and the bit output module is configured to output the third operand according to the precision mode of the third operand.
4. The operational circuit according to claim 2, characterized in that, It also includes a second splitting module and a leading zero detection module; Wherein, the first end of the second splitting module is connected to the second end of the first splitting module, the second end of the second splitting module is connected to the first end of the leading zero detection module, and the second end of the leading zero detection module is connected to the first end of the calculation module; When the initial operand is a floating-point number, the second splitting module is configured to split the third operand to output the mantissa of the third operand, and the leading zero detection module is configured to perform leading zero detection on the mantissa of the third operand and output the leading zero detection result of the third operand to the calculation module.
5. The operational circuit according to claim 4, characterized in that, The calculation module includes a normalization module, a first selection module, and a first exponent calculation module; Wherein, the first end of the normalization module is connected to the second end of the leading zero detection module, the second end of the normalization module is connected to the first input end of the first selection module and the first end of the first exponent calculation module, and the first end of the first exponent calculation module and the second input end of the first selection module are both connected to the second end of the second splitting module; The normalization module is configured to normalize the mantissa of the third operand based on the leading zero detection result to generate a normalized mantissa result of the third operand; the first selection module is configured to output the normalized mantissa input from the first input terminal or the second input terminal; The first exponent calculation module is configured to perform division exponentiation or first-stage square root exponentiation on the exponent of the third operand based on the normalization processing result; or / and, The first exponent calculation module is configured to perform a subtraction operation on the exponent of the first operand output by the first splitting module.
6. The operational circuit according to claim 5, characterized in that, The calculation module also includes a second exponent calculation module; The second exponent calculation module is connected to the second end of the first exponent calculation module and is configured to perform a second-stage square root exponent calculation on the exponent of the third operand.
7. The operational circuit according to claim 5, characterized in that, It also includes a special floating-point detection module and a floating-point anomaly detection module; Wherein, the first end of the special floating-point detection module is connected to the second end of the first splitting module, and the second end of the special floating-point detection module is connected to both the floating-point anomaly detection module and the first end of the first selection module; The special floating-point detection module is configured to perform special value detection on the third operand, output a first type of data to the floating-point anomaly detection module, and output a second type of data to the first selection module; the floating-point anomaly detection module is configured to perform anomaly detection on the first type of data.
8. The operational circuit according to claim 5, characterized in that, The calculation module also includes a second selection module and an SRT iteration module; Wherein, the first end of the second selection module is connected to the second end of the first splitting module and the second end of the first selection module, the second end of the second selection module is connected to the first end of the SRT iteration module, and the second end of the SRT iteration module is connected to the output module; The second selection module is configured to output the mantissa of the first operand or the mantissa of the third operand to the SRT iteration module; When the initial operand is an integer, the SRT iteration module is configured to perform division or remainder operation on the mantissa of the first operand within a preset first iteration number, or the SRT iteration module is configured to perform square root operation on the mantissa of the first operand. When the initial operand is a floating-point number, the SRT iteration module is configured to perform division or square root operation on the mantissa of the third operand within a preset second iteration number, or the SRT iteration module is configured to perform a modulo operation on the mantissa of the third operand.
9. The operational circuit according to claim 8, characterized in that, The first number of iterations is determined based on the bit width of the first operand, and the second number of iterations is determined based on the precision mode of the initial operand.
10. The operational circuit according to claim 2, characterized in that, It also includes an integer anomaly detection module; The integer anomaly detection module is connected to the second end of the first splitting module and is configured to perform integer anomaly detection on the second operand.