A true random number generator and generation method based on a competition mechanism

Abstract

The application belongs to the field of true random number generators and relates to a true random number generation method based on a competition mechanism. The method triggers two diffusion type memristors to compete for conduction by applying a voltage pulse and uses the random competition behavior of the two diffusion type memristors in the opening process as an entropy source. Before each operation, the two memristors are in a high resistance state. After an operation pulse is applied, one of the two memristors randomly opens first, and the other one opens subsequently. In the initial state, the lower electrodes of the two diffusion type memristors are at a low level. When one of the diffusion type memristors opens first, the potential of the corresponding lower electrode is clamped to a high level. The lower electrode of the diffusion type memristor that opens subsequently remains at a low level. After the pulse is removed, all the opened diffusion type memristors will return to the off state, so as to realize the true random number generation by taking the competition process in the opening time between devices as an entropy source. The method ensures the randomness of the output result and meets the requirements of the true random number generator.

Description

Technical Field

[0001] This invention belongs to the field of true random number generators, and more specifically, relates to a true random number generator and generation method based on a competition mechanism. Background Technology

[0002] A true random number generator (TRNG) is a device that generates random numbers by collecting unpredictable natural phenomena in the physical environment (such as electronic thermal noise, photon behavior, or radioactive decay). Its output is completely unpredictable and non-repeatable, fundamentally different from pseudo-random numbers generated by algorithms. TRNGs are core hardware in fields such as cryptography and secure communications, ensuring absolute reliability of randomness.

[0003] CN114995787A discloses a true random number generator based on a memristor and a method for generating random numbers. It utilizes the temporal and resistance randomness of the reset process of a non-volatile memristor, combined with the capacitor charging and discharging process, to generate random voltage pulses. This process requires an additional reference voltage, which is compared with the reference voltage to generate a count, subsequently leading to the generation of random numbers. Therefore, the random number generation process of this generator is relatively complex. Summary of the Invention

[0004] In view of the above-mentioned defects or improvement needs of the existing technology, the present invention provides a true random number generator and generation method based on a competition mechanism. The purpose is to solve the technical problem of the complex generation process of the existing true random number generator that uses a non-volatile memory resistor as an entropy source.

[0005] To achieve the above objectives, according to one aspect of the present invention, a method for generating true random numbers based on a competition mechanism is provided, comprising: Two diffused memristors are competitively turned on by applying a voltage pulse, and the random competitive behavior of the two diffused memristors during the turn-on process is used as an entropy source. Before each operation, both memristors are in a high-resistance state. After the operation pulse is applied, one of them will randomly turn on first, and the other will turn on subsequently. Initially, the lower electrodes of both diffused memristors are at a low level; when one of the diffused memristors turns on first, its corresponding lower electrode potential is clamped to a high level; and the lower electrode of the diffused memristor that turns on later remains at a low level. After the pulse is removed, all activated diffused memristors will return to the off state, preparing for the next true random number generation operation.

[0006] To achieve the above objectives, according to another aspect of the present invention, a true random number generator based on a competition mechanism is provided, comprising: a first diffused memristor, a second diffused memristor, a first N-type CMOS transistor, a second N-type CMOS transistor, a first current-limiting resistor, and a second current-limiting resistor; The upper electrodes of the first and second diffused memristors are connected together and used to apply a voltage source. The lower electrode of the first diffused memristor is connected to the drain of the first N-type CMOS transistor and the upper end of the first current-limiting resistor, respectively. The lower electrode of the second diffused memristor is connected to the drain of the second N-type CMOS transistor and the upper end of the second current-limiting resistor, respectively. The gate of the first N-type CMOS transistor is connected to the drain of the second N-type CMOS transistor, and the gate of the second N-type CMOS transistor is connected to the drain of the first N-type CMOS transistor. The sources of the first N-type CMOS transistor, the sources of the second N-type CMOS transistor, the lower ends of the first current-limiting resistor, and the lower ends of the second current-limiting resistor are all grounded.

[0007] Furthermore, it also includes a first operational amplifier, a second operational amplifier, an XOR gate, a NOT gate, an AND gate, and a tri-state buffer; Define the lower electrode output node of the first diffused memristor as node A and the lower electrode output node of the second diffused memristor as node B. The output signal of node A is amplified by the first operational amplifier to obtain the first amplified signal, and the output signal of node B is amplified by the second operational amplifier to obtain the second amplified signal, wherein: The first amplified signal and the second amplified signal are XORed by an XOR gate and then used as the control input signal of the tri-state buffer. The second amplified signal is then ANDed with the first amplified signal by an AND gate after passing through an NOT gate, and the result of the AND operation is used as the control input signal of the tri-state buffer. The random number generated by the true random number generator can be obtained by reading the output of the tri-state buffer.

[0008] Furthermore, it also includes a first resistor, a second resistor, a third resistor, and a fourth resistor; The first resistor is connected in series between the negative terminal and the output terminal of the first operational amplifier, and node A is connected to the positive terminal of the first operational amplifier; one end of the second resistor is connected between the negative terminal of the first operational amplifier and the first resistor, and the other end is grounded. The third resistor is connected in series between the negative terminal and the output terminal of the second operational amplifier, and node B is connected to the positive terminal of the second operational amplifier; one end of the fourth resistor is connected between the negative terminal of the second operational amplifier and the third resistor, and the other end is grounded.

[0009] Furthermore, in the initial state, both the first and second diffused memristors are in the off state; when a positive voltage pulse is applied by the voltage source, the first and second diffused memristors begin to compete to turn on, one of which will randomly turn on first, causing its corresponding node potential to jump from low to high; then the other turns on, and due to the clamping effect of the cross coupling of the first and second N-type CMOS transistors, the lower electrode output node of the first turn-on remains at a high level, while the lower electrode output node of the second turn-on remains at a low level.

[0010] Furthermore, the voltage applied by the voltage source exceeds the threshold voltage of the first and second diffused memristors.

[0011] Furthermore, by detecting the level states of nodes A and B, the output of the random number is determined to be 1 or 0, with a low level output of 0.

[0012] Furthermore, when node A is opened first, the output of the tri-state buffer is 1; when node B is opened first, the output of the tri-state buffer is 0; finally, the output of the tri-state buffer can be read to obtain the random number generated by the true random number generator.

[0013] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects: 1. Diffuse-type memristors exhibit significant random characteristics during conduction, stemming from inherent random differences in the formation of conductive channels within their functional layers. This intrinsic randomness leads to significant differences in the conduction timing of different memristors when the same excitation is applied. This invention effectively amplifies this random effect by constructing a conduction competition mechanism between two memristors, thereby forming a high-entropy source and providing a stable and reliable physical basis for true random number generation. This invention utilizes the conduction competition mechanism between two memristors to effectively amplify their intrinsic randomness, thus providing a high-entropy source for true random number generation.

[0014] 2. This invention eliminates the need for the reference voltage commonly used in traditional memristor-type true random number generators, simplifying the circuit structure and reducing design complexity.

[0015] 3. Because the drains and gates of the two NMOS transistors in this invention are cross-connected, forming a clamping effect of cross-coupling, the node that is turned on first maintains a high level, while the node that is turned on later maintains a low level. This structure also exhibits symmetry, so the memristor of either node (A or B) turning on first can represent the generation of the random number "1", resulting in a more stable output.

[0016] 4. When node A is turned on first, the signal is amplified by an operational amplifier, then XORed with the voltage signal of node B, and then used as the control input signal of the three-state buffer. This ensures that no incorrect random numbers will be output when A and B are in the initial state. Attached Figure Description

[0017] Figure 1 A basic schematic diagram of a true random number generator based on a competition mechanism provided for embodiments of the present invention; Figure 2 A basic structural block diagram of a true random number generator based on a competition mechanism is provided for embodiments of the present invention; Figure 3 The IV curve diagram of the diffused memristor provided in the embodiment of the present invention; Figure 4 A block diagram of a true random number generator based on a competition mechanism is provided for embodiments of the present invention. Figure 5 The specific operation flow provided for the use of this invention is as follows.

[0018] In all the accompanying drawings, the same reference numerals are used to denote the same elements or structures, wherein: 1-First diffused memristor, 2-Second diffused memristor, 3-Voltage source, 4-First N-type CMOS transistor, 5-Second N-type CMOS transistor, 6-First current-limiting resistor, 7-Second current-limiting resistor, 8-First operational amplifier, 9-Second operational amplifier, 10-First resistor, 11-Second resistor, 12-Third resistor, 13-Fourth resistor, 14-XOR gate, 15-NOT gate, 16-AND gate, 17-Tri-state buffer. Detailed Implementation

[0019] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.

[0020] like Figure 1 As shown, the present invention provides a true random number generation method based on a competition mechanism, the basic principle of which is as follows: Two diffused memristors are competitively turned on by applying a voltage pulse, and the random competition behavior of the two diffused memristors during the turn-on process is used as an entropy source; before each operation, both memristors are in a high-resistance state; after the operation pulse is applied, one of them will randomly turn on first, and the other will turn on subsequently; initially, the lower electrodes of both diffused memristors are at a low level; when one of the diffused memristors turns on first, its corresponding lower electrode potential is clamped to a high level; the lower electrode of the subsequently turned-on diffused memristor remains at a low level; after the pulse is removed, all the turned-on diffused memristors will return to the off state, preparing for the next true random number generation operation.

[0021] like Figure 2 As shown, the true random number generator of the present invention includes diffused memristors, N-type CMOS transistors, and current-limiting resistors. The upper electrodes of the diffused memristors are common and used to apply the operating voltage; the lower electrodes of each memristor are respectively connected to a current-limiting resistor and the drain of an NMOS transistor. The gates of the NMOS transistors are cross-interconnected to the drains of another NMOS transistor, forming a symmetrical cross-coupling structure. All current-limiting resistors and the sources of the NMOS transistors are grounded.

[0022] Specifically, such as Figure 2 As shown, a preferred true random number generator based on a competition mechanism according to the present invention includes: a first diffused memristor 1, a second diffused memristor 2, a first N-type CMOS transistor 4, a second N-type CMOS transistor 5, a first current-limiting resistor 6, and a second current-limiting resistor 7. The upper electrodes of the first and second diffused memristors 1 and 2 are connected together to apply voltage source 3; the lower electrode of the first diffused memristor 1 is connected to the drain of the first N-type CMOS transistor 4 and the first current-limiting resistor 6 respectively; the lower electrode of the second diffused memristor 2 is connected to the drain of the second N-type CMOS transistor 5 and the second current-limiting resistor 7 respectively; the gate of the first N-type CMOS transistor 4 is connected to the drain of the second N-type CMOS transistor 5, and the gate of the second N-type CMOS transistor 5 is connected to the drain of the first N-type CMOS transistor 4; the source of the first N-type CMOS transistor 4, the source of the second N-type CMOS transistor 5, the source of the first current-limiting resistor 6 and the source of the second current-limiting resistor 7 are all grounded.

[0023] Preferably, such as Figure 4 As shown, it also includes a first operational amplifier 8, a second operational amplifier 9, an XOR gate 14, a NOT gate 15, an AND gate 16, and a tri-state buffer 17; Define the lower electrode output node of the first diffused memristor 1 as node A, and the lower electrode output node of the second diffused memristor 2 as node B. The output signal of node A is amplified by the first operational amplifier 8 to obtain the first amplified signal, and the output signal of node B is amplified by the second operational amplifier 9 to obtain the second amplified signal, wherein: The first amplified signal and the second amplified signal are XORed by XOR gate 14 and then used as the control input signal of the tri-state buffer 17. The second amplified signal is then ANDed with the first amplified signal by AND gate 16 after passing through NOT gate 15, and the result of the AND operation is used as the control input signal of the tri-state buffer 17. The random number generated by the true random number generator can be obtained by reading the output of the tri-state buffer.

[0024] Preferably, it further includes a first resistor 10, a second resistor 11, a third resistor 12, and a fourth resistor 13; The first resistor 10 is connected in series between the negative terminal and the output terminal of the first operational amplifier 8, and node A is connected to the positive terminal of the first operational amplifier 8; one end of the second resistor 11 is connected between the negative terminal of the first operational amplifier 8 and the first resistor 10, and the other end is grounded. The third resistor 12 is connected in series between the negative terminal and the output terminal of the second operational amplifier 9, and node B is connected to the positive terminal of the second operational amplifier 9; one end of the fourth resistor 13 is connected between the negative terminal of the second operational amplifier 9 and the third resistor 12, and the other end is grounded.

[0025] The working principle of this invention is as follows: The random number output is determined as "1" or "0" by detecting the voltage levels of nodes A and B. Initially, both memristors are off. When a positive voltage pulse is applied to the upper electrode, the two memristors begin to compete to turn on. One of them will randomly turn on first, causing its corresponding node potential to jump from low to high. Then the other memristor turns on, and due to the clamping effect of the NMOS cross-coupling, the node that turned on first remains at a high level, while the node that turned on later remains at a low level. Since the circuit structure is completely symmetrical, the priority of memristor turning on at either node (A or B) can represent the generation of the random number "1".

[0026] like Figure 4 and Figure 5 As shown, during initialization, power is supplied to the logic devices and operational amplifiers. Before the voltage pulse is applied, nodes A and B are both at a low level. The applied pulse voltage must exceed [a certain value]. Figure 3 The threshold voltage is shown. After the pulse is applied, the two memristors compete to turn on. Assuming the memristor at node A turns on first, the potential at point A jumps to a high level. This high-level signal is simultaneously applied to the gate of the corresponding NMOS at node B, turning it on and clamping the potential at point B to a low level. The low level at point B is then fed back to the gate of the NMOS at node A, keeping it off, thus maintaining a high level at point A. Even if the memristor at node B later turns on, due to the clamping effect of its NMOS, point B remains at a low level. Therefore, during the pulse duration, if point A turns on first, then A is high and B is low; conversely, if point B turns on first, then B is high and A is low.

[0027] exist Figure 4In the process, operational amplifiers amplify the voltage signals of nodes A and B to ensure they can be recognized by subsequent logic units. When node A is turned on first, the signal is amplified by the operational amplifier. Then, after XORing, it is XORed with the voltage signal of node B, and this result is used as the control input signal of the tri-state buffer. This ensures that A and B do not output incorrect random numbers initially. Node B's signal is amplified by the operational amplifier. Then, after NOT gate, it is ANDed with the signal of node A. The result of this AND operation is used as the input port of the tri-state buffer. After logic control, when node A is turned on first, the output of the tri-state buffer is 1. When node B is turned on first, the output of the tri-state buffer is 0. Finally, reading the output of the tri-state buffer yields the random number generated by the true random number generator.

[0028] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for generating truly random numbers based on a competition mechanism, characterized in that, include: By applying a voltage pulse to trigger two diffused memristors to compete for conduction, the random competitive behavior of the two diffused memristors during the turn-on process is used as an entropy source. Before each operation, both memristors are in a high-resistance state; after an operation pulse is applied, one of them will randomly turn on first, and the other will turn on subsequently. Initially, the lower electrodes of both diffused memristors are at a low level; when one of the diffused memristors turns on first, its corresponding lower electrode potential is clamped to a high level; and the lower electrode of the diffused memristor that turns on later remains at a low level. After the pulse is removed, all activated diffused memristors will return to the off state, preparing for the next true random number generation operation.

2. A true random number generator based on a competition mechanism, characterized in that, include: First diffused memristor (1), second diffused memristor (2), first N-type CMOS transistor (4), second N-type CMOS transistor (5), first current-limiting resistor (6), and second current-limiting resistor (7); The upper electrodes of the first and second diffused memristors (1, 2) are connected together to apply a voltage source (3); the lower electrode of the first diffused memristor (1) is connected to the drain of the first N-type CMOS transistor (4) and the upper end of the first current-limiting resistor (6); the lower electrode of the second diffused memristor (2) is connected to the drain of the second N-type CMOS transistor (5) and the upper end of the second current-limiting resistor (7); the gate of the first N-type CMOS transistor (4) is connected to the drain of the second N-type CMOS transistor (5), and the gate of the second N-type CMOS transistor (5) is connected to the drain of the first N-type CMOS transistor (4); the source of the first N-type CMOS transistor (4), the source of the second N-type CMOS transistor (5), the lower end of the first current-limiting resistor (6) and the lower end of the second current-limiting resistor (7) are all grounded.

3. A true random number generator based on a competition mechanism according to claim 2, characterized in that, It also includes a first operational amplifier (8), a second operational amplifier (9), an XOR gate (14), a NOT gate (15), an AND gate (16), and a tri-state buffer (17). Define the lower electrode output node of the first diffused memristor (1) as node A and the lower electrode output node of the second diffused memristor (2) as node B. The output signal of node A is amplified by the first operational amplifier (8) to obtain the first amplified signal, and the output signal of node B is amplified by the second operational amplifier (9) to obtain the second amplified signal, wherein: The first amplified signal and the second amplified signal are XORed by an XOR gate (14) and then used as the control input signal of the tri-state buffer (17). The second amplified signal is then ANDed with the first amplified signal by an AND gate (16) after passing through an NOT gate (15), and the result of the AND operation is used as the control input signal of the tri-state buffer (17). The random number generated by the true random number generator can be obtained by reading the output of the tri-state buffer.

4. A true random number generator based on a competition mechanism according to claim 3, characterized in that, It also includes a first resistor (10), a second resistor (11), a third resistor (12) and a fourth resistor (13); The first resistor (10) is connected in series between the negative terminal and the output terminal of the first operational amplifier (8), and node A is connected to the positive terminal of the first operational amplifier (8); one end of the second resistor (11) is connected between the negative terminal of the first operational amplifier (8) and the first resistor (10), and the other end is grounded. The third resistor (12) is connected in series between the negative terminal and the output terminal of the second operational amplifier (9), and node B is connected to the positive terminal of the second operational amplifier (9); one end of the fourth resistor (13) is connected between the negative terminal of the second operational amplifier (9) and the third resistor (12), and the other end is grounded.

5. A method for generating truly random numbers based on the truly random number generator of claim 2, characterized in that, In the initial state, both the first and second diffused memristors (1, 2) are in the off state. When the voltage source (3) applies a positive voltage pulse, the first and second diffused memristors (1, 2) begin to compete to turn on. One of them will randomly turn on first, causing its corresponding node potential to jump from low to high. Then the other turns on. Due to the clamping effect of the cross-coupling of the first and second N-type CMOS transistors (4, 5), the lower electrode output node that turns on first maintains a high level, while the lower electrode output node that turns on later maintains a low level.

6. The true random number generation method according to claim 5, characterized in that, The voltage applied by the voltage source (3) exceeds the threshold voltage of the first and second diffused memristors (1, 2).

7. A method for generating truly random numbers based on the truly random number generator of claim 3, characterized in that, The random number output is determined to be 1 or 0 by detecting the level states of nodes A and B.

8. The true random number generation method according to claim 7, characterized in that, When node A is opened first, the output of the tri-state buffer is 1; when node B is opened first, the output of the tri-state buffer is 0; finally, the output of the tri-state buffer can be read to obtain the random number generated by the true random number generator.

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