Data prefetch processing method, multi-level cache processor architecture and computer device

Abstract

The application provides a data prefetch processing method, a multi-level cache processor architecture and a computer device. The method is applied to a multi-level cache processor architecture including a first cache and a second cache. The method includes the following steps: when a first data request corresponding to first data sent by the first cache does not hit the second cache, the second cache determines address information of second data that is likely to be accessed; the second cache stores the address information of the second data to a target cache line of the second cache; in the case that the second data request corresponding to the first data does not hit the first data in the second cache and hits the target cache line, the second cache sends the address information of the second data stored in the target cache line to the first cache; and the first cache sends a prefetch request for the second data to the second cache based on the address information of the second data. The above method can reduce the storage space occupation of the upper-level cache by data prefetching and improve the storage space utilization rate of the upper-level cache.

Description

Technical Field

[0001] This application relates to the field of computer technology, and in particular to a data prefetching processing method, a multi-level cache processor architecture, and a computer device. Background Technology

[0002] In a multi-level cache processor architecture, different caches have different storage sizes. The higher the cache level, the smaller the storage space and the greater the cost if the data in it is corrupted.

[0003] Meanwhile, in a multi-level cache processor architecture, the upper-level cache sends prefetch requests to the lower-level cache to prefetch potentially needed data so that the data can be directly retrieved from the lower-level cache when it is actually needed.

[0004] To achieve accurate data prefetching, the cache needs to perform prefetch training and save the prefetch training results. By using the saved prefetch training results, when a request for a certain data is received, the cache can predict the data that may be used later, thus completing the prefetching of the data that may be used later.

[0005] However, due to the limited storage space of the cache, especially for the upper-level cache, storing the prefetched training results will occupy a lot of storage space, resulting in excessive cache space occupation and reduced cache space utilization. Summary of the Invention

[0006] To address the aforementioned technical issues, this application provides a data prefetching processing method, a multi-level cache processor architecture, and a computer device, which can reduce the storage space occupied by data prefetching on the upper-level cache and improve the storage space utilization of the upper-level cache.

[0007] This application provides a data prefetching processing method applied to a multi-level cache processor architecture, the multi-level cache processor architecture including a first cache and a second cache, the method comprising: When a first data request corresponding to the first data sent by the first cache is not found in the second cache, the second cache determines the address information of the second data that may be accessed after the first data; the second data includes at least one cache line data; The second cache stores the address information of the second data into the target cache line of the second cache; If a second data request corresponding to the first data does not find the first data in the second cache, but does find the target cache line, the second cache sends the address information of the second data stored in the target cache line to the first cache. The first cache sends a prefetch request for the second data to the second cache based on the address information of the second data.

[0008] In some implementations, the address information of the second data includes virtual address information; The second cache determines the address information of the second data after the first data, including: The second cache accesses the first cache to determine the virtual address information of the first data; The second cache determines the virtual address information of the second data that may be accessed after the first data based on the virtual address information of the first data and the prefetched training data.

[0009] In some implementations, the second data includes multiple cached line data following the first data; The second cache stores the address information of the second data into the target cache line, including: The second cache compresses the addresses of the multiple cache line data into an address sequence of one cache line size, stores the address sequence in the target cache line, and adds a prefetch tag to the target cache line.

[0010] In some implementations, the target cache line includes the address of the first data and the address sequence, wherein the address of the first data carries the prefetch tag.

[0011] In some implementations, the second data includes multiple cached line data following the first data; The second cache sends the address information of the second data stored in the target cache line to the first cache, including: The second cache reads the address information of the multiple cache line data from the target cache line, and sends the address information of each cache line data to the first cache in sequence.

[0012] In some implementations, the method further includes: If a third data request corresponding to the first data hits the first data in the second cache and also hits the target cache line, the second cache adds a priority eviction tag to the target cache line.

[0013] In some implementations, the target cache line carries a prefetch tag; The method further includes: After the system context is switched, the second cache sets the target cache line with the same exception level as before the system context is switched and carries the prefetch tag to an invalid state or a priority replacement state. When the second cache needs to evict data for request data backfilling, it will evict the data of the cache line that is in the invalid state or the priority replacement state.

[0014] A second aspect of this application provides a multi-level cache processor architecture, including a first cache and a second cache; wherein: When a first data request corresponding to the first data sent by the first cache is not found in the second cache, the second cache determines the address information of the second data that may be accessed after the first data; the second data includes at least one cache line data; The second cache stores the address information of the second data into the target cache line of the second cache; If a second data request corresponding to the first data does not find the first data in the second cache, but does find the target cache line, the second cache sends the address information of the second data stored in the target cache line to the first cache. The first cache sends a prefetch request for the second data to the second cache based on the address information of the second data.

[0015] In some implementations, the address information of the second data includes virtual address information; The second cache determines the address information of the second data after the first data, including: The second cache accesses the first cache to determine the virtual address information of the first data; The second cache determines the virtual address information of the second data that may be accessed after the first data based on the virtual address information of the first data and the prefetched training data.

[0016] A third aspect of this application provides a computer device including a multi-level cache processor architecture, the multi-level cache processor architecture including a first cache and a second cache, the multi-level cache processor architecture being configured to implement the above-described data prefetching processing method.

[0017] The data prefetching method proposed in this application, when a first data request corresponding to first data sent from the first cache misses in the second cache, determines the address information of second data that may be accessed after the first data and stores the address information in the target cache line of the second cache. When a second data request corresponding to the first data misses in the second cache but hits the target cache line, the second cache sends the address information of the second data in the target cache line to the prefetcher of the first cache, and the prefetcher of the first cache sends a prefetch request for the second data to the second cache. This method stores the prefetched training data in the second cache. When data needs to be prefetched, the second cache sends the address information of the data to be prefetched to the first cache, notifying the first cache to perform the data prefetching operation. This method can avoid excessive occupation of the storage space of the first cache due to storing prefetched training results in the first cache, thereby improving the storage space utilization of the first cache. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0019] Figure 1 This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application.

[0020] Figure 2 This is a flowchart illustrating a data prefetching processing method provided in an embodiment of this application. Detailed Implementation

[0021] The technical solution of this application embodiment is applicable to application scenarios of cache data prefetching in a multi-level cache processor architecture. The technical solution of this application embodiment can reduce the storage space occupation of the first cache by data prefetching and improve the storage space utilization of the first cache.

[0022] In the hierarchical structure of a computer storage system, cache is a high-speed, small-capacity memory located between the central processing unit (CPU) and main memory. It consists of static RAM chips, which have a relatively small capacity but are faster than main memory, approaching the speed of the CPU.

[0023] The working principle of caching is as follows: When the CPU needs to read data, it first searches for it in the CPU cache. If found, it reads the data immediately and sends it to the CPU for processing. If not found, it reads the data from the relatively slower main memory and sends it to the CPU for processing. Simultaneously, the data block containing this data is loaded into the cache. This allows subsequent reads of the entire data block to be performed from the cache, avoiding further access to main memory. This reading mechanism increases the CPU's cache hit rate, meaning that the data the CPU needs to read next is more likely to be in the CPU cache, with only a small amount of data needing to be read from main memory. This significantly saves the time the CPU spends directly reading from main memory and essentially eliminates waiting time when reading data.

[0024] The data in the cache is only a copy of a portion of the data in memory. Therefore, when the CPU searches for data in the cache, it may encounter situations where it cannot find the data (because some data has not been copied from memory to the cache). In this case, the CPU will still read the data from memory, thus slowing down the CPU's data read speed. However, the CPU will copy the read data into the cache for future use. Therefore, the more frequently data is accessed, the longer it remains in the cache. Furthermore, the most frequently accessed data changes over time, so the data in the cache needs to be frequently updated according to a specific algorithm to ensure that the data in the cache always represents the most frequently accessed data.

[0025] The technical solution of this application embodiment is applicable to a multi-level cache processor architecture, which includes multiple levels of cache, such as two-level cache, three-level cache, four-level cache, or any number of other cache levels.

[0026] In the multi-level cache described above, based on their distance from the processor core, the caches can be defined as Level 1 cache, Level 2 cache, Level 3 cache, and so on. The earlier the cache level, the closer it is to the processor core, and the faster the processor core can read data from it. Conversely, the later the cache level, the farther it is from the processor core, and the slower the processor core can read data from it. For example, the processor core can read data from the Level 1 cache faster than from the Level 2 cache, and from the Level 2 cache faster than from the Level 3 cache.

[0027] Generally, the earlier a cache is in the cache hierarchy, the more frequently the stored data is accessed by the processor core; conversely, the later a cache is in the cache hierarchy, the less frequently the stored data is accessed by the processor core. Furthermore, caches at earlier tiers typically have smaller storage spaces, while caches at later tiers generally have larger storage spaces.

[0028] Figure 1This is a schematic diagram of a multi-level cache processor architecture provided in an embodiment of this application. In this multi-level cache processor architecture, three levels of cache are exemplarily shown, namely the first level cache L1, the second level cache L2, and the third level cache L3.

[0029] The first-level cache (L1) is further divided into instruction cache (L1I) and data cache (L1D). Instruction cache (L1I) is used to cache instructions, and data cache (L1D) is used to cache data.

[0030] The first-level cache L1 mentioned above, which includes instruction cache L1I and data cache L1D, shares the second-level cache L2.

[0031] See Figure 1 As shown, this multi-level cache processor architecture includes multiple processor cores. Each processor core is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. Multiple processor cores share a single Level 3 cache L3.

[0032] See also Figure 1 For multiple processor cores, different regions can be defined. Each processor core in each region is configured with its own dedicated Level 1 cache (including instruction cache L1I and data cache L1D) and Level 2 cache L2. All processor cores in this region share a single Level 3 cache L3. Processor cores in multiple regions share the system main memory through an on-chip network.

[0033] In the processor architecture described above, when a LOAD instruction misses the required data in L1D, L1D sends a read request to L2 to read the data. If the data is still not found in L2, a read request is sent to L3 to read the data. If the data is still not found in L3, it needs to be read from main memory. During this process, if the required data is found in a certain level of cache, it is returned sequentially to the upper-level caches until it is returned to the processor. For example, if the data is read from L2, the cache line containing that data is returned to L1, where it is stored, and L1 then returns the cache line to the processor.

[0034] Data prefetching refers to storing the data needed by the processor core in a cache so that when the processor core actually needs to read this data, it can directly retrieve it from the cache without having to read the data from main memory again. Data prefetching also reduces the probability of data requests missing from the cache.

[0035] For example in Figure 1In the multi-level cache processor architecture shown, L1D sends a prefetch request to L2C, causing L2C to prefetch and load the target data into L2C. When the processor core actually needs the target data, L1D sends a data request to L2C, and the data can be obtained from L2C.

[0036] In the aforementioned data prefetching process, the prefetcher in the cache needs to be trained based on the data request process of the processor core. That is, the prefetcher extracts the data request patterns of the processor core based on the data request process of the processor core as training data for training. Thus, during the operation of the processor core, the trained prefetcher can accurately predict the data that the processor core needs to read in the next operation.

[0037] The training data mentioned above is typically stored in the local cache storage. However, as the amount of data processed by the processor cores increases, the training data also grows larger, consuming more and more cache storage space, leading to insufficient cache storage. This is especially true for upper-level caches, such as L1D, which have limited storage space and are more susceptible to contamination. Storing all prefetched training data in the cache can result in insufficient storage space for cached data, reducing cache space utilization.

[0038] To address the aforementioned technical problems, this application provides a novel data prefetching method. This method stores prefetched training data in a lower-level cache, and when data needs to be prefetched from the upper-level cache, the lower-level cache sends the prefetched training data to the upper-level cache, enabling the upper-level cache to perform the data prefetching operation. This method can save storage space in the upper-level cache and improve its utilization rate.

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0040] This application first provides a data prefetching processing method, which can be applied to a multi-level cache processor architecture. This architecture includes a first cache and a second cache, wherein the first cache is located at the upper level of the second cache (i.e., the first cache is the upper-level cache of the second cache), and similarly, the second cache is the lower-level cache of the first cache. Furthermore, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0041] The aforementioned multi-level cache processor architecture can be as follows: Figure 1The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1 The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0042] The data prefetching processing method provided in this application embodiment can be applied to a first cache and a second cache, specifically to a scenario where the first cache sends a prefetch request to the second cache to prefetch data into the second cache. This data prefetching processing method can be implemented through the interaction of the prefetcher of the first cache and the prefetcher of the second cache.

[0043] See Figure 2 As shown, the data prefetching processing method provided in this application embodiment includes: S101. When the first data request corresponding to the first data sent by the first cache is not hit in the second cache, the second cache determines the address information of the second data that may be accessed after the first data.

[0044] Specifically, when the first cache sends a first data request to the second cache to request first data, but the first data request is not found in the second cache, the second cache sends a data request to the next-level cache or main memory to request the first data. When the first data is obtained from the next-level cache or main memory, the first data is cached in the second cache and returned to the first cache.

[0045] On the other hand, in this embodiment, the prefetcher of the second cache determines the second data that may be accessed after the first data request based on the missed first data request and the pre-stored prefetch training data. The pre-stored prefetch training data refers to data used to train the prefetcher to perform data prefetching, determined based on the historical data request process of the processor core. Typically, the process of the processor core running a program and making data requests is repetitive or regular. The prefetcher records and summarizes the data request process of the processor core to obtain prefetch training data. This prefetch training data can characterize the data request patterns of the processor core and can be regarded as empirical data of the processor core's data request process. For example, each time a processor core runs an application, it requests data A, B, C, D, E, and F in sequence. Then, {A, B, C, D, E, F} can form a set of prefetch training data. Based on this prefetch training data, when the processor core runs the application again and requests data A, the prefetcher can prefetch data B, C, D, E, and F into the cache in advance, so that the processor core can hit the cache when it subsequently requests data B, C, D, E, and F.

[0046] Based on the aforementioned prefetch training data, when the second cache detects a first data request sent by the first cache that misses in the second cache, the prefetcher of the second cache checks whether there is any information related to the first data that missed in the prefetch training data. If there is information related to the first data that missed, it means that there is prefetch training data related to the first data in the prefetch training data. At this time, the second cache determines, based on the information related to the first data, information related to the second data that may be accessed after the first data from the prefetch training data. The second data can be data from at least one cache line following the first data.

[0047] In this embodiment, the second cache determines the address information of the second data that may be accessed after the first data based on the address information of the first cache that was missed.

[0048] The address information mentioned above may be a physical address or a virtual address, depending on the address type used when training the prefetcher and the address types used in the first and second caches.

[0049] Typically, the data addresses used for prefetching training of the prefetchers for the first and second caches can be either physical addresses or virtual addresses.

[0050] If the first cache uses virtual addresses and the second cache uses physical addresses, and the prefetcher of the second cache is trained using virtual addresses, then when a data request for the first data fails in the first cache, a backfill buffer is allocated for that data request in the first cache. At this time, the virtual address of the first data is stored in this backfill buffer. Then, the first cache sends a first data request to the second cache, carrying the physical address of the first data. If this first data request fails in the second cache, the second cache accesses the backfill buffer of the first cache to obtain the virtual address of the first data. This virtual address of the first data is then used to train the prefetcher of the second cache.

[0051] In the above process, the second cache first determines the virtual address of the first data that was not hit in the second cache by accessing the first cache. Then, based on the virtual address of the first data and the prefetch training data of the second cache, it determines the virtual address information of the second data that may be accessed after the first data.

[0052] If the first cache uses virtual addresses and the second cache uses physical addresses, and the second cache's prefetcher is trained using physical addresses, then when a data request for the first data fails in the first cache, a backfill buffer is allocated for that data request in the first cache. At this time, the virtual address of the first data is stored in this backfill buffer. Then, the first cache sends a first data request to the second cache, carrying the physical address of the first data. If this first data request fails in the second cache, the second cache sends the physical address of the first data to its prefetcher. When the second cache's prefetcher has been trained to a certain extent, it can determine the physical address information of the second data that might be accessed later based on the physical address of the first data, and will also directly send a prefetch request for the second data to the second cache.

[0053] If the first cache and the second cache use the same address, such as both using virtual or physical addresses, when a data request for the first data fails to find the data in the first cache, a backfill buffer will be allocated for the data request in the first cache, and the first data will be stored in this backfill buffer. If both the first cache and the second cache use virtual addresses, the virtual address of the first data will be stored in the backfill buffer; if both the first cache and the second cache use physical addresses, the physical address of the first data will be stored in the backfill buffer.

[0054] Then, the first cache sends a first data request to the second cache to request the first data. If both the first and second caches use virtual addresses, the first data request carries the virtual address of the first data; if both the first and second caches use physical addresses, the first data request carries the physical address of the first data. If the first data request misses in the second cache, the second cache sends the physical address of the first data to its prefetcher. When the second cache's prefetcher has been trained to a certain extent, it can determine the physical address information of the second data that may be accessed later based on the physical address of the first data, and will also directly send a prefetch request for the second data to the second cache.

[0055] In the above process, since the second data and the first data are usually data from adjacent cache lines, the address information of the second data can be deduced based on the storage location relationship between the second data and the first data, given that the address information of the first data is determined.

[0056] When a data request for the first data fails to reach the first cache, a backfill buffer is allocated for that data request in the first cache. At this time, the virtual address of the first data is stored in the backfill buffer, and the position (id) of the data request within that backfill buffer is recorded. Then, the first cache sends the first data request to the second cache. This first data request carries the physical address of the first data and its position (id) within the first cache's backfill buffer. If the first data request fails to reach the second cache, the second cache retrieves the virtual address of the first data by accessing the corresponding position (id) in the first cache's backfill buffer.

[0057] Through the above processing, the second cache can determine the address information of the second data that may be accessed after the first data.

[0058] S102, The second cache stores the address information of the second data into the target cache line of the second cache.

[0059] Specifically, after obtaining the address information of the second data through step S101, the prefetcher of the second cache stores the address information of the second data into the target cache line of the second cache. This target cache line can be any free cache line in the second cache.

[0060] In some embodiments, the second data includes data from multiple cache lines following the first data. In this case, when storing the address information of the second data, the second cache first compresses the addresses of the data from the multiple cache lines following the first data into an address sequence the size of a cache line, and then stores this address sequence in the target cache line. Simultaneously, a prefetch tag is added to the target cache line. This target cache line is the cache line used by the second cache to store the first data request when it determines that the first data request has failed.

[0061] In another embodiment, a target cache line for storing the address information of the second data described above is disclosed, including an address storage bit and a data storage bit. The address storage bit stores the address information of the first data, while the data storage bit stores the address sequence described above. Then, a prefetch tag is added to the address information of the first data stored in the address storage bit.

[0062] Through the above processing, the prefetcher of the second cache stores the address information of all second data that may be accessed after the first data into the target cache line. The address information of the second data can also be encoded or compressed before storage.

[0063] S103. If the second data request corresponding to the first data does not find the first data in the second cache, but finds the target cache line, the second cache sends the address information of the second data stored in the target cache line to the first cache.

[0064] Specifically, when the second cache receives another data request for the first data, such as a second data request for the first data, it determines whether the second data request hits the first data in the second cache. If the second data request does not hit the first data in the second cache, but hits the target cache line stored in the second cache and marked with a prefetch tag, the prefetcher of the second cache can determine that the second data after the first data needs to be prefetched at this time.

[0065] In this case, the second data request hitting the target cache line marked with a prefetch tag means that the address information of the requested first data carried in the second data request matches the address information of the first data stored in the address storage bit of the target cache line marked with a prefetch tag. At this time, it is considered that the second data request has hit the target cache line marked with a prefetch tag.

[0066] If the prefetcher of the second cache determines that the second data request hits the target cache line that has been prefetched, the prefetcher of the second cache reads the address information of the second data in the target cache line, that is, decodes and reads the information stored in the data storage bits of the target cache line, and sends the read address information of the second data to the prefetcher of the first cache so that the prefetcher of the first cache can prefetch the second data.

[0067] In another embodiment, the second data includes data from multiple cache lines following the first data. Correspondingly, the address information of the second data stored in the target cache line of the second cache includes the address information of these multiple cache line data. When the prefetcher of the second cache sends the address information of the second data to the prefetcher of the first cache, it decodes and reads the address information of these multiple cache line data from the target cache line, and then sends the address information of each cache line data sequentially to the prefetcher of the first cache in chronological order.

[0068] For example, assuming the first data is data A, and the address information of the second data stored in the target cache line is specifically the address information of data B, data C, data D, data E, and data F after data A {B, C, D, E, F}, then after the prefetcher of the second cache reads {B, C, D, E, F} from the target cache line, it sends the address of data B, the address of data C, the address of data D, the address of data E, and the address of data F to the prefetcher of the first cache in the order of their respective addresses.

[0069] In another embodiment, the prefetcher in the second cache stores the address information of the second data that may be accessed after the first data in the target cache line and adds a prefetch tag to the target cache line. When the second cache receives other data requests for the first data, such as a third data request for the first data, it determines whether the third data request hits the first data in the second cache. If the third data request hits the first data in the second cache and hits the target cache line stored in the second cache and marked with a prefetch tag, the second cache adds a priority eviction tag to the target cache line marked with a prefetch tag. In subsequent operation, when the data requests stored in the second cache are full and it is necessary to evict the requests stored in some cache lines, the data in these cache lines carrying priority eviction tags are evicted first.

[0070] S104. The first cache sends a prefetch request for the second data to the second cache based on the address information of the second data.

[0071] Accordingly, when the first cache receives the address information of the second data sent by the second cache, it generates a prefetch request for the second data and sends the prefetch request to the second cache, so that the second cache can prefetch the second data. When a subsequent processor core requests the second data, it can find the second data in the second cache.

[0072] In another embodiment, the second data includes data from multiple cache lines following the first data. When the prefetcher of the second cache sends the address information of the second data to the prefetcher of the first cache, it sends the address information of each cache line in sequential order. Correspondingly, when the first cache receives the address information of a cache line from the second cache, it immediately sends a prefetch request for that cache line to the second cache. This process is repeated, with the first cache prefetcher sequentially sending prefetch requests for each cache line following the first data to the second cache. The second cache then sequentially performs the prefetch operation for each cache line.

[0073] As described above, in the data prefetching processing method proposed in this application, when a first data request corresponding to first data sent by the first cache is not found in the second cache, the second cache determines the address information of second data that may be accessed after the first data and stores the address information in the target cache line of the second cache. When a second data request corresponding to the first data is not found in the second cache but is found in the target cache line, the second cache sends the address information of the second data in the target cache line to the first cache, and the first cache sends a prefetch request for the second data to the second cache. This method stores the prefetched training data in the second cache. When data needs to be prefetched, the second cache sends the address information of the data to be prefetched to the first cache, notifying the first cache to perform the data prefetching operation. This method can avoid the excessive occupation of the storage space of the first cache due to storing the prefetched training results in the first cache, thereby improving the storage space utilization of the first cache.

[0074] In another embodiment, it is also disclosed that the target cache line in the second cache for storing address information of the second data that may be accessed after the first data carries a prefetch tag, the addition of which can be found in the description of the above embodiments.

[0075] When the system switches contexts, requests with the same exception level as before the context switch should be evicted first, because the data of these requests may not be accessed in the short term. In other words, the previous prefetched training data is no longer accurate for data access after the context switch, so the previous prefetched training data needs to be evicted.

[0076] The aforementioned exception level configuration is used to assign different privilege levels to different code within the system, thereby achieving secure, efficient, and layered protection of system resources. For example, the operating system kernel, hypervisor, security firmware, and user programs are assigned different exception levels, granting them different hardware or software privileges. Code with different exception levels will not compete for resources, and code with higher exception levels will not be subject to damage or security threats from code with lower exception levels.

[0077] Under the above-mentioned exception level mechanism, when a system context switch occurs, the memory data accessed by the processor core will also change if the context switch occurs within the same exception level. Therefore, after the system context switch, the data content in the cache that is at the same exception level as before the context switch is likely not to be used again for a short period of time. At this time, this data content can be evicted to free up cache space for storing the data content that is currently needed.

[0078] Based on the above ideas, in this embodiment, when the system switches context, the second cache sets the target cache line with the same exception level as before the system switches context and carries the prefetch label to an invalid state or a priority replacement state. That is, the target cache line storing the prefetch training data in the second cache is set to an invalid state or a priority replacement state.

[0079] In this process, when a target cache line with the same exception level as before the system context switch and carrying the prefetch tag is set to an invalid state, the second cache first generates a prefetch wipe request. Then, starting from set0 in the second cache, it queries the target cache lines in the second cache that carry the prefetch tag and have the same exception level as before the context switch, and sets the queried target cache lines to an invalid state, for example, by adding an invalid tag to the queried target cache lines. Then, it increments set by 1, and so on, until the entire second cache has been queried. Through the above processing, all target cache lines in the second cache that carry the prefetch tag and have the same exception level as before the context switch are marked as invalid. Subsequently, when the second cache needs to evict requests or data, it will directly evict the invalid cache lines. This scheme is suitable for scenarios where, after a context switch, subsequent requests will no longer access data saved in the second cache before the context switch.

[0080] When the second cache sets a target cache line with the same exception level as before the system context switch and carrying the prefetch tag to a pre-replacement state, the second cache first generates a prefetch wipe request. Then, starting from set0 of the second cache, it queries the target cache lines in the second cache that carry the prefetch tag and have the same exception level as before the context switch, updates the corresponding algorithm, and sets this cache line to a priority replacement state. For example, it adds a priority replacement tag to the queried cache line, then increments set by 1, until the entire second cache has been queried. Through the above processing, all target cache lines in the second cache that carry the prefetch tag and have the same exception level as before the context switch can be marked as priority replacement states. Subsequently, when the second cache needs to evict requests or data, it can choose to evict cache lines in the priority replacement state. This scheme is suitable for scenarios where, after a context switch, subsequent requests will not access data saved in the second cache before the context switch for a short period of time, but may access this data after a longer period of time.

[0081] After the above processing, when the second cache needs to evict data during request data backfilling, it can evict data in the cache line that is in an invalid state or a priority replacement state. Furthermore, the second cache can prioritize evicting cache lines in an invalid state, and only evict cache lines in a priority replacement state when there are no invalid cache lines.

[0082] The solution in this embodiment allows for flexible updating or evicting of prefetched training data in the second cache, while saving storage space in the first cache and improving the space utilization of the first cache by saving prefetched training data to the second cache. This avoids insufficient storage space in the second cache due to the continuous addition of prefetched training data.

[0083] Another embodiment of this application provides a multi-level cache processor architecture, which includes a first cache and a second cache. The first cache is located at the upper level of the second cache, that is, the first cache is the upper-level cache of the second cache, and similarly, the second cache is the lower-level cache of the first cache. Furthermore, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0084] The aforementioned multi-level cache processor architecture can be as follows: Figure 1 The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1 The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0085] The multi-level cache processor architecture provided in this embodiment is configured to implement the data prefetching processing method described in any of the above embodiments. The specific processing steps and corresponding beneficial effects of this multi-level cache processor architecture in implementing the above data prefetching processing method can be found in the descriptions of the above method embodiments, and will not be repeated here.

[0086] Furthermore, another embodiment of this application provides a computer device including a multi-level cache processor architecture. This architecture includes a first cache and a second cache, wherein the first cache is located at the upper level of the second cache; that is, the first cache is the upper-level cache of the second cache, and similarly, the second cache is the lower-level cache of the first cache. Moreover, the first cache and the second cache are different caches at adjacent levels, wherein the storage space of the second cache is larger than the storage space of the first cache.

[0087] The aforementioned multi-level cache processor architecture can be as follows: Figure 1 The multi-level cache processor architecture shown can be configured such that the first cache and the second cache are respectively... Figure 1 The first level cache (L1, specifically L1C or L1D) and the second level cache (L2) can be used, or the first and second caches can be respectively... Figure 1 The second-level cache (L2) and the third-level cache (L3) are used in the system.

[0088] The multi-level cache processor architecture in the computer device provided in this embodiment is configured to implement the data prefetching processing method described in any of the above embodiments. The specific processing steps and corresponding beneficial effects of the multi-level cache processor architecture implementing the above data prefetching processing method can be found in the descriptions of the above method embodiments, and will not be repeated here.

[0089] For the foregoing method embodiments, in order to simplify the description, they are all described as a series of actions. However, those skilled in the art should understand that this application is not limited to the described order of actions, because according to this application, some steps can be performed in other orders or simultaneously. Furthermore, those skilled in the art should also understand that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily essential to this application.

[0090] It should be noted that the various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For apparatus embodiments, since they are basically similar to method embodiments, the description is relatively simple; relevant parts can be referred to the descriptions in the method embodiments.

[0091] The steps in the methods of the various embodiments of this application can be adjusted, merged, or deleted in order according to actual needs, and the technical features described in each embodiment can be replaced or combined.

[0092] The modules and sub-modules in the various embodiments of the present application's devices and terminals can be merged, divided, and deleted according to actual needs.

[0093] It should be understood that the disclosed terminals, devices, and methods can be implemented in other ways, given the several embodiments provided in this application. For example, the terminal embodiments described above are merely illustrative. For instance, the division of modules or sub-modules is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple sub-modules or modules may be combined or integrated into another module, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be indirect coupling or communication connection through some interfaces, devices, or modules, and may be electrical, mechanical, or other forms.

[0094] The modules or submodules described as separate components may or may not be physically separate. The components that constitute a module or submodule may or may not be physical modules or submodules; that is, they may be located in one place or distributed across multiple network modules or submodules. Some or all of the modules or submodules can be selected to achieve the purpose of this embodiment's solution, depending on actual needs.

[0095] Furthermore, the functional modules or sub-modules in the various embodiments of this application can be integrated into one processing module, or each module or sub-module can exist physically separately, or two or more modules or sub-modules can be integrated into one module. The integrated modules or sub-modules described above can be implemented in hardware or in the form of software functional modules or sub-modules.

[0096] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0097] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software unit executed by a processor, or a combination of both. The software unit can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.

[0098] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0099] The above description of the disclosed embodiments enables those skilled in the art to make or use this application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of this application. Therefore, this application is not to be limited to the embodiments shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A data prefetching processing method, characterized by, Applied to a multi-level cache processor architecture, the multi-level cache processor architecture including a first cache and a second cache, the method includes: When a first data request corresponding to the first data sent by the first cache is not found in the second cache, the second cache determines the address information of the second data that may be accessed after the first data; the second data includes at least one cache line data; The second cache stores the address information of the second data into the target cache line of the second cache; If a second data request corresponding to the first data does not find the first data in the second cache, but does find the target cache line, the second cache sends the address information of the second data stored in the target cache line to the first cache. The first cache sends a prefetch request for the second data to the second cache based on the address information of the second data.

2. The method of claim 1, wherein, The address information of the second data includes virtual address information; The second cache determines the address information of the second data after the first data, including: The second cache accesses the first cache to determine the virtual address information of the first data; The second cache determines the virtual address information of the second data that may be accessed after the first data based on the virtual address information of the first data and the prefetched training data.

3. The method of claim 1, wherein, The second data includes multiple cached lines of data following the first data; The second cache stores the address information of the second data into the target cache line, including: The second cache compresses the addresses of the multiple cache line data into an address sequence of one cache line size, stores the address sequence in the target cache line, and adds a prefetch tag to the target cache line.

4. The method of claim 3, wherein, The target cache line includes the address of the first data and the address sequence, wherein the address of the first data carries the prefetch tag.

5. The method according to claim 1, characterized in that, The second data includes multiple cached lines of data following the first data; The second cache sends the address information of the second data stored in the target cache line to the first cache, including: The second cache reads the address information of the multiple cache line data from the target cache line, and sends the address information of each cache line data to the first cache in sequence.

6. The method according to any one of claims 1 to 5, characterized in that, The method further includes: If a third data request corresponding to the first data hits the first data in the second cache and also hits the target cache line, the second cache adds a priority eviction tag to the target cache line.

7. The method according to any one of claims 1 to 5, characterized in that, The target cache line carries a prefetch tag; The method further includes: After the system context is switched, the second cache sets the target cache line with the same exception level as before the system context is switched and carries the prefetch tag to an invalid state or a priority replacement state. When the second cache needs to evict data for request data backfilling, it will evict the data of the cache line that is in the invalid state or the priority replacement state.

8. A multi-level cache processor architecture, characterized in that, Includes the first cache and the second cache; where: When a first data request corresponding to the first data sent by the first cache is not found in the second cache, the second cache determines the address information of the second data that may be accessed after the first data; the second data includes at least one cache line data; The second cache stores the address information of the second data into the target cache line of the second cache; If a second data request corresponding to the first data does not find the first data in the second cache, but does find the target cache line, the second cache sends the address information of the second data stored in the target cache line to the first cache. The first cache sends a prefetch request for the second data to the second cache based on the address information of the second data.

9. The multi-level cache processor architecture according to claim 8, characterized in that, The address information of the second data includes virtual address information; The second cache determines the address information of the second data after the first data, including: The second cache accesses the first cache to determine the virtual address information of the first data; The second cache determines the virtual address information of the second data that may be accessed after the first data based on the virtual address information of the first data and the prefetched training data.

10. A computer device, characterized in that, The system includes a multi-level cache processor architecture, which includes a first cache and a second cache, and is configured to implement the data prefetching processing method as described in any one of claims 1 to 7.

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