A timing convergence method and apparatus based on clock trees

Abstract

This invention discloses a timing closure method and apparatus based on a clock tree, relating to the field of circuit design technology. The method includes: automatic device placement; determining the timing paths requiring optimization in a one-to-many structure timing path; optimizing setup time timing margins and determining a useful clock skew adjustment setting pattern based on the optimized setup time timing margins; determining the number of buffers based on the useful clock skew adjustment setting pattern and the optimized setup time timing margins, and generating a clock tree; determining whether the hold time timing violations of the timing paths requiring optimization meet predetermined requirements based on the generated clock tree; if the predetermined requirements are not met, adjusting the useful clock skew adjustment setting pattern and returning to the clock tree generation step; and completing automatic routing based on the clock tree that meets the predetermined requirements. This invention can solve the problem of increased power consumption caused by repairing hold timing violations.

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