Equivalence testing methods, systems, electronic devices, and storage media for quantum circuits

Abstract

This invention discloses a method, system, electronic device, and storage medium for verifying the equivalence of quantum circuits, relating to the field of quantum computing technology. The method includes: acquiring a first quantum circuit and a second quantum circuit; constructing an inverse circuit of a preset quantum circuit, where the preset circuit is either the first or second circuit, and the other circuit is a non-preset circuit; constructing a local random circuit and its inverse circuit; sequentially combining the local random circuit, the non-preset circuit, the preset inverse circuit, and the local random inverse circuit into a composite circuit; repeatedly executing the composite circuit m times with an all-zero state as the initial state, randomly generating local random circuit parameters each time; statistically analyzing the frequency of the all-zero state as a probability p; comparing p with a threshold δ; if p ≥ δ, then equivalence is determined; otherwise, equivalence is not considered. This invention directly verifies the equivalence of quantum circuits on quantum hardware through composite circuits, avoiding the exponential consumption of classical simulation. It requires only n qubits, no additional resources, significantly reducing costs while maintaining accuracy.

Description

Technical Field

[0001] This invention relates to the field of quantum computing technology, and in particular to a method, system, electronic device, and storage medium for verifying the equivalence of quantum circuits. Background Technology

[0002] Quantum computers exhibit the potential for exponential speedup compared to classical computers in solving specific problems, and the realization of this advantage highly depends on the efficient execution of quantum algorithms. In the development of quantum algorithms, researchers initially focus on the logical-level algorithm design, without considering hardware implementation details. However, before the algorithm is actually deployed, these logical operations must be transformed into sequences of quantum gates, i.e., quantum circuits, executable by a quantum computer. For the same quantum algorithm, different compilers may generate quantum circuits with different structures; therefore, verifying the functional equivalence of these circuits is crucial to ensuring the reliability of the algorithm implementation and the correctness of compiler optimizations.

[0003] Currently, existing methods for verifying the equivalence of quantum circuits mainly fall into three traditional categories. The first method relies on classical computers to compute the complete matrix representation of the quantum circuit and determines equivalence by comparing whether the matrices are identical. However, the computational resources required by this method increase exponentially with the number of qubits. The second method is a verification scheme based on ZX graphs, which verifies the equivalence by simplifying the quantum circuit and its inverse to form a composite circuit. However, in practical applications, composite circuits are often difficult to completely simplify, still requiring classical computational resources to determine whether the remaining part is an identity matrix. The third method, the decision graph method, transforms the quantum circuit into a decision graph and performs equivalence comparisons. However, in complex scenarios, the representation and processing of decision graphs also face the problem of exponential resource consumption. The recently developed RH algorithm uses quantum generative adversarial networks to directly verify circuit equivalence on quantum hardware. This method does not rely on classical simulation, thus avoiding exponential resource consumption in principle.

[0004] However, these existing technologies all have significant limitations. Traditional methods cannot overcome the problem of exponential resource consumption, making them unsuitable for large-scale quantum circuit verification scenarios. While the RH algorithm employs a quantum hardware verification strategy, it still suffers from significant drawbacks: it requires twice the number of qubits of the circuit to be verified, necessitates the introduction of additional auxiliary circuit modules to entangle the circuit under test, and requires complex post-measurement processing to extract equivalence conclusions. Furthermore, as a QGAN-based method, the RH algorithm requires pre-training of the discriminator before verification, all of which greatly increase the implementation complexity and overall cost of the algorithm.

[0005] To address the issues of high resource consumption and implementation cost of existing quantum circuit equivalence verification methods, there is an urgent need for a verification scheme that can be implemented at low cost on quantum computers. This scheme should avoid the exponential resource consumption of classical simulations and overcome the high cost of existing quantum verification methods, providing a practical verification means for the reliable implementation of quantum algorithms and the optimization and development of compilers. Summary of the Invention

[0006] The technical problem to be solved by this invention is to address the shortcomings of existing technologies, specifically by providing a method, system, electronic device, and storage medium for verifying the equivalence of quantum circuits, as detailed below: 1) In a first aspect, the present invention provides a method for verifying the equivalence of quantum circuits, the specific technical solution of which is as follows: Obtain the first quantum circuit and the second quantum circuit. Both the first quantum circuit and the second quantum circuit are quantum circuits that operate on n qubits, and the first quantum circuit and the second quantum circuit are quantum gate sequences obtained by different compilers for the same quantum algorithm. Construct the inverse circuit of a preset quantum circuit, wherein the preset quantum circuit is either the first quantum circuit or the second quantum circuit, and the other quantum circuit is defined as a non-preset quantum circuit; Construct local random circuits and their inverses; Combine local random circuits, non-preset quantum circuits, inverse circuits of preset quantum circuits, and inverse circuits of local random circuits into composite circuits according to the execution order. Using the all-zero state as the initial quantum state, the composite circuit is repeatedly executed m times. During each execution, the parameters of the local random circuit are randomly generated. The probability p is the percentage of times the quantum state is all zero in the measurement results after m executions. Compare the probability p with the decision threshold δ. If the probability p is greater than or equal to the decision threshold δ, then the first quantum circuit and the second quantum circuit are determined to be equivalent; otherwise, the first quantum circuit and the second quantum circuit are determined to be inequivalent. Where n and m are both positive integers.

[0007] The beneficial effects of the quantum circuit equivalence verification method provided by this invention are as follows: By constructing a composite circuit containing local random circuits and their inverses, equivalence verification is directly performed on quantum hardware, fundamentally avoiding the exponential computational resource consumption caused by classical simulations in traditional methods. Compared to existing quantum verification schemes, this method only requires the same number of qubits as the circuit to be verified, i.e., n qubits, without the need for additional quantum resources, significantly reducing hardware requirements. During the verification process, the fidelity information between circuits can be obtained by directly statistically analyzing the probability p of all-zero states appearing in the measurement results, eliminating the need for complex post-measurement processing and simplifying the implementation steps. Furthermore, this method completely avoids the pre-training stage of the discriminator in quantum generative adversarial networks, further reducing algorithm complexity and time costs. This efficient and concise verification mechanism enables this method to significantly reduce overall implementation costs while maintaining verification accuracy, providing practical technical support for the reliable implementation of quantum algorithms and the optimized development of compilers.

[0008] Based on the above scheme, the equivalence verification method for quantum circuits of the present invention can be further improved as follows.

[0009] Furthermore, constructing the inverse circuit of the pre-defined quantum circuit includes: The order in which all quantum gates in the preset quantum circuit are applied is reversed. If the preset quantum circuit contains parameter gates, the parameters in the parameter gates are negativeized.

[0010] The beneficial effect of adopting the above-mentioned further scheme is that reversing the order of application of all quantum gates in the preset quantum circuit and simultaneously negating the parameters when parameter gates are included ensures the accurate construction of the inverse circuit. Its advantage lies in the ability to rigorously realize the mathematical inverse transformation of quantum operations, thereby effectively canceling the original operational effects of the preset quantum circuit in the composite circuit. This direct and concise method of constructing inverse circuits avoids complex calculations or additional resource consumption, allowing subsequent equivalence verification processes to avoid relying on classical simulations or cumbersome post-processing steps. By accurately reproducing quantum state transformations, this technique significantly improves the reliability of fidelity measurements while reducing the overall verification complexity and implementation cost, providing an efficient and practical foundation for quantum circuit equivalence verification.

[0011] Furthermore, the local random circuit is composed of n single-qubit RY gates and n single-qubit RZ gates connected in sequence, and the inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected in sequence. The parameters for randomly generating local random circuits include the rotation angles of the single-qubit RY gate and the single-qubit RZ gate of the local random circuit.

[0012] The advantages of adopting the above-mentioned further scheme are: single-qubit gates have extremely low hardware implementation costs, and the simple structure of sequential connection ensures the ease of circuit construction. Dynamically randomly generated rotation angle parameters ensure that different random quantum states are produced with each execution, effectively covering the diversity of the state space. This symmetric circuit construction method guarantees that the inverse circuit can accurately cancel the original randomization operation, providing a reliable basis for subsequent fidelity measurements. Simultaneously, the structure based entirely on single-qubit gates avoids the additional complexity and errors introduced by multi-qubit gates, significantly reducing resource consumption and experimental complexity while ensuring statistical validity, and providing a stable and efficient random state preparation scheme for quantum circuit equivalence testing.

[0013] Furthermore, the execution order is as follows: first apply the local random circuit, then apply the non-preset quantum circuit, then apply the inverse circuit of the preset quantum circuit, and finally apply the inverse circuit of the local random circuit.

[0014] The advantages of adopting the above-mentioned further scheme are: the use of single-qubit gates ensures the simplicity and low resource consumption of circuit construction, while the carefully designed execution sequence constructs a complete quantum state transformation and restoration process. This process first randomizes the initial all-zero state, then sequentially undergoes transformations through the circuit to be compared and its inverse circuit, and finally attempts to restore it through an inverse random circuit. This symmetric structure allows the probability of the occurrence of the all-zero state in the measurement result to directly reflect the fidelity between the two circuits to be tested, obtaining the equivalence judgment basis without any complex post-processing, greatly simplifying the verification process and improving the testing efficiency.

[0015] 2) In a second aspect, the present invention also provides an equivalence verification system for quantum circuits, the specific technical solution of which is as follows: It includes a quantum circuit acquisition module, a first inverse circuit construction module, a second inverse circuit construction module, a circuit combination module, a parameter generation module, a probability determination module, and a verification and judgment module; The quantum circuit acquisition module is used to acquire a first quantum circuit and a second quantum circuit. Both the first quantum circuit and the second quantum circuit are quantum circuits that operate on n qubits, and the first quantum circuit and the second quantum circuit are quantum gate sequences compiled by different compilers for the same quantum algorithm. The first inverse circuit construction module is used to: construct the inverse circuit of a preset quantum circuit, wherein the preset quantum circuit is either the first quantum circuit or the second quantum circuit, and the other quantum circuit is defined as a non-preset quantum circuit; The second inverse line construction module is used to: construct local random lines and inverse lines of local random lines; The circuit combination module is used to combine local random circuits, non-preset quantum circuits, inverse circuits of preset quantum circuits, and inverse circuits of local random circuits into composite circuits according to the execution order. The parameter generation module is used to: repeatedly execute the composite circuit m times with the all-zero state as the initial quantum state, and randomly generate the parameters of the local random circuit each time it is executed; The probability determination module is used to: count the percentage of times the quantum state is all zero in the measurement results after m executions, and use this percentage as the probability p; The verification and judgment module is used to: compare the probability p with the judgment threshold δ. If the probability p is greater than or equal to the judgment threshold δ, the first quantum circuit and the second quantum circuit are determined to be equivalent; otherwise, the first quantum circuit and the second quantum circuit are determined to be inequivalent. Where n and m are both positive integers.

[0016] Based on the above scheme, the quantum circuit equivalence verification system of the present invention can be further improved as follows.

[0017] Furthermore, the first reverse circuit construction module is specifically used for: The order in which all quantum gates in the preset quantum circuit are applied is reversed. If the preset quantum circuit contains parameter gates, the parameters in the parameter gates are negativeized.

[0018] Furthermore, the local random circuit is composed of n single-qubit RY gates and n single-qubit RZ gates connected in sequence, and the inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected in sequence. The parameters for randomly generating local random circuits include the rotation angles of the single-qubit RY gate and the single-qubit RZ gate of the local random circuit.

[0019] Furthermore, the execution order is as follows: first apply the local random circuit, then apply the non-preset quantum circuit, then apply the inverse circuit of the preset quantum circuit, and finally apply the inverse circuit of the local random circuit.

[0020] 3) In a third aspect, the present invention also provides an electronic device, the electronic device including a processor coupled to a memory, the memory storing at least one computer program, the at least one computer program being loaded and executed by the processor, so as to enable the electronic device to implement any of the above-mentioned quantum circuit equivalence verification methods.

[0021] 4) In a fourth aspect, the present invention also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the equivalence verification method for any of the above-mentioned quantum circuits.

[0022] It should be noted that the beneficial effects of the technical solutions of the second to fourth aspects of the present invention and their corresponding possible implementations can be found in the above description of the technical effects of the first aspect and its corresponding possible implementations, and will not be repeated here. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments of the present invention will be briefly introduced below: Figure 1 This is a flowchart illustrating a quantum circuit equivalence verification method according to an embodiment of the present invention. Figure 2 This is a composite circuit used in this invention to detect the equivalence between two lines, U and V; Figure 3 This is a schematic diagram of quantum circuit U; Figure 4 This is a schematic diagram of quantum circuit V; Figure 5 Reverse route A schematic diagram; Figure 6 This is a schematic diagram of a composite circuit; Figure 7 This is a schematic diagram of the structure of a quantum circuit equivalence verification system according to an embodiment of the present invention; Figure 8 This is a schematic diagram of the structure of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0024] The principles and features of the present invention are described below. The examples given are only for explaining the present invention and are not intended to limit the scope of the present invention.

[0025] The technical solution of the present invention and how the technical solution of the present invention solves the above-mentioned technical problems are described in detail below with specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments. The embodiments of the present invention will now be described with reference to the accompanying drawings.

[0026] like Figure 1 As shown, an embodiment of the present invention provides a method for verifying the equivalence of quantum circuits, comprising: S1. Obtain the first quantum circuit and the second quantum circuit. Both the first quantum circuit and the second quantum circuit are quantum circuits that operate on n qubits. The first quantum circuit and the second quantum circuit are quantum gate sequences obtained by different compilers for the same quantum algorithm, where n is a positive integer.

[0027] In the field of quantum computing, quantum circuits are the concrete carriers for implementing quantum algorithms, composed of a series of quantum gates combined in a specific order. Both the first and second quantum circuits operate on n qubits, meaning each circuit is designed to operate on a quantum system consisting of n qubits. Here, n is a positive integer representing the number of qubits, determining the circuit's size and computational power. The quantum gates in each quantum circuit include single-qubit gates and multi-qubit gates, which operate on one or more qubits respectively, performing computational tasks by changing the quantum state. For example, when n=1, the circuit may only contain single-qubit gates such as Hadamard gates or rotation gates; when n>1, the circuit may involve two-qubit gates such as CNOT gates or more complex entanglement gates to handle multi-qubit interactions. The depth and complexity of the circuit increase with the value of n, but the core is that all operations are confined to these n qubits, ensuring that the circuit performs transformations in n-dimensional Hilbert space. This design allows quantum circuits to fully utilize the properties of quantum superposition and entanglement, achieving efficient computation, while providing a clear qubit-number basis for equivalence testing.

[0028] The first and second quantum circuits are quantum gate sequences compiled by different compilers for the same quantum algorithm. The quantum algorithm can be a quantum Fourier transform algorithm, Grover's search algorithm, a variable quantum eigenvalue solver, a quantum approximation optimization algorithm, a Hamiltonian simulation algorithm, or a quantum machine learning algorithm, etc., and can be set according to the actual situation. This reflects the compilation process of the quantum algorithm from logical design to hardware implementation. Quantum algorithms such as Shor's algorithm or Grover's algorithm are usually described in high-level logic form, but when actually running on a quantum computer, these logical operations need to be transformed into specific quantum gate sequences by a compiler. Different compilers, based on their own optimization strategies, target hardware constraints, or gate set preferences, may generate quantum gate sequences with different structures. For example, one compiler may preferentially use RY and RZ gates to reduce errors, while another compiler may use RX and CNOT gates to improve execution speed. Although the compiled results differ in gate sequences and connection methods, they should theoretically be equivalent to the original algorithm, that is, producing the same output state for any input state. Therefore, verifying the equivalence of these circuits is crucial to ensure the reliability of the algorithm and the correctness of the compiler. This process involves comparing the global phase and matrix representation of the circuits, but traditional methods are not applicable due to high resource consumption. This invention directly verifies equivalence in a hardware-efficient manner, thereby improving the reliability of the compilation process.

[0029] S2. Construct the inverse circuit of the preset quantum circuit, wherein the preset quantum circuit is either the first quantum circuit or the second quantum circuit, and the other quantum circuit is defined as a non-preset quantum circuit.

[0030] The construction of the inverse circuit of the preset quantum circuit includes: reversing the order in which all quantum gates in the preset quantum circuit are applied; if the preset quantum circuit contains parameter gates, then the parameters in the parameter gates are negativeed. Specifically, this includes: S20. Identify all quantum gates contained in the preset quantum circuit and their execution order, which records the application order of the quantum gates from initial to final. Then, completely reverse the application order of the entire quantum gates; that is, the quantum gate applied first in the original circuit becomes the last applied in the reverse circuit, and the quantum gate applied last in the original circuit becomes the first applied in the reverse circuit. This step ensures the reverse reconstruction of the operation timing.

[0031] S21. If the preset quantum circuit contains parameter gates, then the parameter negation operation needs to be performed on each parameter gate, based on the reversed order. A parameter gate is a quantum gate whose operation is defined by specific angle or numerical parameters, such as an RY gate or an RZ gate. The negation operation reverses the sign of the parameter, turning positive parameters into negative parameters and negative parameters into positive parameters. This mathematical processing corresponds to the inverse operation of a quantum gate, because for a unitary gate, its inverse matrix can be obtained by negating the parameter. For example, the inverse operation of an RY gate with a rotation angle of θ is an RY gate with a rotation angle of -θ.

[0032] By combining the two key operations of reversing the order and negating the parameters, the final constructed circuit is mathematically rigorously equivalent to the inverse operation of the original pre-defined quantum circuit. When this inverse circuit is connected in series with the original circuit, the overall effect should be a unit operation, that is, it does not produce a net change in the quantum state.

[0033] For example, suppose a pre-defined quantum circuit V consists of three quantum gates in sequence: an RY gate applying an angle of π / 2, a CNOT gate, and an RZ gate applying an angle of π / 4. When constructing its inverse circuit, the gate order is first completely reversed, becoming RZ gate, CNOT gate, and RY gate. Next, the parameter gates in the circuit are processed: the angle π / 2 of the RY gate is negatively taken as -π / 2, and the angle π / 4 of the RZ gate is negatively taken as -π / 4. For non-parametric gates like the CNOT gate, its inverse is itself, requiring no parameter changes. The final inverse circuit executes in the following order: first, the RZ gate is applied with an angle of -π / 4; then the CNOT gate is applied; and finally, the RY gate is applied with an angle of -π / 2. This inverse circuit mathematically strictly cancels out the operational effects of the original circuit V.

[0034] S3. Construct a local random circuit and its inverse circuit. The local random circuit is composed of single-qubit gates. The local random circuit is composed of n single-qubit RY gates and n single-qubit RZ gates connected in sequence. The inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected in sequence.

[0035] The construction of local random circuits and their inverses specifically includes: S30. Locally random circuits are designed for quantum circuits operating on n qubits, meaning the circuit operates on a quantum system containing n qubits. A locally random circuit is constructed from single-qubit gates; specifically, it consists of n single-qubit RY gates and n single-qubit RZ gates connected sequentially. These gates are applied to each qubit in sequence: first an RY gate is applied to each qubit, then an RZ gate is applied to each qubit. The rotation angle parameters of the RY and RZ gates are dynamically and randomly generated during each construction, with each parameter independently and randomly selected from a uniform distribution from 0 to 2π, ensuring the randomness and diversity of the circuit in each execution. This design allows locally random circuits to transform an initial all-zero quantum state into a random quantum state, thus providing efficient state preparation in equivalence checks and avoiding the exponential resource consumption of classical simulations.

[0036] S31. The construction of the inverse circuit of the local random circuit follows the general principle of quantum circuit inversion, that is, it is achieved by reversing the application order of all quantum gates in the original local random circuit and negating the parameters of the gates. Specifically, the inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected sequentially. These gates are applied to each qubit in sequence, that is, first an RZ gate is applied to each qubit, and then an RY gate is applied to each qubit. The rotation angle parameter of the RZ gate is set to the negative value of the corresponding rotation angle of the RZ gate in the original local random circuit, and the rotation angle parameter of the RY gate is set to the negative value of the corresponding rotation angle of the RY gate in the original local random circuit. This parameter negation operation ensures that the inverse circuit mathematically strictly cancels the operational effect of the original local random circuit, making the overall transformation of the composite circuit close to a unit operation, thus providing a reliable basis for equivalence testing.

[0037] For example, suppose we want to generate a locally random circuit for a quantum circuit on a 2-qubit quantum circuit. First, we randomly generate a set of rotation angle parameters; for example, for the first qubit, the RY gate angle is... The RZ gate angle is For the second qubit, the RY gate angle is... The RZ gate angle is The execution order of the local random circuit is as follows: first apply all RY gates (i.e., qubit 1's...). And 2 qubits Then apply all RZ gates (i.e., the gates of qubit 1). And 2 qubits Then, its inverse circuit is constructed: the execution order of the inverse circuit is to first apply all RZ gates (i.e., the gates of qubit 1). And 2 qubits Then apply all RY gates (i.e., the gates of qubit 1). And 2 qubits Through this construction method, the quantum state can be effectively restored when the local random circuit and its inverse circuit work together, ensuring the accuracy and efficiency of the equivalence test. The entire implementation process relies on dynamic parameter generation and inverse operations, guaranteeing the feasibility and low-cost advantage of the method.

[0038] S4. Combine the local random circuit, the non-preset quantum circuit, the inverse of the preset quantum circuit, and the inverse of the local random circuit into a composite circuit according to the execution order; wherein, the execution order is: first apply the local random circuit, then apply the non-preset quantum circuit, then apply the inverse of the preset quantum circuit, and finally apply the inverse of the local random circuit, specifically: On a quantum computer, four circuit components—a locally random circuit, a non-preset quantum circuit, the inverse of the preset quantum circuit, and the inverse of the locally random circuit—are sequentially connected to form a complete composite circuit. The execution order of this composite circuit is strictly defined as: first, the locally random circuit is applied; then, the non-preset quantum circuit is applied; then, the inverse of the preset quantum circuit is applied; and finally, the inverse of the locally random circuit is applied. This order ensures that the quantum state, starting from an initial all-zero state, undergoes a series of transformations and is ultimately measured to extract equivalent information. Technically, the composite circuit is constructed using a quantum programming framework or hardware instructions, where each circuit component is treated as an independent sequence of quantum gates. The locally random circuit consists of single-qubit gates, specifically n single-qubit RY gates and n single-qubit RZ gates. These gates are applied sequentially to each qubit, and their rotation angle parameters are dynamically and randomly generated each time the circuit is executed. The non-preset quantum circuit is either the first or second quantum circuit, depending on the choice of the preset quantum circuit; it represents the sequence of quantum gates to be tested. The inverse circuit of a predefined quantum circuit is constructed by reversing the order in which all quantum gates are applied in the predefined quantum circuit and negating the parameters of the gates to ensure that the operations of the original predefined quantum circuit are mathematically canceled out. The inverse circuit of a localized random circuit is also composed of single-qubit gates, including n single-qubit RZ gates and n single-qubit RY gates, with their parameters negated to restore the effect of the localized random circuit. In combination, these circuits are cascaded into the same quantum circuit, operating on the same n qubits. For example, in a quantum software development kit, this can be achieved by sequentially adding the gate sequences of the localized random circuit, the gate sequences of the non-predefined quantum circuit, the gate sequences of the inverse circuit of the predefined quantum circuit, and the gate sequences of the inverse circuit of the localized random circuit. When executing a composite circuit, the quantum computer starts with a zero-state initialization, progressively applies each component circuit, and finally performs a measurement. The key to this sequence is that the local random circuit transforms the initial state into a random quantum state, the inverse circuits of the non-preset quantum circuit and the preset quantum circuit work together to reflect the difference between the two, and the inverse circuit of the local random circuit is used to restore the state, so that the measurement result can directly reflect the fidelity between the non-preset quantum circuit and the preset quantum circuit.

[0039] For example, a non-preset quantum circuit U is composed of Hadamard gates and CNOT gates, while a preset quantum circuit V is composed of a series of RY gates and CZ gates, and V is selected as the preset quantum circuit. First, a locally random circuit L is constructed; for example, for each qubit, a random angle is first applied using RY gates. and Then apply the RZ gate to randomize the angle. and Then, the inverse circuit of the predefined quantum circuit V is constructed. This is achieved by reversing the order of all gates in V and negating the parameter gates. Next, the inverse of the local random circuit L is constructed. For example, for each qubit, first apply the RZ gate angle. and Then apply the RY gate angle and Finally, L, U, and They are sequentially combined into composite circuits. When executed on a quantum computer, starting with a completely zero state, L is first applied to generate a random state, then U is applied to transform the state, and then... Perform inverse transform, and finally apply. The process attempts to restore the original state. If U and V are equivalent, the probability of measuring the all-zero state is close to 1; otherwise, the probability is low. This process is executed directly in hardware, avoiding the exponential resource consumption of classical simulation and achieving low-cost and efficient verification.

[0040] S5. Using the all-zero state as the initial quantum state, the composite circuit is executed m times repeatedly. During each execution, the parameters of the local random circuit are randomly generated. The parameters of the randomly generated local random circuit include the rotation angle of the single-qubit RY gate and the rotation angle of the single-qubit RZ gate of the local random circuit. S6. Calculate the percentage of times the quantum state is all zero in the measurement results after m executions, and use this percentage as the probability p; where m is a positive integer.

[0041] S5 and S6 are explained as follows: 1) Initialize a quantum system containing n qubits on a quantum computer, setting all qubits to the ground state zero state, i.e., all zero states. This initial state is the standard starting point for quantum computing, ensuring that each execution begins from the same quantum state, providing a consistent benchmark for subsequent equivalence checks.

[0042] 2) Set the number of samples, m, whose value is determined according to the accuracy requirements, and is usually set to 1,000,000 to meet most application scenarios. The number of samples, m, determines the reliability of the statistical results. The larger the value of m, the smaller the variance of the probability estimate and the more accurate the result. In the technical implementation, m is passed as an input parameter to the quantum control program to control the number of loop executions.

[0043] 3) For each execution, with indices from 1 to m, the quantum computer performs the following operations: During each execution of the composite circuit, it randomly generates the rotation angles of the single-qubit RY gates and the single-qubit RZ gates. The local random circuit consists of n single-qubit RY gates and n single-qubit RZ gates, thus requiring the generation of 2^n rotation angle parameters. Each parameter is independently and randomly drawn from a uniform distribution from 0 to 2π, for example, generated in real-time in the quantum control software using a pseudo-random number generator. These parameters are regenerated in each execution, ensuring the randomness and diversity of the local random circuit and avoiding bias.

[0044] 4) After generating the parameters, the quantum computer constructs local random circuits and their inverses based on these parameters. The gate sequence of the local random circuit is applied sequentially; specifically, an RY gate is applied to each qubit first, followed by an RZ gate. The inverse of the local random circuit applies the gate sequence in the reverse order, with the parameters negativeed: an RZ gate (negating the angle) is applied to each qubit first, followed by an RY gate (negating the angle). Simultaneously, non-preset quantum circuits and the inverses of the preset quantum circuits are integrated into the composite circuit as fixed components.

[0045] 5) Combine the complete gate sequence of the composite circuit in the execution order. Specifically, first apply the local random circuit, then the non-preset quantum circuit, then the inverse of the preset quantum circuit, and finally the inverse of the local random circuit. In quantum hardware, this sequence is implemented through quantum gate operations, with each gate acting sequentially on its corresponding qubit. When executing the composite circuit, the quantum state starts from a state of all zeros, is transformed into a random quantum state through the local random circuit, then transformed through the non-preset quantum circuit and the inverse of the preset quantum circuit, and finally attempts to restore it through the inverse of the local random circuit. If the non-preset quantum circuit and the preset quantum circuit are equivalent, the quantum state should be restored to the state of all zeros; otherwise, the quantum state will deviate.

[0046] 6) After execution, the quantum computer measures all n qubits, obtaining a measurement result (0 or 1) for each qubit. The measurement result is recorded as an n-bit binary string, such as "00" for a 2-qubit system. A 2-qubit system, consisting of two qubits, is a typical test platform for verifying the equivalence of quantum gates. On this system, quantum circuits can be represented by the implementation of basic operations such as entanglement gate compilation optimization and quantum state preparation. The local random circuit in the technical solution will be configured with two single-qubit RY gates and two single-qubit RZ gates. The construction and execution of the composite circuit are strictly limited within the framework of the 2-qubit system, and equivalence is determined by statistically analyzing the probability of the |00> state in the measurement result. The measurement result of each execution is stored for subsequent statistical analysis.

[0047] 7) After repeating the above process m times, count the number of times the all-zero state (i.e., the string where all qubits are 0) appears in all measurement results. Calculate the percentage of all-zero states, that is, divide the number of all-zero states by m to get the probability p. This probability p directly reflects the fidelity between the non-preset quantum circuit and the preset quantum circuit, and is used for equivalence determination. The above process specifically refers to: randomly generating the rotation angles of all single-qubit RY gates and RZ gates required for this execution; constructing a local random circuit and its inverse circuit based on these parameters; executing a composite circuit composed of the local random circuit, the non-preset quantum circuit, the inverse circuit of the preset quantum circuit, and the inverse circuit of the local random circuit in sequence; and finally measuring all qubits and recording the results.

[0048] For example, the number of samplings m = 1,000,000. During the first execution, the rotation angles of the RY gate and RZ gate for a single qubit are randomly generated: for example, the RY gate angle for qubit 1 is 0.5π, and the RZ gate angle is 1.2π; the RY gate angle for qubit 2 is 0.8π, and the RZ gate angle is 0.3π. The composite circuit is executed sequentially: first, a local random circuit (RY(0.5π) and RY(0.8π) are applied to the two qubits, then RZ(1.2π) and RZ(0.3π)) are applied; then a non-preset quantum circuit U (e.g., composed of Hadamard gates and CNOT gates) is applied; then the inverse of the preset quantum circuit V is applied (e.g., by reversing the gate order of V and taking negative parameters); finally, the inverse of the local random circuit (RZ(-1.2π) and RZ(-0.3π) are applied to the two qubits, then RY(-0.5π) and RY(-0.8π)) are applied. After execution, the qubits are measured, assuming a result of "00". This process is repeated 1,000,000 times. Each time, the rotation angles of all single-qubit RY gates and single-qubit RZ gates are randomly regenerated. The final count of all-zero states is 999,000, resulting in a probability p = 0.999. This probability is compared to a decision threshold δ to determine equivalence. The entire implementation relies on the parallel execution of quantum hardware and random parameter generation, ensuring the feasibility and efficiency of the method.

[0049] S7. Compare the probability p with the decision threshold δ. If the probability p is greater than or equal to the decision threshold δ, then the first quantum circuit and the second quantum circuit are considered equivalent; otherwise, the first quantum circuit and the second quantum circuit are considered not equivalent. Specifically: After completing m executions of the composite circuit and calculating the proportion p of all-zero states in the measurement results, the numerical comparison logic is automatically executed. The decision threshold δ is a preset constant value close to 1, typically set to 0.999, representing the lowest acceptable limit for the fidelity of the two circuit operations in a statistically significant sense. In the quantum control program or classical post-processing module, the calculated probability p is compared with the stored decision threshold δ. If the probability p is greater than or equal to the decision threshold δ, i.e., p ≥ δ, the program automatically determines that the first and second quantum circuits are equivalent in a quantum operational sense. The physical meaning of this conclusion is that the difference in output states produced by the two circuits for any input quantum state is negligible, and their operation matrices are consistent within experimental precision. Conversely, if the probability p is less than the decision threshold δ, i.e., p < δ, the program determines that the first and second quantum circuits are not equivalent. This indicates that there is a non-negligible difference in the transformation of quantum states between the two circuits, which may originate from compilation errors, gate sequence mismatches, or parameter errors.

[0050] For example, a decision threshold δ is set to 0.999. After repeatedly executing the composite circuit m = 1,000,000 times, the number of times the measurement result is in the all-zero state is counted as 999,200, and the calculated probability p is 0.9992. Since 0.9992 is greater than the decision threshold 0.999, the condition p ≥ δ is satisfied, so the decision result is automatically output: the first quantum circuit U and the second quantum circuit V are equivalent. Conversely, if the number of all-zero states is counted as 998,500, the calculated probability p is 0.9985. Since 0.9985 is less than the decision threshold 0.999, the condition p < δ is satisfied, and circuits U and V are determined to be non-equivalent. This decision mechanism is entirely based on statistical data and preset thresholds and is completed automatically without manual intervention. This ensures the objectivity of the test results and demonstrates the feasibility and practicality of the method in a real quantum computing environment. The entire comparison and decision process constitutes the final decision-making link in the quantum circuit equivalence test, providing a key quality assurance for the reliable compilation and hardware verification of quantum algorithms.

[0051] During the development of a quantum compiler, it is necessary to verify whether quantum circuits generated by different compilation strategies maintain functional consistency. Taking the Quantum Fourier Transform (QFT) algorithm as an example, for a 4-qubit system, compiler A generates the first quantum circuit U, which adopts a CNOT gate architecture based on adjacent qubits; simultaneously, compiler B generates the second quantum circuit V, which adopts a CNOT gate architecture based on symmetric qubits to optimize hardware connectivity. The inverse circuit of the preset quantum circuit V is then constructed. This is achieved by reversing the order in which all quantum gates in V are applied and negating the parameters of the parameter gates. Subsequently, a local random circuit L and its inverse circuit are constructed. L is composed of four single-qubit RY gates and four single-qubit RZ gates connected sequentially. It consists of four single-qubit RZ gates and four single-qubit RY gates connected sequentially. These components are then combined in sequence to form a composite circuit: first L, then U, and then... Finally, the application Using an all-zero state as the initial quantum state, the composite circuit was repeatedly executed 1,000,000 times on a quantum computer. During each execution, the rotation angles of all single-qubit RY gates and single-qubit RZ gates were randomly generated. The statistical measurement showed that the proportion of all-zero states was 0.9995, a probability p greater than the judgment threshold δ=0.999, thus determining the two circuits to be equivalent. This verification result confirms the correctness of compiler B's optimization strategy and provides crucial evidence for compiler performance evaluation. The 4-qubit system refers to a quantum computing platform composed of four qubits, and all gate operations of the quantum circuit operate on this system. In practical implementation, this system can support more complex quantum algorithms such as quantum error correction coding or variable quantum algorithms with specific structures. When performing the equivalence test, the local random circuit will be configured with four single-qubit RY gates and four single-qubit RZ gates, and its parameter generation, circuit combination, and measurement processes maintain the operational consistency of the 4-qubit system.

[0052] In quantum machine learning applications, a variable quantum circuit for data classification has two different parameterization implementations. For a 3-qubit system, data scientists designed a first quantum circuit U using an RY-gate-based parameterization layer structure; simultaneously, they designed a second quantum circuit V using an RZ-gate-based parameterization layer structure to explore different feature extraction strategies. A 3-qubit system refers to a quantum register containing three qubits, where both the first and second quantum circuits are sequences of quantum gates operating on these three qubits. This system provides an execution environment for algorithms such as quantum Fourier transform or quantum phase estimation, where the single-qubit and two-qubit gate operations within the circuit are confined to the Hilbert space of these three qubits. When constructing composite circuits, the local random circuit and its inverse are also configured with three single-qubit RY gates and three single-qubit RZ gates to ensure that all operations remain within the system dimension.

[0053] During the verification process, U is selected as the preset quantum circuit, and its inverse circuit is constructed. This is achieved by reversing the gate sequence and negating the parameters of all gates. Then, a local random circuit L and its inverse circuit are constructed. L is composed of three single-qubit RY gates and three single-qubit RZ gates connected sequentially. Connecting L, V, ... and Combine them in sequence to form a composite circuit.

[0054] Using the all-zero state as the initial quantum state, the composite circuit was repeatedly executed 1,000,000 times on a quantum processor. During each execution, the rotation angle parameters of all single-qubit gates were dynamically and randomly generated. Statistical measurements showed that the proportion of the all-zero state was 0.998, a probability p less than the decision threshold δ=0.999, leading the system to determine that the two circuits were not equivalent. This result demonstrates a significant difference in quantum state transformation between the two parameterization schemes, providing a crucial decision-making basis for the structure selection of machine learning models and avoiding performance degradation caused by circuit inequivalence.

[0055] Another embodiment will be used to illustrate the equivalence verification method of a quantum circuit according to the present invention, specifically: For a quantum circuit to be tested with two n qubits (denoted as circuit) With the line First, construct the circuit. The reverse line (denoted as line) The method for reversing the circuit involves inverting the order in which all quantum gates are applied, and if a parameter gate is included, negating the parameter. Simultaneously, a local random circuit is constructed, consisting of n single-qubit RY gates (Y-axis rotation gates) and n single-qubit RZ gates (Z-axis rotation gates). And the inverse line corresponding to this local random line. The rotation angles of the RY and RZ gates The parameters are determined using a dynamic, random generation method, and their values ​​range from 0 to 2. Between. The line ,line ,line and lines Composed sequentially to form a composite circuit for equivalence verification. This indicates the adoption of industry convention, where the part executed first is placed on the right side of the expression, and the part executed later is placed on the left side. The graphical representation of this compound line is as follows: Figure 2 As shown.

[0056] Among them, the RY and RZ gates on the far left together form a local random circuit. The RZ and RY gates on the far right together form the corresponding reverse circuit. .

[0057] Specifically, for a quantum circuit with two n qubits to be detected, denoted as the first quantum circuit U and the second quantum circuit V, the inverse circuit of the preset quantum circuit is first constructed. When the second quantum circuit V is selected as the preset quantum circuit, its inverse circuit is denoted as... If the first quantum circuit U is chosen as the preset quantum circuit, then its inverse circuit is denoted as... The method for constructing the inverse of a predefined quantum circuit involves completely reversing the order in which all quantum gates are applied. If the circuit contains parameter gates, the parameters are simultaneously negativeed. Simultaneously, a local random circuit L is constructed, consisting of n single-qubit RY gates and n single-qubit RZ gates connected sequentially, along with the corresponding inverse circuit. The rotation angle parameters of the RY and RZ gates are determined using a dynamically and randomly generated method, with each parameter... The value of is strictly limited to the interval [0, 2π]. Local random circuit L, non-preset quantum circuit, inverse circuit of preset quantum circuit, and inverse circuit of local random circuit. The quantum circuits are arranged in the order of execution to form a composite circuit C for equivalence verification. When the preset quantum circuit is V, the complete mathematical expression of the composite circuit is: When the preset quantum circuit is At that time, the complete mathematical expression of the composite circuit is C= Following quantum computing industry conventions, the expression for the composite circuit places the first part executed on the right and the second part on the left. The graphical representation of this composite circuit has a clearly symmetrical structure: the leftmost n RY gates and n RZ gates are sequentially connected to form a localized random circuit. The rightmost n RZ gates and n RY gates are connected in sequence to form the corresponding reverse circuit. The middle part consists of the non-preset quantum circuit and the inverse of the preset quantum circuit, forming a complete verification framework.

[0058] Set the number of samples, m. The specific value depends on the required precision; the higher the precision, the larger the value of m. Generally, setting it to 1,000,000 is sufficient. Set the equivalence determination threshold, typically set to 0.999.

[0059] In quantum state Starting from the initial state, the circuit is executed m times, and the measurement results are statistically analyzed. During each execution, the parameters in the local random circuit are... The value can be randomly selected. The probability of all zeros in the statistical measurement results is calculated. If this probability is greater than the judgment threshold δ, the two lines to be tested are considered equivalent; otherwise, they are considered inequivalent. Specifically: using the all-zero state... As the initial quantum state, the composite circuit is repeatedly executed m times, and the measurement results are statistically analyzed. During each execution, the parameters in the local random circuit L are re-randomized. After m executions, the measurement results show the presence of a completely zero state. The frequency of occurrence of each quantum circuit is calculated as the probability p. If the probability p is greater than or equal to the decision threshold δ, the first quantum circuit U and the second quantum circuit V are determined to be equivalent; otherwise, they are determined to be inequivalent.

[0060] Due to local random lines and its reverse route Containing only single-qubit gates, the circuit depth is 0, therefore the depth of this composite circuit is [the depth of the circuit]. and The sum of the line depths. Number of qubits and line depth. and The number of bits is the same, n, and the overall cost is very low. Specifically, due to the local random line L and its inverse line... Since the circuit depth of a single-qubit gate is negligible compared to that of a multi-qubit gate, the effective depth of this composite circuit mainly depends on the first quantum gate. The sum of the line depths of the first and second quantum circuits V. In terms of quantum resource consumption, the number of qubits required by this method is equal to the number of qubits required by the first quantum circuit. Second quantum circuit The number of qubits is exactly the same, n, which significantly reduces the overall implementation cost compared to existing technologies that require additional qubits.

[0061] Specifically, let's assume the first quantum circuit The depth is The depth of the second quantum circuit V is Then the theoretical depth of composite line C is When executed on a quantum processor, the parameters of the local random circuit L need to be reinitialized each time the composite circuit C is run. These parameters are generated in real time using a pseudo-random number generator to ensure the randomness of each execution. Statistical results obtained through a large number of repeated executions (m times) can reflect the first quantum circuit with high confidence. Second quantum circuit The actual fidelity between them, when The two circuits can be determined to be functionally equivalent immediately. This method, based on random parameters and statistical verification, ensures the accuracy of the test while minimizing the consumption of quantum resources, achieving a truly low-cost quantum circuit equivalence test.

[0062] The equivalence test principle of this invention is: local random circuits can convert the initial quantum state Transform into a random quantum state Following the subsequent routes and and the inverse of local random lines Afterwards, the probability of obtaining all zeros is... The probability value is... and The fidelity between them reflects the degree of similarity between the two. If and Equivalent, then That is, the probability of obtaining all zeros is 1; if and If they are not equivalent, then the value of this probability will be less than 1. Specifically: Local Random Line The initial all-zero quantum state can be Transform into a random quantum state The random quantum state then passes sequentially through a non-preset quantum circuit. Inverse circuit of a pre-set quantum circuit and the inverse of a local random line. The final quantum state is Measuring this final quantum state yields a completely zero state. The probability is: According to the principles of quantum mechanics, this probability Mathematically, it is strictly equal to the operation. and operation The average fidelity between them, i.e.: The integral traverses all random quantum states. This probability value Precisely reflects two quantum circuits and The degree of similarity between them.

[0063] If the first quantum circuit Second quantum circuit Complete equivalence, i.e., satisfying Then there is ,in This indicates a unit operation. The probability in this case is: That is, the probability of measuring a completely zero state is 1. If the first quantum circuit... Second quantum circuit If they are not equivalent, then At this point, the probability The value will be strictly less than 1. The probability estimate obtained through extensive sampling... With the judgment threshold By comparing the two quantum circuits, a reliable judgment can be made on their equivalence.

[0064] The detection principle ensures that the present invention can obtain fidelity information by directly statistically analyzing the frequency of all-zero states in the measurement results, without the need for complex post-processing, thereby significantly reducing the implementation cost.

[0065] The present invention will be further illustrated by the following embodiments, with an experiment to determine the equivalence between two compilation schemes for a specific quantum gate as a specific embodiment. The specific operation process is as follows: For the same quantum gate operation, different quantum compilers may, based on their respective optimization strategies, target gate sets, and hardware constraints, compile quantum circuits that differ significantly in their quantum gate sequence structure but are functionally equivalent. We take the controlled rotation gate, a common feature in quantum computing, as an example. For example, this gate can control the rotation of a qubit around the target qubit by a π-angle Y-axis. Two different compilers generated the following compilation results for this quantum gate operation: The quantum circuit generated by the first compilation scheme is denoted as the first quantum circuit. This circuit is implemented using a standard CNOT gate combination and a single-qubit rotating gate. Function. The quantum circuit generated by the second compilation scheme is denoted as the second quantum circuit. This circuit achieves the same quantum operation by optimizing the gate sequence and parameterizing the gate combination. These two quantum circuits... and All of them act on Quantum circuits on qubits, and all are aimed at realizing The same quantum algorithm is used to generate quantum gate sequences compiled by different compilers. These two types of circuits... and The graphical representations are as follows: Figure 3 and Figure 4 As shown.

[0066] In this embodiment, by applying the quantum circuit equivalence verification method of the present invention, the circuits generated by these two different compilation schemes can be verified. and Whether they are functionally equivalent. This method achieves low-cost, high-efficiency equivalence verification on a quantum computer by constructing the inverse circuit of a predefined quantum circuit, building a composite circuit containing local random circuits and their inverse circuits, performing multiple measurement statistics, and comparing probabilities with thresholds. The specific operation process and implementation details of this verification method will be explained in detail below.

[0067] To verify the first quantum circuit Second quantum circuit To determine whether they are equivalent, first construct the inverse of the preset quantum circuit. When choosing the second quantum circuit... When used as a pre-defined quantum circuit, its inverse circuit is constructed. The specific method is to The order in which all quantum gates are applied is completely reversed, and if If a parameter gate is included, its parameter value is negative. Reverse circuit Graphical representation such as Figure 5 As shown.

[0068] Then, a local random circuit is constructed. and its reverse route ,in Depend on A single quantum bit Door and A single quantum bit The doors are connected in sequence to form a structure. Depend on A single quantum bit Door and A single quantum bit The doors are connected in sequence. Here Represents the set of parameters for all revolving doors. Each parameter is generated independently and randomly each time it is executed.

[0069] Local random lines First quantum circuit The inverse circuit of the second quantum circuit Inverse of local random circuit Combined into composite circuits according to the execution order This composite circuit Number of qubits used With the first quantum circuit Second quantum circuit The number of qubits is exactly the same. Composite circuits, such as Figure 6 As shown.

[0070] In quantum state As the initial state, repeatedly execute the composite circuit. total Next, that is And each execution uses a local random circuit. and its reverse route All rotation angle parameters All values ​​are regenerated randomly, and the range of values ​​for each parameter is [value range missing]. .

[0071] This invention differs fundamentally from traditional verification methods based on ZX graphs and decision graphs. It employs a direct verification strategy based on quantum computer hardware, fundamentally avoiding the exponential computational resource consumption required by classical simulations in traditional methods. While maintaining the advantages of quantum hardware verification, this method achieves cost optimization through structural innovation. Specifically, it borrows the core idea of ​​the RH algorithm, which uses a localized random circuit. This circuit efficiently generates random quantum states through random combinations of single-qubit gates, avoiding the exponential cost of preparing random quantum states in traditional methods. However, this method makes a crucial improvement: it incorporates an inverse circuit that strictly corresponds to the localized random circuit into the overall circuit structure. This improvement significantly simplifies the process of extracting fidelity information. While the RH algorithm requires complex post-processing of measurement results to obtain fidelity information, this method directly obtains the fidelity by statistically analyzing the probability of all-zero states in the measurement results, greatly reducing experimental complexity. In terms of the verification mechanism, this method differs fundamentally from the RH algorithm. The RH algorithm uses a quantum generative adversarial network (GAN) architecture to determine circuit equivalence. This mechanism has significant limitations: it requires twice the number of qubits as the circuit being tested and necessitates the introduction of additional circuit modules to entangle the two circuits. Furthermore, the RH algorithm requires pre-training of the discriminator in the QGAN, increasing both algorithm complexity and implementation cost. This method, however, verifies the equivalence of two circuits using the fundamental principle of circuit inversion, requiring only the same number of qubits as the circuit being tested. Specifically, for two n-qubit circuits, this method requires only n qubits for verification, while the RH algorithm requires 2n qubits. This halving of quantum resource requirements, combined with the advantage of not requiring pre-training, significantly reduces the overall verification cost, providing a more feasible technical solution for the practical application of quantum circuit equivalence testing.

[0072] Although the steps have been numbered in the above embodiments, they are only specific embodiments given by the present invention. Those skilled in the art can adjust the execution order of the steps according to the actual situation, which is also within the protection scope of the present invention. It can be understood that some embodiments may include some or all of the above embodiments.

[0073] like Figure 7 As shown, an equivalence verification system 200 for quantum circuits according to an embodiment of the present invention includes a quantum circuit acquisition module 201, a first inverse circuit construction module 202, a second inverse circuit construction module 203, a circuit combination module 204, a parameter generation module 205, a probability determination module 206, and a verification and judgment module 207. The quantum circuit acquisition module 201 is used to: acquire a first quantum circuit and a second quantum circuit, both of which are quantum circuits operating on n qubits, and the first quantum circuit and the second quantum circuit are quantum gate sequences compiled by different compilers for the same quantum algorithm; The first inverse circuit construction module 202 is used to: construct the inverse circuit of a preset quantum circuit, wherein the preset quantum circuit is either the first quantum circuit or the second quantum circuit, and the other quantum circuit is defined as a non-preset quantum circuit; The second inverse line construction module 203 is used to: construct local random lines and inverse lines of local random lines; The circuit combination module 204 is used to combine local random circuits, non-preset quantum circuits, inverse circuits of preset quantum circuits, and inverse circuits of local random circuits into composite circuits according to the execution order. The parameter generation module 205 is used to: repeatedly execute the composite circuit m times with the all-zero state as the initial quantum state, and randomly generate the parameters of the local random circuit each time it is executed; The probability determination module 206 is used to: count the percentage of times the quantum state is all zero in the measurement results after m executions, and use it as the probability p; The inspection and judgment module 207 is used to: compare the probability p with the judgment threshold δ. If the probability p is greater than or equal to the judgment threshold δ, the first quantum circuit and the second quantum circuit are determined to be equivalent; otherwise, the first quantum circuit and the second quantum circuit are determined to be inequivalent. Where n and m are both positive integers.

[0074] Optionally, in the above technical solution, the first reverse circuit construction module 202 is specifically used for: The order in which all quantum gates in the preset quantum circuit are applied is reversed. If the preset quantum circuit contains parameter gates, the parameters in the parameter gates are negativeized.

[0075] Optionally, in the above technical solution, the local random circuit is composed of n single-qubit RY gates and n single-qubit RZ gates connected in sequence, and the inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected in sequence. The parameters for randomly generating local random circuits include the rotation angles of the single-qubit RY gate and the single-qubit RZ gate of the local random circuit.

[0076] Optionally, in the above technical solution, the execution order is as follows: first apply the local random circuit, then apply the non-preset quantum circuit, then apply the inverse circuit of the preset quantum circuit, and finally apply the inverse circuit of the local random circuit.

[0077] It should be noted that the beneficial effects of the quantum circuit equivalence verification system 200 provided in the above embodiments are the same as those of the quantum circuit equivalence verification method described above, and will not be repeated here. Furthermore, the system provided in the above embodiments is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the system can be divided into different functional modules according to the actual situation to complete all or part of the functions described above. In addition, the system and method embodiments provided in the above embodiments belong to the same concept, and their specific implementation process is detailed in the method embodiments, and will not be repeated here.

[0078] The quantum circuit equivalence verification system of the present invention can be a computer program (including program code) running on a computer device. For example, the quantum circuit equivalence verification system of the present invention is an application software that can be used to execute the corresponding steps in the quantum circuit equivalence verification method of the present invention.

[0079] In some embodiments, the quantum circuit equivalence verification system of the present invention can be implemented in a combination of hardware and software. As an example, the quantum circuit equivalence verification system of the present invention can be a processor in the form of a hardware decoding processor, which is programmed to execute the quantum circuit equivalence verification method of the present invention. For example, the processor in the form of a hardware decoding processor can be one or more application-specific integrated circuits (ASICs), DSPs, programmable logic devices (PLDs), complex programmable logic devices (CPLDs), field-programmable gate arrays (FPGAs), or other electronic components.

[0080] The modules described in the embodiments of this invention can be implemented in software or hardware. The names of the modules are not, in some cases, limiting the scope of the module itself.

[0081] An electronic device according to an embodiment of the present invention includes a memory, a processor, and a computer program stored in the memory and executable on the processor. When the processor executes the computer program, it implements any of the above-mentioned quantum circuit equivalence verification methods. That is, an electronic device according to an embodiment of the present invention may include, but is not limited to: a processor and a memory; the memory is used to store the computer program; the processor is used to execute the quantum circuit equivalence verification method shown in any embodiment of the present invention by calling the computer program.

[0082] In one alternative embodiment, an electronic device is provided, such as Figure 8 As shown, Figure 8 The illustrated electronic device 4000 includes a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, for example, via a bus 4002. Optionally, the electronic device 4000 may further include a transceiver 4004, which can be used for data interaction between the electronic device and other electronic devices, such as sending and / or receiving data. It should be noted that in practical applications, the transceiver 4004 is not limited to one type, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present invention.

[0083] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array), or other programmable logic devices, transistor logic devices, hardware components, or any combination thereof. It can implement or execute the various exemplary logic blocks, modules, and circuits described in conjunction with the disclosure of this invention. Processor 4001 may also be a combination that implements computational functions, such as including one or more microprocessor combinations, a combination of a DSP and a microprocessor, etc.

[0084] Bus 4002 may include a path for transmitting information between the aforementioned components. Bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus, etc. Bus 4002 can be divided into address bus, data bus, control bus, etc. For ease of representation, Figure 8The bus 4002 is represented by only one thick line, but this does not mean that there is only one bus or one type of bus.

[0085] The memory 4003 may be ROM (Read Only Memory) or other types of static storage devices capable of storing static information and instructions, RAM (Random Access Memory) or other types of dynamic storage devices capable of storing information and instructions, or EEPROM (Electrically Erasable Programmable Read Only Memory), CD-ROM (Compact Disc Read Only Memory) or other optical disc storage, optical disc storage (including compressed optical discs, laser discs, optical discs, digital universal optical discs, Blu-ray discs, etc.), magnetic disk storage media or other magnetic storage devices, or any other medium capable of carrying or storing desired program code in the form of instructions or data structures and accessible by a computer, but not limited thereto.

[0086] The memory 4003 stores application code (computer program) for executing the present invention, and its execution is controlled by the processor 4001. The processor 4001 executes the application code stored in the memory 4003 to implement the content shown in the foregoing method embodiments.

[0087] Among them, electronic devices can also be terminal devices, which can be any device that can install applications, including at least one of smartphones, tablets, laptops, desktop computers, smart speakers, smartwatches, smart TVs, and smart in-vehicle devices.

[0088] It should be noted that, Figure 8 The electronic device shown is merely an example and should not be construed as limiting the functionality and scope of the embodiments of the present invention.

[0089] An embodiment of the present invention provides a computer-readable storage medium storing a computer program, which, when executed by a processor, implements any of the above-mentioned quantum circuit equivalence verification methods.

[0090] Alternatively, the computer-readable storage medium may be a read-only memory (ROM), a random access memory (RAM), a compact disc read-only memory (CD-ROM), magnetic tape, a floppy disk, and an optical data storage device, etc.

[0091] In an exemplary embodiment, a computer program product or computer program is also provided, comprising computer instructions stored in a computer-readable storage medium. A processor of an electronic device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the electronic device to perform any of the aforementioned quantum circuit equivalence verification methods.

[0092] Computer program code for performing the operations of this invention can be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages ​​such as Java, Smalltalk, and C++, and conventional procedural programming languages ​​such as C or similar languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network—including a local area network (LAN) or a wide area network (WAN)—or can be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0093] It should be understood that the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present invention. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The computer-readable storage medium provided in this invention can be, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination thereof. More specific examples of a computer-readable storage medium may include, but are not limited to: an electrical connection having one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EEPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage device, magnetic storage device, or any suitable combination thereof. In this invention, a computer-readable storage medium can be any tangible medium containing or storing a program that can be used by or in conjunction with an instruction execution system, apparatus, or device.

[0095] The aforementioned computer-readable storage medium carries one or more programs, which, when executed by the electronic device, cause the electronic device to perform the method shown in the above embodiments.

[0096] The above description is merely a preferred embodiment of the present invention and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of disclosure in this invention is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-disclosed concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features with similar functions disclosed in this invention.

[0097] It should be noted that the terms "first," "second," etc., used in the specification and claims of this application are used to distinguish similar objects and represent a limitation on a specific order or sequence. Where appropriate, the order of use for similar objects can be interchanged so that the embodiments of this application described herein can be implemented in an order other than that shown or described.

[0098] Those skilled in the art will recognize that this invention can be implemented as a system, method, or computer program product. Therefore, this invention can be specifically implemented in the following forms: it can be entirely hardware, entirely software (including firmware, resident software, microcode, etc.), or a combination of hardware and software, generally referred to herein as a "circuit," "module," or "system." Furthermore, in some embodiments, this invention can also be implemented as a computer program product contained in one or more computer-readable media, which includes computer-readable program code.

[0099] Although embodiments of the present invention have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting the present invention. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of the present invention.

Claims

1. A method for verifying the equivalence of quantum circuits, characterized in that, include: Obtain a first quantum circuit and a second quantum circuit, both of which are quantum circuits operating on n qubits, and the first quantum circuit and the second quantum circuit are quantum gate sequences compiled by different compilers for the same quantum algorithm; Construct the inverse circuit of a preset quantum circuit, wherein the preset quantum circuit is either the first quantum circuit or the second quantum circuit, and the other quantum circuit is defined as a non-preset quantum circuit; Construct local random circuits and their inverses; The local random circuit, the non-preset quantum circuit, the inverse circuit of the preset quantum circuit, and the inverse circuit of the local random circuit are combined into a composite circuit according to the execution order. Using the all-zero state as the initial quantum state, the composite circuit is executed m times repeatedly. During each execution, the parameters of the local random circuit are randomly generated. The probability p is the percentage of times the quantum state is all zero in the measurement results after m executions. Compare the probability p with the decision threshold δ. If the probability p is greater than or equal to the decision threshold δ, then the first quantum circuit and the second quantum circuit are determined to be equivalent; otherwise, the first quantum circuit and the second quantum circuit are determined to be inequivalent. Where n and m are both positive integers; The local random circuit is composed of n single-qubit RY gates and n single-qubit RZ gates connected in sequence, and the inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected in sequence. The parameters for randomly generating the local random circuit include: the rotation angle of the single-qubit RY gate and the rotation angle of the single-qubit RZ gate of the local random circuit.

2. The method for verifying the equivalence of quantum circuits according to claim 1, characterized in that, Constructing the inverse circuit of the preset quantum circuit includes: The order in which all quantum gates in the preset quantum circuit are applied is reversed. If the preset quantum circuit contains parameter gates, the parameters in the parameter gates are negativeized.

3. The method for verifying the equivalence of a quantum circuit according to any one of claims 1 to 2, characterized in that, The execution order is as follows: first apply the local random circuit, then apply the non-preset quantum circuit, then apply the inverse circuit of the preset quantum circuit, and finally apply the inverse circuit of the local random circuit.

4. An equivalence verification system for quantum circuits, characterized in that, It includes a quantum circuit acquisition module, a first inverse circuit construction module, a second inverse circuit construction module, a circuit combination module, a parameter generation module, a probability determination module, and a verification and judgment module; The quantum circuit acquisition module is used to: acquire a first quantum circuit and a second quantum circuit, wherein the first quantum circuit and the second quantum circuit are both quantum circuits acting on n qubits, and the first quantum circuit and the second quantum circuit are quantum gate sequences compiled by different compilers for the same quantum algorithm; The first inverse circuit construction module is used to: construct the inverse circuit of a preset quantum circuit, wherein the preset quantum circuit is the first quantum circuit or the second quantum circuit, and the other quantum circuit is defined as a non-preset quantum circuit; The second inverse circuit construction module is used to: construct local random circuits and inverse circuits of local random circuits; The circuit combination module is used to: combine the local random circuit, the non-preset quantum circuit, the inverse circuit of the preset quantum circuit, and the inverse circuit of the local random circuit into a composite circuit according to the execution order; The parameter generation module is used to: repeatedly execute the composite circuit m times with the all-zero state as the initial quantum state, and randomly generate the parameters of the local random circuit each time it is executed; The probability determination module is used to: count the percentage of times the quantum state is all zero in the measurement results after m executions, and use this percentage as the probability p; The verification and judgment module is used to: compare the probability p with the judgment threshold δ; if the probability p is greater than or equal to the judgment threshold δ, then the first quantum circuit and the second quantum circuit are determined to be equivalent; otherwise, the first quantum circuit and the second quantum circuit are determined to be inequivalent. Where n and m are both positive integers; The local random circuit is composed of n single-qubit RY gates and n single-qubit RZ gates connected in sequence, and the inverse circuit of the local random circuit is composed of n single-qubit RZ gates and n single-qubit RY gates connected in sequence. The parameters for randomly generating the local random circuit include: the rotation angle of the single-qubit RY gate and the rotation angle of the single-qubit RZ gate of the local random circuit.

5. The equivalence verification system for quantum circuits according to claim 4, characterized in that, The first reverse circuit construction module is specifically used for: The order in which all quantum gates in the preset quantum circuit are applied is reversed. If the preset quantum circuit contains parameter gates, the parameters in the parameter gates are negativeized.

6. The equivalence verification system for quantum circuits according to any one of claims 4 to 5, characterized in that, The execution order is as follows: first apply the local random circuit, then apply the non-preset quantum circuit, then apply the inverse circuit of the preset quantum circuit, and finally apply the inverse circuit of the local random circuit.

7. An electronic device, characterized in that, It includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the equivalence verification method for a quantum circuit as described in any one of claims 1 to 3.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the equivalence verification method for a quantum circuit as described in any one of claims 1 to 3.

Images