A clock synchronization method for a chip computing network

Abstract

The application relates to the field of integrated circuits and distributed computing technology, in particular to a clock synchronization method for a chip computing network, which is characterized in that a customized simplified synchronization frame format is used to facilitate quick identification of a receiving end and reduce analysis overhead, a hardware synchronization module is arranged between a physical layer and a link layer to record high-precision time stamps and eliminate errors caused by protocol stack processing, a master-slave node interaction-based time stamp information is used to calculate clock deviation and realize real-time correction to achieve accurate synchronization, and each communication port is independently configured with a master-slave role and supports automatic topology discovery to adapt to complex network structures. The method reuses existing routing protocols and physical links of chips to reduce hardware overhead, has high synchronization precision and strong flexibility, can be widely applied to computing networks formed by artificial intelligence acceleration chips, graphic processors and data processors, and effectively improves multi-chip collaborative computing efficiency and data consistency.

Description

Technical Field

[0001] This invention relates to the field of integrated circuits and distributed computing technology, and in particular to a clock synchronization method for chip computing networks. Background Technology

[0002] With the rapid development of artificial intelligence, high-performance computing, and big data processing, the computing power of a single chip is gradually becoming a bottleneck. Interconnecting multiple computing chips (such as AI accelerator chips, GPUs, and DPUs) to form large-scale computing networks has become the mainstream solution. In such distributed computing systems, the collaborative execution of tasks and the consistency of data are highly dependent on the high-precision clock synchronization among all participating computing chips.

[0003] In existing technologies, the IEEE 1588 Precision Time Protocol (PTP) is a commonly used clock synchronization protocol for distributed systems. PTP achieves time synchronization by exchanging Sync, Follow_Up, Delay_Req, and Delay_Resp messages between master and slave nodes and recording the precise timestamps of the messages sent and received.

[0004] However, directly applying the traditional PTP protocol to chip computing networks faces many challenges: 1. Low synchronization accuracy: The PTP protocol usually runs on the network protocol stack of traditional operating systems. The jitter and latency uncertainty introduced by software processing are high, making it difficult to meet the nanosecond-level synchronization requirements between chips. 2. Decoupling from underlying chip interconnect protocols: Chips typically communicate using proprietary high-speed serial interconnects (such as SerDes) and simplified routing packet protocols. The general PTP message format cannot be effectively integrated with these underlying routing packet protocols, requiring additional encapsulation and decapsulation, increasing complexity and latency. 3. Insufficient clock adjustment granularity: The local clock source of the chip is usually generated by circuits such as phase-locked loop (PLL), and its frequency and phase adjustment is usually relatively coarse, or lacks a software-configurable real-time adjustment interface, making it difficult to achieve fine clock correction and drift compensation.

[0005] Therefore, there is an urgent need in this field for a clock synchronization solution that can be deeply integrated with the underlying communication architecture of the chip, with low hardware overhead and high synchronization accuracy. Summary of the Invention

[0006] The purpose of this invention is to overcome the problems of the prior art and provide a clock synchronization method for chip computing networks. This method addresses the technical issues of insufficient synchronization accuracy (failing to meet nanosecond-level requirements), disconnection from the underlying chip interconnection protocol requiring additional encapsulation and increased latency, coarse clock adjustment granularity hindering fine-grained correction, and fixed port roles resulting in weak adaptability to complex topologies when applied to chip computing networks. By designing a simplified frame format, a high-precision hardware synchronization module close to the physical layer, and flexibly configurable master-slave node roles, this invention achieves low-overhead, high-precision, and highly flexible chip-level clock synchronization.

[0007] The above objectives are achieved through the following technical solutions: A clock synchronization method for chip computing networks, applied to chip computing networks consisting of multiple computing chips interconnected by a high-speed interconnect network, includes the following steps: Step S1: Customization and transmission of synchronization frame format The synchronization frame adopts a simplified frame format. The Type field in the first frame is set to a specific reserved synchronization packet type value. The synchronization packet type value is different from the type of other data packets and control packets transmitted in the chip network and is used to indicate that the current frame is a high-priority clock synchronization frame. Step S2: Recording high-precision timestamps The hardware synchronization module records a precise transmission timestamp as the synchronization frame is about to leave the chip and enter the physical layer; the hardware synchronization module records a precise reception timestamp as the synchronization frame arrives at the physical layer entry point of the receiving chip. Step S3: Clock Deviation Calculation and Correction The slave node transmits the sending timestamp and the receiving timestamp to the local hardware synchronization module. The hardware synchronization module integrates a local clock correction unit. The local clock correction unit calculates the frequency deviation, phase deviation and drift of the clock based on the timestamp information of the master and slave nodes, and corrects the local clock based on the frequency deviation, the phase deviation and the drift. Step S4: Flexible Master-Slave Role Configuration Each communication link port in each direction of the chip can be independently configured as a master node or slave node through configuration registers to adapt to different chip network topologies.

[0008] As a further optimization step S1 of this method, the simplified frame format is a 64-bit short frame structure. The frame format includes an 8-bit Type field, a 56-bit routing information field, a 16-bit message ID field, a 48-bit nanosecond integer field, and a 16-bit nanosecond decimal field set sequentially. The message ID field is used to identify the type of synchronization frame. The types of synchronization frames include Sync frame, Follow_Up frame, Delay_Req frame, and Delay_Resp frame, with corresponding message ID values ​​of 0x00, 0x08, 0x02, and 0x03, respectively.

[0009] As a further optimization step S1 of this method, the specific reserved synchronization packet type value is 0x55; when the hardware parsing logic of the receiving chip recognizes that the Type field value is 0x55, it directly routes the synchronization frame to the hardware synchronization module for processing without the need for intervention from the upper layer protocol stack.

[0010] In step S2, a further optimization of this method, the hardware synchronization module is located between the physical layer (PHY) and the link layer (MAC) of the chip. The hardware synchronization module includes a timestamp generation unit (PTP_CLOCK), a timestamp recording unit (TSU), and a clock control unit. The timestamp generation unit is a counter based on local clock counting, controlled by the frequency, phase, and drift control words generated by the clock control unit. The timestamp recording unit includes a transmit timestamp recording subunit (TX_TSU) and a receive timestamp recording subunit (RX_TSU), which are used to record the transmit timestamp and receive timestamp of the synchronization frame, respectively.

[0011] In step S2, a further optimization of this method, both the sending timestamp and the receiving timestamp are 64-bit precision, and the time interval between the recording time of the timestamp and the synchronization frame entering and leaving the physical layer is less than 1 nanosecond, so as to avoid time errors caused by protocol stack processing and queue delay.

[0012] As a further optimization step S3 of this method, the specific formula for the local clock correction unit to calculate the clock deviation is as follows: offset=[(t2-t1)-(t4-t3)] / 2 Wherein, t1 is the timestamp of the master node sending the Sync frame, t2 is the timestamp of the slave node receiving the Sync frame, t3 is the timestamp of the slave node sending the Delay_Req frame, and t4 is the timestamp of the master node receiving the Delay_Req frame; the local clock correction unit adjusts the counting frequency and phase of the timestamp generation unit based on the offset to achieve clock synchronization.

[0013] As a further optimization of this method, the clock control unit is connected to the processor core through the chip's internal bus. The processor core can read the synchronization status information of the hardware synchronization module and participate in the configuration of clock synchronization parameters by writing control words. The synchronization status information includes the current master-slave role, timestamp deviation value, and clock correction count.

[0014] As a further optimization step S4 of this method, the communication link ports include ports in the four directions of east, south, west and north; the master-slave role configuration includes two modes: automatic configuration and external configuration: when the chip processor receives an external configuration request, it sets the port role according to the external configuration instruction; when there is no external configuration request, the western port is configured as the slave node and the eastern port is configured as the slave node by default.

[0015] As a further optimization step S4 of this method, the automatic configuration mode also includes a topology detection step: after the default configuration, it checks whether there is a connection on the western port; if there is a connection on the western port, the synchronization role of the north and south ports is not set; if there is no connection on the western port, the southern port is set as the master node and the northern port as the slave node.

[0016] As a further optimization of this method, during the execution of steps S1 to S4, the existing routing packet protocol and physical link of the chip are reused, and there is no need to set up a separate communication channel for the synchronization function; the physical link is a high-speed serial interconnection link between chips, including the SerDes link.

[0017] The clock synchronization method for chip computing networks provided by this invention reduces protocol parsing overhead and processing latency by customizing a simplified synchronization frame format, achieves nanosecond-level synchronization accuracy through a hardware synchronization module close to the physical layer, saves hardware resources and bandwidth by reusing existing chip routing protocols and physical links, and achieves efficient adaptation to complex chip network topologies through flexible configuration of master and slave port roles and automatic topology discovery. Compared with existing technologies, it has the following advantages: 1. High precision: By processing synchronization messages and adding timestamps through hardware instead of software, protocol stack latency and operating system jitter are greatly eliminated, achieving nanosecond-level synchronization precision; 2. Low overhead and high efficiency: Reuse the chip's existing routing packet protocol and physical link, eliminating the need to set up a separate communication channel for the synchronization function, thus saving hardware resources and bandwidth; 3. High flexibility: Each port role is configurable and supports automatic topology discovery, which can perfectly adapt to various complex chip network topologies (such as linear, mesh, array), enhancing the versatility and practicality of the solution; 4. High scalability: The clock control unit connects to the processor via an internal bus and supports dynamic software configuration of synchronization parameters (such as timestamp sampling frequency and deviation correction threshold), which can adapt to the performance requirements of different computing chips; 5. Good stability: By calculating frequency deviation and drift in real time, dynamic compensation of the clock is achieved, which effectively resists clock drift caused by temperature and voltage changes and improves long-term synchronization stability. Attached Figure Description

[0018] Figure 1 This is a schematic diagram showing the location of the chip hardware synchronization module in the chip in the clock synchronization method for chip computing networks described in this invention. Figure 2 This is a schematic diagram of the frame format of the clock synchronization frame in the clock synchronization method for chip computing networks described in this invention; Figure 3 This is a schematic diagram of the synchronization message interaction and timestamp recording between master and slave nodes in a clock synchronization method for chip computing networks according to the present invention. Figure 4 This is a flowchart illustrating the master-slave role configuration of chip ports in a clock synchronization method for chip computing networks as described in this invention. Figure 5 This is a schematic diagram of the default master-slave port of the chip array in the clock synchronization method for chip computing networks described in this invention. Detailed Implementation

[0019] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments. The described embodiments are merely some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0020] This solution provides a clock synchronization method for chip computing networks, applicable to chip computing networks consisting of multiple computing chips interconnected by a high-speed interconnect network. The method includes the following steps: S1: Customization and transmission of synchronization frame format The synchronization frame uses a simplified frame format, with the Type field in the first frame set to a specific, reserved synchronization packet type value (specifically 0x55). This value distinguishes it from other data packets and control packets transmitted within the chip network, indicating that the current frame is a high-priority clock synchronization frame. This facilitates rapid identification and capture by the synchronization module of the receiving chip, thereby reducing protocol parsing overhead and processing latency.

[0021] like Figure 2 As shown, the simplified frame format is a 64-bit short frame structure, with the specific field divisions as follows: Byte 1 (8 bits): Type field, a value of 0x55 indicates a synchronization frame; Bytes 2-8 (56 bits): Routing Information field, used to indicate the transmission path of the synchronization frame in the chip network; Bytes 9-10 (16 bits): Message ID field, used to identify the specific type of synchronization frame, where Sync frame corresponds to 0x00, Follow_Up frame corresponds to 0x08, Delay_Req frame corresponds to 0x02, and Delay_Resp frame corresponds to 0x03; Bytes 11-16 (48 bits): Nanoseconds field, recording the integer part of the timestamp; Bytes 17-18 (16 bits): Fractionns field, which records the fractional part of the timestamp, achieving sub-nanosecond precision.

[0022] Once the hardware parsing logic of the receiving chip recognizes that the Type field is 0x55, it can directly route the frame to the hardware synchronization module for efficient processing without the need for intervention from the upper-layer protocol stack, thus further reducing processing latency.

[0023] S2: Record of high-precision timestamps Just as the synchronization frame is about to leave the chip and enter the physical layer (PHY), the transmission timestamp recording subunit (TX_TSU) in the hardware synchronization module records the precise transmission timestamp; similarly, when the synchronization frame arrives at the physical layer entry point of the receiver chip, the reception timestamp recording subunit (RX_TSU) in the hardware synchronization module enters the precise reception timestamp.

[0024] like Figure 1 As shown, the hardware synchronization module is located between the physical layer (PHY) and the data link layer (MAC) of the chip, closely adjacent to the physical layer, and specifically includes three core sub-units: Timestamp generation unit (PTP_CLOCK): A counter that continuously counts based on the local clock, controlled by the frequency, phase and drift control words generated by the clock control unit, providing 64-bit precision timestamps for the entire clock synchronization module; Timestamp Recording Unit (TSU): Divided into TX_TSU and RX_TSU, which generate record information containing a 64-bit timestamp and message type (i.e., MessageID) at the moment when the synchronization frame enters or leaves the PHY; Clock control unit: It is connected to the processor core through the chip's internal bus (such as the APB bus). The processor can read synchronization status information (such as the current master / slave role and timestamp deviation value) and write control words to participate in clock synchronization parameter configuration.

[0025] By placing the timestamp recording point as close as possible to the physical layer, time errors caused by protocol stack processing and queue delays are effectively avoided. The time interval between the recording time of the sending timestamp and receiving timestamp and the entry and exit time of the synchronization frame into and out of the physical layer is less than 1 nanosecond, thereby obtaining a highly accurate timestamp.

[0026] S3: Clock Deviation Calculation and Correction The slave node transmits the received timestamp (t1) from the master node, its own received timestamp (t2), the timestamp of its own Delay_Req frame transmission (t3), and the timestamp of the received Delay_Req frame returned by the master node (t4) to its local hardware synchronization module. The local clock correction unit within this module calculates the clock frequency deviation, phase deviation, and drift based on these four timestamps.

[0027] The specific calculation process is as follows: First, such as Figure 3 As shown, according to the message interaction sequence between the master and slave nodes, the master node first sends a Sync packet. After capturing the sending time t1 of the Sync packet in TX_TSU, it loads the t1 value into a Follow_Up packet and sends it to the slave node. The slave node captures the receiving time t2 of the Sync packet in RX_TSU and parses the Follow_Up packet to obtain t1. Subsequently, the slave node sends a Delay_Req packet, and TX_TSU captures its sending time t3. The master node captures the receiving time t4 of the Delay_Req packet in RX_TSU and loads the t4 value into a Delay_Resp packet and returns it to the slave node. The slave node parses the Delay_Resp packet to obtain t4.

[0028] Based on t1-t4 above, the local clock correction unit calculates the clock offset using the following formula: offset=[(t2-t1)-(t4-t3)] / 2 The frequency deviation and drift are fitted by combining the offset values ​​from multiple samplings; then the corresponding frequency control word, phase control word and drift compensation word are generated and sent to the timestamp generation unit (PTP_CLOCK) to adjust its counting frequency and phase, so as to realize real-time clock correction and drift compensation.

[0029] S4: Flexible Master-Slave Role Configuration Each communication link port of the chip in each direction (such as the four directions of east, south, west and north) can be independently configured as a master node or a slave node through the configuration register to adapt to different network topologies (such as linear arrays and mesh structures).

[0030] like Figure 4 As shown, the specific configuration process is as follows: After the system starts up, the chip processor first checks for external configuration requests (i.e., configuration instructions written by the upper-layer software). If there is an external configuration request, the master / slave roles of each port will be set according to the external configuration instructions; If there is no external configuration request, the west port is configured as the slave node (S) and the east port as the master node (M) by default. After completing the default configuration, check if there is a physical connection on the west port (by checking the link status signal). If there is a connection on the west port, the synchronization role of the north-south port is not set (i.e., the north-south port does not participate in clock synchronization). If there is no connection on the west port, then set the south port as the master node (M) and the north port as the slave node (S). The role status of all ports can be overridden by the software at any time through the configuration register. The value of the configuration register determines the final working mode of the port.

[0031] like Figure 5 As shown, in the chip array, the actual effect of the default master-slave port configuration is as follows: the system clock is synchronized step by step by the chip in the upper left corner. The east port (M) of the chip in the upper left corner is connected to the west port (S) of the adjacent chip on the right, and the south port (M) is connected to the north port (S) of the adjacent chip below, forming a tree-like synchronization topology to ensure the clock consistency of the entire array.

[0032] Furthermore, during the execution of steps S1 to S4, this method reuses the chip's existing routing packet protocol (such as the chip-to-chip simplified routing protocol) and physical link (such as the SerDes high-speed serial link), eliminating the need to establish a separate communication channel for the synchronization function, thus saving hardware resources and bandwidth.

[0033] The above description is merely illustrative of the embodiments of the present invention and is not intended to limit the present invention. For those skilled in the art, any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A clock synchronization method for chip computing networks, characterized in that, Applied to chip computing networks consisting of multiple computing chips interconnected by a high-speed interconnect network, the method includes the following steps: Step S1: Customization and transmission of synchronization frame format The synchronization frame adopts a simplified frame format. The Type field in the first frame is set to a specific reserved synchronization packet type value. The synchronization packet type value is different from the type of other data packets and control packets transmitted in the chip network and is used to indicate that the current frame is a high-priority clock synchronization frame. Step S2: Recording high-precision timestamps The hardware synchronization module records a precise transmission timestamp as the synchronization frame is about to leave the chip and enter the physical layer; the hardware synchronization module records a precise reception timestamp as the synchronization frame arrives at the physical layer entry point of the receiving chip. Step S3: Clock Deviation Calculation and Correction The slave node transmits the sending timestamp and the receiving timestamp to the local hardware synchronization module. The hardware synchronization module integrates a local clock correction unit. The local clock correction unit calculates the frequency deviation, phase deviation and drift of the clock based on the timestamp information of the master and slave nodes, and corrects the local clock based on the frequency deviation, the phase deviation and the drift. Step S4: Flexible Master-Slave Role Configuration Each communication link port in each direction of the chip can be independently configured as a master node or slave node through configuration registers to adapt to different chip network topologies.

2. The clock synchronization method for chip computing networks according to claim 1, characterized in that, In step S1, the simplified frame format is a 64-bit short frame structure. The frame format includes an 8-bit Type field, a 56-bit routing information field, a 16-bit message ID field, a 48-bit nanosecond integer field, and a 16-bit nanosecond decimal field, set sequentially. The message ID field is used to identify the type of synchronization frame. The types of synchronization frames include Sync frames, Follow_Up frames, Delay_Req frames, and Delay_Resp frames, with corresponding message ID values ​​of 0x00, 0x08, 0x02, and 0x03, respectively.

3. The clock synchronization method for chip computing networks according to claim 2, characterized in that, In step S1, the specific reserved synchronization packet type value is 0x55; when the hardware parsing logic of the receiving chip recognizes that the Type field value is 0x55, it directly routes the synchronization frame to the hardware synchronization module for processing without the need for intervention from the upper-layer protocol stack.

4. The clock synchronization method for chip computing networks according to claim 1, characterized in that, In step S2, the hardware synchronization module is located between the physical layer and the link layer of the chip; the hardware synchronization module includes a timestamp generation unit, a timestamp recording unit, and a clock control unit; the timestamp generation unit is a counter based on local clock counting, controlled by the frequency, phase, and drift control words generated by the clock control unit; the timestamp recording unit includes a transmit timestamp recording subunit and a receive timestamp recording subunit, which are used to record the transmit timestamp and receive timestamp of the synchronization frame, respectively.

5. A clock synchronization method for chip computing networks according to claim 4, characterized in that, In step S2, both the sending timestamp and the receiving timestamp are 64-bit precision.

6. A clock synchronization method for chip computing networks according to claim 4, characterized in that, In step S3, the specific formula for the local clock correction unit to calculate the clock deviation is as follows: offset=[(t2-t1)-(t4-t3)] / 2 Wherein, t1 is the timestamp of the master node sending the Sync frame, t2 is the timestamp of the slave node receiving the Sync frame, t3 is the timestamp of the slave node sending the Delay_Req frame, and t4 is the timestamp of the master node receiving the Delay_Req frame; the local clock correction unit adjusts the counting frequency and phase of the timestamp generation unit based on the offset to achieve clock synchronization.

7. A clock synchronization method for chip computing networks according to claim 4, characterized in that, The clock control unit is connected to the processor core via the chip's internal bus. The processor core can read the synchronization status information of the hardware synchronization module and participate in the configuration of clock synchronization parameters by writing control words.

8. A clock synchronization method for chip computing networks according to claim 1, characterized in that, In step S4, the communication link ports include ports in the four directions of east, south, west, and north; The master-slave role configuration includes two modes: automatic configuration and external configuration. When the chip processor receives an external configuration request, it sets the port role according to the external configuration instructions. When there is no external configuration request, the western port is configured as a slave node and the eastern port is configured as a slave node by default.

9. A clock synchronization method for chip computing networks according to claim 8, characterized in that, In step S4, the automatic configuration mode also includes a topology detection step: after the default configuration, it checks whether there is a connection on the western port; if there is a connection on the western port, the synchronization role of the north and south ports is not set; if there is no connection on the western port, the southern port is set as the master node and the northern port as the slave node.

10. A clock synchronization method for chip computing networks according to claim 1, characterized in that, During the execution of steps S1 to S4, the existing routing packet protocol and physical link of the chip are reused, and there is no need to set up a separate communication channel for the synchronization function; the physical link is a high-speed serial interconnection link between chips.

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