A high-speed hardware acceleration system and implementation method for kyber quantum-resistant cryptographic algorithm

Abstract

This invention discloses a high-speed hardware acceleration system and implementation method for the Kyber quantum-resistant cryptographic algorithm. The invention relates to the field of hardware acceleration technology for quantum-resistant cryptographic algorithms, and includes: a dynamic resource management and scheduling center, reconfigurable NTT computing cluster units, a streaming polynomial coefficient cache network, and a runtime secure scheduler. The dynamic resource management and scheduling center is connected to the reconfigurable NTT computing cluster units, the streaming polynomial coefficient cache network, and the runtime secure scheduler. This high-speed hardware acceleration system and implementation method for the Kyber quantum-resistant cryptographic algorithm effectively improves the overall system throughput and response speed, and reduces idle losses caused by fixed resource allocation or data waiting. The flexible reconfiguration and reuse capabilities of hardware resources enable the same set of physical units to efficiently adapt to different core operation modes in the Kyber algorithm, improving hardware utilization efficiency.

Description

Technical Field

[0001] This invention relates to the field of hardware acceleration technology for quantum-resistant cryptographic algorithms, specifically to a high-speed hardware acceleration system and implementation method for the Kyber quantum-resistant cryptographic algorithm. Background Technology

[0002] With the rapid development of quantum computing technology, traditional public-key cryptography systems face severe challenges. The Kyber algorithm, a key encapsulation mechanism based on the modular learning problem (MLWE), has been selected as one of the main algorithms in the quantum-resistant cryptography standardization project. Its efficient implementation in practical systems is noteworthy; however, the core operations of the Kyber algorithm involve a large number of polynomial multiplications and number-theoretic transformations (NTTs), leading to challenges such as high computational latency, high resource consumption, and limited throughput in hardware implementation. To improve the execution efficiency of cryptographic algorithms on hardware, existing technologies have proposed some general optimization schemes. For example, patent document CN119728106B describes a "method and apparatus for high-speed algorithm operation based on multi-level field caching." This solution utilizes the collaboration between the configuration management CPU and the business processing CPU, employing a two-level cache structure comprised of on-chip BRAM and external DDR on the FPGA to efficiently manage and cache algorithm parameters, keys, and intermediate computation states. However, this solution primarily focuses on optimizing general cryptographic task scheduling and cache management, without in-depth hardware architecture optimization for the core computational characteristics of the Kyber quantum-resistant algorithm. Furthermore, in the implementation of quantum-resistant cryptography hardware, in addition to performance, security, such as resistance to side-channel attacks, is also a crucial indicator, and general cache optimization solutions typically do not integrate targeted physical security protection mechanisms.

[0003] Therefore, how to design a high-speed hardware acceleration system and implementation method specifically for Kyber's quantum-resistant cryptographic algorithm, and achieve a comprehensive performance breakthrough in throughput, latency and resource utilization through deep hardware optimization of the algorithm's core computing unit, efficient parallel computing architecture design and integrated side-channel protection mechanism, while ensuring the correctness and security of the algorithm, and taking into account stable and efficient operation in high-concurrency scenarios, has become an urgent technical problem to be solved in this field. Summary of the Invention

[0004] The purpose of this invention is to provide a high-speed hardware acceleration system and implementation method for Kyber quantum-resistant cryptography algorithms, so as to solve the problems mentioned in the background art.

[0005] To solve the above-mentioned technical problems, the present invention provides the following technical solution: a high-speed hardware acceleration system for Kyber quantum-resistant cryptography algorithm, integrated in a programmable logic device or application-specific integrated circuit, including: a dynamic resource management and scheduling hub, a reconfigurable NTT computing cluster unit, a streaming polynomial coefficient cache network, and a runtime security scheduler;

[0006] The dynamic resource management and scheduling hub is connected to the reconfigurable NTT computing cluster unit, the streaming multinomial coefficient cache network, and the runtime security scheduler, respectively. It is used to receive cryptographic operation instructions, parse the operation tasks into computing kernels, dynamically allocate and configure computing and storage resources for each computing kernel, generate a unified scheduling flow containing computing control microcode and data transfer instructions, and monitor the system status to trigger dynamic optimization.

[0007] The reconfigurable NTT computing cluster unit is connected to the dynamic resource management and scheduling center. It is used to dynamically combine multiple basic computing units into a computing cluster that executes the topology required by a specific computing kernel according to the configuration instructions of the dynamic resource management and scheduling center, and to perform number theory transformation, inverse number theory transformation and modular operation under the control of the scheduling flow.

[0008] The streaming polynomial coefficient caching network is connected to the dynamic resource management and scheduling center and the reconfigurable NTT computing cluster unit. It is used to hierarchically store polynomial coefficients and intermediate data, and according to the data transfer instructions issued by the dynamic resource management and scheduling center, it streams the computation data and writes back the results in a manner that overlaps with the computation process of the reconfigurable NTT computing cluster unit.

[0009] The runtime security scheduler is connected to the dynamic resource management and scheduling center. During algorithm execution, it dynamically generates hardware-level protection operation microcode based on preset security policies and random signals, and then encodes the protection operation microcode into the unified scheduling flow through the dynamic resource management and scheduling center.

[0010] Furthermore, the reconfigurable NTT computing cluster unit includes multiple basic computing units and an on-chip interconnect network;

[0011] The basic computing unit includes: a Montgomery modular multiplier core, an arithmetic logic array configurable to perform modular addition or modular subtraction operations, and a local coefficient register file;

[0012] The on-chip interconnect network connects multiple basic computing units, and its connection path can be changed by the configuration of the dynamic resource management and scheduling center;

[0013] The dynamic resource management and scheduling hub dynamically combines a group of basic computing units into an operational cluster that executes the current computing kernel by configuring the working modes of the on-chip interconnect network and the arithmetic logic array within the basic computing unit.

[0014] Furthermore, the streaming polynomial coefficient cache network includes: a coefficient register window, a dedicated cache for butterfly operations, an on-chip block RAM pool, and a data transfer engine;

[0015] The coefficient register window is set within each of the basic computing units and is used to temporarily store the individual coefficients currently participating in the calculation;

[0016] The dedicated cache for butterfly operations has a storage structure that matches the access mode of butterfly operations in number theory transformations. It adopts a multi-volume parallel and interleaved storage method to provide all the coefficient pairs required for a single round of butterfly operations for one of the operation clusters.

[0017] The on-chip block RAM pool is used to store complete polynomial or matrix data blocks;

[0018] The data transfer engine is connected to the butterfly operation dedicated cache and the on-chip block RAM pool, and is also connected to the dynamic resource management and scheduling center. It is used to perform prefetch and write-back operations of coefficient data between the on-chip block RAM pool and the butterfly operation dedicated cache according to the prediction of the dynamic resource management and scheduling center.

[0019] Furthermore, the runtime security scheduler includes: a true random number generator, a protection operation microcode library, and a scheduling state machine;

[0020] The protection operation microcode library stores a variety of hardware operation sequences that have no actual computational meaning and are used to change the power consumption characteristics or state of the circuit.

[0021] The scheduling state machine is connected to the true random number generator, the protection operation microcode library, and the dynamic resource management and scheduling center, respectively. It is used to select the corresponding protection operation microcode from the protection operation microcode library based on the random number output by the true random number generator, the current computing pipeline status fed back by the dynamic resource management and scheduling center, and the pre-loaded security level configuration, and to determine the timing of its insertion into the unified scheduling flow.

[0022] Furthermore, when orchestrating the unified scheduling flow, the dynamic resource management and scheduling center mixes the protective operation microcode from the runtime security scheduler with the normal computation microcode from the computation task parsing, so that the protective operation microcode is inserted into the execution gaps of the normal computation instruction flow without introducing independent, predictable idle clock cycles.

[0023] Furthermore, the dynamic resource management and scheduling center performs the following steps to achieve system control:

[0024] S1: Receives and parses cryptographic tasks, decomposing the tasks into multiple computational kernels with dependencies;

[0025] S2: For the computing kernel to be executed, dynamically configure the reconfigurable NTT computing cluster unit to form a matching operation cluster, and allocate a data storage area for the computing kernel in the streaming polynomial coefficient cache network;

[0026] S3: Generate the unified scheduling flow, wherein synchronization includes: computation control microcode that controls the computation cluster to perform computation, data transfer instructions that control the data transfer engine to perform data prefetching and write-back, and protection operation microcode provided by the runtime security scheduler;

[0027] S4: Issue and execute the unified scheduling flow to enable computation, data transfer and security protection operations to be performed in a coordinated manner;

[0028] S5: During task execution, monitor the utilization rate of the computing cluster and the access status of the streaming polynomial coefficient cache network. If the performance index is lower than the preset threshold, trigger dynamic reconfiguration of the internal connection or data prefetching strategy of the computing cluster.

[0029] Furthermore, in step S3, generating the unified scheduling flow specifically includes:

[0030] S31: Based on the data access mode of the computing kernel, generate a data prefetch instruction sequence from the on-chip block RAM pool to the butterfly operation dedicated cache;

[0031] S32: Based on the configuration of the computing cluster and the algorithm steps of the computing kernel, generate the computing control microcode sequence;

[0032] S33: While generating the computation control microcode sequence, the protective operation microcode is inserted into the instruction gaps of the computation control microcode sequence according to the output of the runtime security scheduler, forming a hybrid microcode sequence;

[0033] S34: The data prefetch instruction sequence, the hybrid microcode sequence, and the corresponding data write-back instruction sequence are combined into the unified scheduling flow according to the time-series dependency relationship.

[0034] Furthermore, the butterfly operation-specific cache of the streaming polynomial coefficient cache network is organized in a multi-bank parallel and interleaved manner as follows: coefficient pairs required for different butterfly operations belonging to the same round are stored in different storage banks; when the operation cluster performs a round of butterfly operation, all coefficient pairs required for that round of operation can be read simultaneously from multiple storage banks through a single parallel access operation.

[0035] A high-speed hardware acceleration method for the Kyber quantum-resistant cryptographic algorithm, executed by the dynamic resource management and scheduling center in the high-speed hardware acceleration system, the method comprising:

[0036] a: Receive cryptographic operation task instructions and security level configuration;

[0037] b: Parse the cryptographic operation task and decompose it into multiple ordered computational kernels;

[0038] c: Dynamically configure reconfigurable NTT computing cluster units for the current computing kernel to form an adapted computing cluster topology;

[0039] d: Based on the data access characteristics of the current computing kernel, plan the data storage path in the streaming multinomial coefficient cache network and start data prefetching;

[0040] e: Obtain the protection operation microcode generated by the runtime security scheduler based on the security level configuration and random signals;

[0041] f: Generate a unified scheduling flow, in which computation control microcode, data transfer instructions and the protection operation microcode are mixed and arranged, so that the protection operation is completed in the execution gap of the computation instruction flow;

[0042] g: Execute the unified scheduling flow, control the operation cluster and the streaming polynomial coefficient cache network to work together, complete the cryptographic operation and output the result.

[0043] Furthermore, after generating the unified scheduling flow but before execution, an optimization step is also included:

[0044] Analyze the timing relationship between computation microcode and data transfer instructions in the unified scheduling flow to identify idle periods of computing units that may occur due to data dependencies;

[0045] Adjust the insertion position of the protection operation microcode in the unified scheduling flow, and prioritize filling the identified idle time periods with the protection operation microcode.

[0046] This invention provides a high-speed hardware acceleration system and implementation method for Kyber quantum-resistant cryptography algorithms. It offers the following advantages:

[0047] This high-speed hardware acceleration system and implementation method for the Kyber quantum-resistant cryptographic algorithm achieves dynamic optimization and combination of computing resources according to the algorithm stage through a unified coordination of reconfigurable computing clusters, streaming cache networks, and a secure scheduler via a dynamic resource management and scheduling center. This results in deep overlap between data supply and the computing pipeline, effectively improving the overall system throughput and response speed while reducing idle losses caused by fixed resource allocation or data waiting. The flexible reconfiguration and reuse capabilities of hardware resources enable the same set of physical units to efficiently adapt to different core computational modes in the Kyber algorithm, improving hardware utilization efficiency.

[0048] This high-speed hardware acceleration system and implementation method for the Kyber quantum-resistant cryptographic algorithm achieves synchronous integration of security protection and normal computation at the hardware level by seamlessly inserting and filling runtime-generated protective operation microcode into the inherent gaps in the computation instruction stream. This approach increases the difficulty of side-channel analysis and enhances the system's physical security without occupying an additional full clock cycle or interfering with the normal data flow. The collaborative architecture of these three components enables the system to exhibit excellent adaptability and overall performance when dealing with diverse cryptographic tasks and security threats. Attached Figure Description

[0049] Figure 1 This is a flowchart illustrating the unified scheduling flow generation process of a high-speed hardware acceleration system and implementation method for Kyber quantum-resistant cryptography algorithm according to the present invention.

[0050] Figure 2 This is a diagram showing the internal structure of the runtime security scheduler of a high-speed hardware acceleration system and implementation method for the Kyber quantum-resistant cryptographic algorithm according to the present invention. Detailed Implementation

[0051] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0052] Please see Figure 1 and Figure 2 The present invention provides a technical solution: a high-speed hardware acceleration system for Kyber quantum-resistant cryptography algorithm, integrated in a programmable logic device or application-specific integrated circuit, including: a dynamic resource management and scheduling center, a reconfigurable NTT computing cluster unit, a streaming polynomial coefficient cache network, and a runtime security scheduler;

[0053] The dynamic resource management and scheduling hub is connected to the reconfigurable NTT computing cluster unit, the streaming multinomial coefficient cache network, and the runtime security scheduler, respectively. It is used to receive cryptographic operation instructions, parse the operation tasks into computing kernels, dynamically allocate and configure computing and storage resources for each computing kernel, generate a unified scheduling flow containing computing control microcode and data transfer instructions, and monitor the system status to trigger dynamic optimization.

[0054] The reconfigurable NTT computing cluster unit is connected to the dynamic resource management and scheduling center. It is used to dynamically combine multiple basic computing units into computing clusters that execute the topology required by a specific computing kernel according to the configuration instructions of the dynamic resource management and scheduling center, and to perform number theory transformations, inverse number theory transformations and modular operations under the control of the scheduling flow.

[0055] The streaming polynomial coefficient caching network is connected to the dynamic resource management and scheduling center and the reconfigurable NTT computing cluster unit. It is used to hierarchically store polynomial coefficients and intermediate data, and according to the data transfer instructions issued by the dynamic resource management and scheduling center, it streams the computation data and writes back the results in a way that overlaps with the computation process of the reconfigurable NTT computing cluster unit.

[0056] The runtime security scheduler, connected to the dynamic resource management and scheduling center, is used to dynamically generate hardware-level protection operation microcode based on preset security policies and random signals during algorithm execution, and then hand over the protection operation microcode to the dynamic resource management and scheduling center for orchestration into a unified scheduling flow.

[0057] It should be further explained that this system is integrated into a programmable logic device or application-specific integrated circuit, and its hardware architecture comprises four deeply collaborative components. The dynamic resource management and scheduling hub serves as the control core, internally containing a task parser, a resource status table, and a microcode sequence generator. This hub receives cryptographic operation instructions from the host processor via an internal bus. The task parser, based on the Kyber algorithm's operation sequence, decomposes the instructions into a sequence of computational kernels with explicit data dependencies, such as a polynomial number theory transformation kernel and a coefficient multiplication-addition kernel.

[0058] The resource status table records and updates in real time the idle and busy status of each basic computing unit in the reconfigurable NTT computing cluster unit, as well as the storage occupancy status at each level in the streaming polynomial coefficient cache network. For each computing kernel about to be executed, the microcode sequence generator performs the following operations based on its computing characteristics and resource status: sends configuration words to the reconfigurable NTT computing cluster unit to dynamically combine computing clusters; sends prefetch commands to the data transport engine of the streaming polynomial coefficient cache network; and simultaneously receives protection microcode fragments from the runtime security scheduler, and mixes and arranges these fragments with the generated computing microcode and data transport commands according to time-series logic to form a continuous unified scheduling flow instruction sequence, which is then distributed to each execution unit through a dedicated control interface.

[0059] The reconfigurable NTT computing cluster unit consists of multiple identical basic computing units connected by a configurable on-chip interconnect network. Each basic computing unit integrates a Montgomery modular multiplier core implemented using a carry-preserving adder chain and a partial product compression tree, an arithmetic logic array that can be switched between modular addition and modular subtraction via control signals, and a local coefficient register file with limited capacity. The on-chip interconnect network contains multiple configurable data paths and cross switches.

[0060] When the dynamic resource management and scheduling center issues configuration commands, specific paths in the interconnected network are connected, linking a selected number of basic computing units into a topology adapted to the target computing kernel. For example, for radix-2 butterfly operations, two basic computing units are paired and connected; for operations with higher parallelism, a small mesh structure can be formed. After configuration, the computing cluster obtains operands from the streaming polynomial coefficient cache network based on the computational microcode in the delivered unified scheduling stream, and performs the specified modular multiplication, modular addition, or modular subtraction operations.

[0061] The streaming multinomial coefficient cache network employs a hierarchical structure, including coefficient register windows embedded in each basic computational unit, a centrally located dedicated butterfly operation cache, a large-capacity on-chip block RAM pool, and a dedicated data transfer engine for data migration. The dedicated butterfly operation cache physically consists of multiple parallel memory banks. Its logical address-to-physical memory bank mapping is specially designed to follow the access pattern of number theory transformation butterfly operations, ensuring that coefficient pairs required for different butterfly operations within the same round of computation are stored in different memory banks.

[0062] The data transport engine has pre-defined data flow modes for different computing kernels. When it receives a prefetch instruction from the dynamic resource management and scheduling center, it can autonomously read the coefficient data blocks required for subsequent calculations from the on-chip block RAM pool according to the current calculation progress and prefetch rules, and write them into the corresponding storage of the butterfly operation dedicated cache. At the same time, it writes the calculated data blocks back from the dedicated cache to the block RAM pool. This data transport process overlaps with the operation of the computing cluster in time.

[0063] The runtime safety scheduler internally includes a true random number generator based on a physical entropy source, a read-only memory storing various protective operation microcodes, and a scheduling state machine. Protective operation microcodes are designed short instruction sequences that can generate specific power consumption or electromagnetic characteristics in the hardware circuitry without affecting the actual computational data. Examples include toggling redundant registers and performing modular multiplication addressing with no operation.

[0064] During system operation, the scheduling state machine continuously monitors the computing pipeline status signals provided by the dynamic resource management and scheduling center. Combined with the real-time output of the true random number generator, and based on the pre-loaded security policy configuration, it dynamically selects a segment of protective operation microcode from read-only memory and determines when to submit it to the dynamic resource management and scheduling center for instruction stream hybrid orchestration. Through the collaborative work of these four components, the system achieves on-demand dynamic reconfiguration of computing resources, tight coupling between data provisioning and the computing pipeline, and seamless timing integration of security protection operations and normal computing instructions at the hardware level.

[0065] The reconfigurable NTT computing cluster unit includes multiple basic computing units and an on-chip interconnect network;

[0066] The basic computing unit includes: a Montgomery modular multiplier core, an arithmetic logic array configurable to perform modular addition or modular subtraction operations, and a local coefficient register file;

[0067] The on-chip interconnect network connects multiple basic computing units, and its connection path can be changed by the configuration of the dynamic resource management and scheduling center;

[0068] The dynamic resource management and scheduling hub dynamically combines a group of basic computing units into an operational cluster that executes the current computing kernel by configuring the on-chip interconnect network and the working mode of the arithmetic logic array within the basic computing unit.

[0069] It should be further explained that the reconfigurable NTT computing cluster unit contains multiple structurally identical basic computing units, which are interconnected through an on-chip interconnect network. The hardware configuration of each basic computing unit includes a Montgomery modular multiplier core for performing modular multiplication operations, which is implemented using a specific algorithm to avoid the use of traditional divider units during the operation; an arithmetic logic array that can be configured to perform modular addition or modular subtraction operations based on received control signals; and a local coefficient register file with limited capacity for temporarily storing a few operands or intermediate results directly involved in the current operation.

[0070] The on-chip interconnect network consists of multiple data paths and a configurable crossbar switch matrix, allowing flexible data transmission paths to be established between different basic computing units. The dynamic resource management and scheduling hub can dynamically change the connection status of these data paths by sending specific configuration command words to the on-chip interconnect network, thereby logically combining a set of selected basic computing units into a computational cluster with a specific topology. For example, for performing standard butterfly operations, the hub can configure the interconnect network to pair two basic computing units, enabling data exchange and merging computations; for operations requiring higher data throughput, the hub can configure a small mesh connection structure, allowing multiple basic computing units to perform parallel computations simultaneously. While configuring the computational cluster topology, the hub also sends control signals to the relevant basic computing units, setting their internal arithmetic logic arrays to be in modular addition or modular subtraction mode. Through this mechanism, a set of general-purpose basic computing unit hardware resources can be dynamically reconfigured into the most suitable dedicated computing hardware structure according to the needs of different algorithm stages.

[0071] The streaming polynomial coefficient cache network includes: a coefficient register window, a dedicated cache for butterfly operations, an on-chip block RAM pool, and a data transfer engine;

[0072] The coefficient register window is set within each basic calculation unit to temporarily store the individual coefficients currently involved in the calculation;

[0073] A dedicated cache for butterfly operations, whose storage structure is organized to match the access mode of butterfly operations in number theory transformations, uses a multi-volume parallel and interleaved storage method to provide all the coefficient pairs required for a single round of butterfly operations for an operation cluster;

[0074] On-chip block RAM pool is used to store complete polynomial or matrix data blocks;

[0075] The data transfer engine connects to the butterfly operation dedicated cache and the on-chip block RAM pool, and is also connected to the dynamic resource management and scheduling center. It is used to perform prefetch and write-back operations of coefficient data between the on-chip block RAM pool and the butterfly operation dedicated cache according to the prediction of the dynamic resource management and scheduling center.

[0076] It should be further explained that the streaming polynomial coefficient cache network consists of a tightly coupled four-level structure. Closest to the computation unit is the coefficient register window, directly integrated within each basic computation unit as a dedicated register group. This temporarily stores the few coefficient operands being processed by the unit in the current computation cycle, achieving zero-latency access. The core component is the butterfly operation dedicated cache, which is composed of multiple independent static random access memory banks in parallel. Its address mapping logic is specially designed so that when performing a specific round of quantum theoretical transformations, each pair of coefficients required for all butterfly operations in that round is automatically allocated and stored in different physical memory banks. This multi-bank parallel and interleaved storage organization ensures that when one computation cluster in the reconfigurable NTT computation cluster needs to perform a complete round of butterfly operations, all coefficient pairs required for that round of operations can be read simultaneously from all relevant memory banks through a single parallel multi-port access operation, thus eliminating the waiting caused by sequential access or memory bank conflicts in traditional storage structures. The on-chip block RAM pool consists of multiple large-capacity block RAM modules used to store complete polynomial coefficient vectors or matrix data blocks. The dedicated data transport engine incorporates an address generation state machine and a direct memory access controller. It receives prefetch and write-back instructions from the dynamic resource management and scheduling center. These instructions contain the source address of the data block in the on-chip block RAM pool, the target address in the butterfly operation dedicated cache, and the length information of the data block. Based on these instructions, while the computing cluster is performing the operation on the current data block, the data transport engine independently and asynchronously reads the next block of data to be processed from the on-chip block RAM pool and fills it into the freed memory in the butterfly operation dedicated cache. At the same time, it writes the result data of the current operation from the dedicated cache back to the designated location in the on-chip block RAM pool, thereby achieving complete overlap between computation and data transport on the time axis and forming a continuous data supply stream.

[0077] The runtime security scheduler includes: a true random number generator, a protection operation microcode library, and a scheduling state machine;

[0078] The protection operation microcode library stores a variety of hardware operation sequences that have no actual computational meaning and are used to change the power consumption characteristics or state of the circuit.

[0079] The scheduling state machine is connected to the true random number generator, the protection operation microcode library, and the dynamic resource management and scheduling center, respectively. It is used to select the corresponding protection operation microcode from the protection operation microcode library based on the random number output by the true random number generator, the current computing pipeline status fed back by the dynamic resource management and scheduling center, and the pre-loaded security level configuration, and to determine when to insert it into the unified scheduling flow.

[0080] It should be further explained that the runtime security scheduler comprises three main functional modules. The true random number generator continuously generates a random bit stream based on physical entropy sources, such as the phase jitter of a ring oscillator or the output of a metastable circuit. The protective operation microcode library is a non-volatile memory that stores a variety of pre-designed short instruction sequences. When executed, these instruction sequences trigger specific power consumption or electromagnetic radiation patterns in the hardware circuitry, differing from normal data operations. However, their operations target redundant registers, pseudo-address buses, or idle arithmetic units, and do not alter the actual data state related to the correctness of the cryptographic algorithm. Exemplary instruction sequences include continuously toggling a set of shadow registers parallel to the data path, triggering a modular multiplication address generation cycle with a fixed invalid operand as input, or creating brief switching activities on specific global signal lines.

[0081] The scheduling state machine is a finite state automaton that internally maintains the current security policy configuration register. This state machine continuously receives current computation pipeline state signals from the dynamic resource management and scheduling center, indicating the busy level of the computation clusters and potential microinstruction gaps in the unified scheduling flow. Simultaneously, the state machine samples the output of the true random number generator in real time.

[0082] Based on three types of inputs—security policy, pipeline state, and random sampled values—the scheduling state machine dynamically determines two key parameters through its internal state transition logic and lookup tables: which specific instruction sequence should be selected from the protection operation microcode library at the current moment, and at which relative time position in the unified scheduling flow that instruction sequence should be submitted. After making the decision, the scheduling state machine sends the selected protection operation microcode fragment, along with its insertion timing information, to the microcode sequence generator in the dynamic resource management and scheduling center.

[0083] When orchestrating a unified scheduling flow, the dynamic resource management and scheduling hub mixes protective operation microcode from the runtime safety scheduler with normal computation microcode from the computation task parsing. This allows the protective operation microcode to be inserted into the execution gaps of the normal computation instruction flow without introducing independent, predictable idle clock cycles.

[0084] It should be further explained that the microcode sequence generator inside the dynamic resource management and scheduling center is responsible for implementing the hybrid orchestration of instruction streams. This generator simultaneously receives two input streams: one is the normal computation microcode sequence generated by its internal task parser based on the current computation kernel algorithm steps, where each microcode in the sequence is marked with the number of logical clock cycles required for its execution and operand dependencies; the other is the protective operation microcode fragment submitted by the runtime safety scheduler along with an attached timestamp, which indicates the relative time window in which the fragment is expected to be executed.

[0085] The microcode sequence generator first performs timing analysis on the normal computation microcode sequence, constructing a fine-grained execution timing graph based on the dependencies between microcodes. This graph identifies idle periods in hardware execution units that inevitably occur due to reasons such as data insecurity, resource contention, or control flow jumps. Subsequently, the generator treats protective operation microcode fragments as a special type of data-independent padding microcode and dynamically assigns appropriate insertion positions to each protective microcode fragment based on its timestamp and the distribution of idle periods in the current timing graph.

[0086] The insertion operation is completed during the microcode instruction register loading stage. The generator directly arranges the protection microcode into the instruction gaps of the normal microcode sequence, so that in the final physical execution pipeline, the execution of the protection operation is closely connected with the execution of the normal computation microcode before and after in terms of timing, sharing the same pipeline-level resources, without needing to pause the pipeline or insert a special no-operation cycle for this purpose.

[0087] In this way, the execution time of the protective operation is hidden within the micro-instruction stream of normal computation, and its appearance and timing are not fixedly related to the specific data operation process from the perspective of external observation.

[0088] The dynamic resource management and scheduling center performs the following steps to achieve system control:

[0089] S1: Receives and parses cryptographic tasks, decomposing the tasks into multiple computational kernels with dependencies;

[0090] S2: For the currently executing computation kernel, dynamically configure the reconfigurable NTT computation cluster unit to form a matching operation cluster, and allocate a data storage area for the computation kernel in the streaming polynomial coefficient cache network;

[0091] S3: Generates a unified scheduling flow, in which synchronization includes: computation control microcode that controls the computation cluster to perform computations, data transport instructions that control the data transport engine to perform data prefetching and write-back, and protection operation microcode provided by the runtime security scheduler;

[0092] S4: Issue and execute a unified scheduling flow to enable computation, data transfer and security protection operations to be carried out in a coordinated manner;

[0093] S5: During task execution, monitor the utilization rate of the computing cluster and the access status of the streaming multinomial coefficient cache network. If the performance indicators are lower than the preset threshold, trigger dynamic reconfiguration of the internal connection or data prefetching strategy of the computing cluster.

[0094] It should be further explained that the dynamic resource management and scheduling hub coordinates and controls the entire system through its internally fixed control process, which consists of five ordered steps. In step S1, the hub's task parser receives cryptographic operation task instructions from the host interface. These instructions include the operation type and related parameters. Based on the pre-stored Kyber algorithm operation graph, the parser decomposes the task into multiple computational kernels with clear dependencies, such as sequentially executing kernels for polynomial sampling, number theory transformation, coefficient dot product, and inverse number theory transformation, and generates metadata describing the computational characteristics and resource requirements of each kernel.

[0095] In step S2, for the computing kernel currently to be scheduled, the central resource mapper performs dynamic configuration of computing resources based on its metadata and the real-time hardware status obtained from the resource status table: it sends a configuration instruction word containing specific connection topology information to the reconfigurable NTT computing cluster unit, so that its internal interconnection network is reorganized to form a computing cluster adapted to the kernel; at the same time, it plans the storage path for the data required by the kernel in the streaming multinomial coefficient cache network, allocates the corresponding memory bank set in the butterfly operation dedicated cache, and initializes the relevant address mapping table.

[0096] Step S3 is to generate a unified scheduling flow. The central microcode generator generates a computation microcode sequence based on the algorithm steps of the computation kernel. Its data transport controller generates a prefetch and write-back instruction sequence according to the kernel's data flow pattern, and synchronously receives protection operation microcode fragments provided by the runtime security scheduler. An instruction orchestrator integrates these microinstructions and instructions from different sources into a continuous instruction flow that can be directly executed by the hardware, according to the computation timing, data dependencies, and the insertion requirements of the protection microcode.

[0097] In step S4, the unified scheduling flow is sent out through the control bus, and the central pipeline controller supervises its execution to ensure that the computing cluster performs calculations according to the computing microcode, the data transfer engine performs data migration according to the transfer instructions, and the three proceed synchronously in strict accordance with the timing of the instruction flow arrangement.

[0098] Step S5 is the continuous monitoring and optimization phase. The performance counter built into the central hub collects the utilization information of functional units in the computing cluster and the access hit and conflict information of the cache network in real time. A monitoring analyzer periodically analyzes these performance data. If it finds that a certain indicator is consistently lower than a preset threshold, such as a specific computing unit being idle too much due to data dependency, or regular cache access conflicts, the monitoring analyzer will trigger a reconfiguration request. Based on this, the resource mapper will adjust the fine connection of the computing cluster or the prefetching strategy of the data transport engine online without interrupting the current kernel execution, so as to optimize the efficiency of subsequent execution.

[0099] In step S3, generating a unified scheduling flow specifically includes:

[0100] S31: Based on the data access mode of the computing kernel, it generates a data prefetch instruction sequence from the on-chip block RAM pool to the butterfly operation dedicated cache;

[0101] S32: Generate a computation control microcode sequence based on the configuration of the arithmetic cluster and the algorithm steps of the computation kernel;

[0102] S33: While generating the computation control microcode sequence, protective operation microcodes are inserted into the instruction gaps of the computation control microcode sequence according to the output of the runtime security scheduler, forming a hybrid microcode sequence;

[0103] S34: Combine the data prefetch instruction sequence, the hybrid microcode sequence, and the corresponding data write-back instruction sequence into a unified scheduling flow according to the timing dependency relationship.

[0104] It should be further explained that in the specific steps of generating a unified scheduling flow, dynamic resource management and multiple dedicated sub-modules within the scheduling hub work together. Its data flow controller first analyzes the current computing kernel's data access pattern, which predefines the layout of coefficient data in the on-chip block RAM pool and the reading order during computation. Based on this pattern, the data flow controller generates a series of data prefetch instruction sequences with explicit source address, destination address, and data block length information. This sequence aims to guide the data transport engine to move the required data from the on-chip block RAM pool to the butterfly operation-specific cache before and during computation.

[0105] At the same time, the microcode generator generates corresponding computation control microcode sequences based on the current dynamically configured computing cluster topology for the computing kernel and the algorithm operation steps represented by the kernel. Each microcode in the sequence specifies the operation type and operand source that a specific basic computing unit in the computing cluster should perform in a specific clock cycle.

[0106] During the generation of the computation control microcode sequence, the instruction orchestrator receives in real time the protective operation microcode fragments and their expected execution timing information from the runtime safety scheduler. The instruction orchestrator contains a timing analysis unit that parses the computation control microcode sequence and identifies clock cycle intervals where hardware execution units are necessarily idle due to data dependencies between microcodes or pipeline control. Subsequently, the orchestrator dynamically inserts the protective operation microcode fragments as filling units into these identified idle intervals. If multiple idle intervals are available, the interval closest to the expected timing of the protective microcode is selected first, thus forming a hybrid microcode sequence in which computation microcode and protective microcode are interleaved.

[0107] Finally, based on the global timing dependency graph of the computation kernel, the synthesizer writes the previously generated data prefetch instruction sequence, hybrid microcode sequence, and corresponding results back to the instruction sequence, aligns and packages them according to their inherent order and synchronization relationship, and combines them into a unified scheduling stream containing multiple types of instructions that can be read and executed sequentially by the hardware pipeline controller.

[0108] The butterfly operation-specific cache of the streaming multinomial coefficient caching network employs a multi-bank parallel and interleaved storage organization method as follows: coefficient pairs required for different butterfly operations within the same round are stored in different memory banks; when the computation cluster executes a round of butterfly operations, it can simultaneously read all the coefficient pairs required for that round of operations from multiple memory banks through a single parallel access operation. It should be further explained that the multi-bank parallel and interleaved storage organization of the butterfly operation-specific cache is specifically implemented through its internal address mapping logic and physical structure. This dedicated cache consists of multiple independently addressable static random access memory banks, each with its own independent read / write port. The core of the address mapping logic is a configurable address translation unit, which receives the logical address index contained in the access request issued by the dynamic resource management and scheduling center or the computation cluster.

[0109] Based on the number theory transformation cycle information currently being executed, the transformation unit maps the logical addresses of multiple coefficients or coefficient pairs belonging to the same round of operation but used for different butterfly calculation pairs to different physical memory cell numbers through preset bit order reversal, modular addition, or specific offset calculation rules, and at the same time generates word line addresses within each memory cell.

[0110] For example, in a round of computation involving multiple butterfly operations, the transformation unit ensures that the address of the first operand required by the i-th butterfly operation is mapped to memory bank A, its corresponding second operand address is mapped to memory bank B, and the operand addresses of the (i+1)-th butterfly operation are mapped to memory banks C and D, and so on. When the arithmetic cluster needs to execute this round of computation, its access request is passed through this transformation unit and simultaneously decomposed into multiple parallel sub-requests, each pointing to a different physical memory bank. These memory banks operate concurrently within the same clock cycle, each reading or writing data to its designated internal address.

[0111] Subsequently, the data read from each storage unit passes through an alignment and routing network, is organized and distributed according to the operand pairings required by the computing cluster, and is finally delivered simultaneously to the corresponding basic computing units in the computing cluster.

[0112] This mechanism ensures that a single access operation can obtain all operands for a complete butterfly operation, perfectly matching the data supply bandwidth with the parallel processing capability of the computing cluster, and eliminating latency caused by memory serialization access or resource contention. The address mapping relationship can be fine-tuned by the dynamic resource management and scheduling center according to different algorithm stages or configurations to adapt to different parallelism requirements.

[0113] A high-speed hardware acceleration method for Kyber quantum-resistant cryptography algorithms, executed by a dynamic resource management and scheduling center in a high-speed hardware acceleration system, includes the following steps:

[0114] a: Receive cryptographic operation task instructions and security level configuration;

[0115] b: Deconstruct the cryptographic operation task by breaking it down into multiple ordered computational kernels;

[0116] c: Dynamically configure reconfigurable NTT computing cluster units for the current computing kernel to form an adapted computing cluster topology;

[0117] d: Based on the data access characteristics of the current computing kernel, plan the data storage path in the streaming multinomial coefficient cache network and start data prefetching;

[0118] e: Obtain the protection operation microcode generated by the runtime security scheduler based on the security level configuration and random signals;

[0119] f: Generate a unified scheduling flow, in which computation control microcode, data transfer instructions, and protection operation microcode are mixed and arranged, so that protection operations are completed in the gaps between the execution of computation instruction flow;

[0120] g: Executes a unified scheduling flow, controls the collaborative work of the computation clusters and streaming polynomial coefficient buffer network, completes cryptographic operations, and outputs the results.

[0121] It should be further explained that the high-speed hardware acceleration method is executed by the dynamic resource management and scheduling hub in the system. Its process begins with receiving cryptographic computation task instructions and corresponding security level configuration parameters from the host interface. The hub's task parser first parses the instruction, identifies the operation type as encapsulation, decapsulation, or key generation, and decomposes the entire task into a series of computational kernels with strict sequential dependencies based on the pre-stored Kyber algorithm execution graph. These kernels include polynomial sampling kernels, number theory transformation kernels, coefficient dot product kernels, and inverse number theory transformation kernels. Each kernel is assigned a unique identifier and resource requirement description.

[0122] For the currently executing computing kernel, the central resource allocator initiates a dynamic configuration process: it queries a predefined configuration template based on the kernel identifier, generates configuration instructions containing a specific connection matrix, and sends them to the reconfigurable NTT computing cluster unit via the control bus, enabling the on-chip interconnect network within the unit to reconnect and combine a group of basic computing units into an operational cluster topology adapted to the kernel's computing mode; simultaneously, the allocator allocates a dedicated data storage area for the kernel in the streaming polynomial coefficient cache network, including delineating several memory banks in the butterfly operation dedicated cache, and setting the corresponding source address pointer, destination address pointer, and data block length register in the data transport engine.

[0123] Next, the central dataflow planner, based on the kernel's predefined data access pattern, generates initial data prefetch instructions and activates the data transfer engine, beginning the transfer of the first batch of computational data from the on-chip block RAM pool to the butterfly operation-specific cache. During this process, the central instruction interface continuously receives protective operation microcode fragments dynamically generated by the runtime security scheduler based on the current security level configuration and the output of the internal true random number generator.

[0124] Subsequently, the central microcode synthesizer begins operation. It integrates the algorithm steps of the computation kernel, the configured arithmetic cluster structure, and the received protection microcode to generate a unified scheduling flow. The synthesizer first arranges the normal computation control microcode sequence, then analyzes the timing of the sequence, identifies hardware idle periods caused by instruction dependencies, and dynamically inserts protection operation microcode into these idle periods to form a mixed microcode instruction flow. At the same time, the synthesizer coordinates the prefetch and write-back instructions of the data transfer engine, aligning them with the mixed microcode flow on the time axis to ensure that data supply and computation consumption are synchronized.

[0125] Finally, the central pipeline controller loads this unified scheduling flow into the execution queue, sequentially issues micro-instructions to control the computing clusters to perform cryptographic calculations, controls the cache network to perform data flow, and returns the final calculation results through the output interface. Throughout the entire execution process, the protection operations are seamlessly integrated into the computing pipeline.

[0126] After generating the unified scheduling flow but before execution, optimization steps are also included:

[0127] Analyze the timing relationship between computation microcode and data transfer instructions in the unified scheduling flow to identify idle periods of computing units that may occur due to data dependencies;

[0128] Adjust the insertion position of the protection operation microcode in the unified scheduling flow, and prioritize filling the identified idle time periods with the protection operation microcode.

[0129] It should be further explained that after generating the unified scheduling flow but before the hardware executes it, the dynamic resource management and scheduling center performs a dedicated instruction flow optimization step. This step is implemented by a separate timing analysis unit.

[0130] The timing analysis unit first performs a combination of static and dynamic analysis on the generated unified scheduling flow: static analysis constructs a preliminary microinstruction execution timing diagram based on the microinstruction's opcode, operand address, and predefined microinstruction execution latency cycle number; dynamic analysis further refines the timing diagram by combining the actual configuration state of the current computing cluster and the transmission latency model of the data transport engine, accurately identifying the clock cycles that inevitably arise due to strict data dependencies between microinstructions, resource structure conflicts, or control flow waiting, during which the hardware functional unit cannot execute effective computation microinstructions. These cycles are marked as available idle periods.

[0131] Simultaneously, this unit maintains an idle time slot mapping table associated with the current scheduling flow, recording the start clock offset, duration, and corresponding hardware unit type of each idle time slot. Subsequently, the optimizer matches each protection operation microcode fragment provided by the runtime security scheduler with the records in the idle time slot mapping table, based on its own execution duration and required hardware resource type. The matching strategy follows a preset priority rule: priority is given to idle time slots that fully accommodate the protection microcode execution length in time and match the hardware resource type; if multiple candidates exist, the time slot closest in time to the original expected insertion point associated with the protection microcode is selected.

[0132] After a successful match, the optimizer will modify the order of micro-instructions in the unified scheduling flow, moving the instruction word of the protection operation microcode from its original temporary position to the instruction slot corresponding to the final determined target idle time period, and may adjust the positions of adjacent, undependent normal micro-instructions accordingly to maintain overall semantic correctness.

[0133] Through this optimization step, the protective operations are more tightly "woven" into the instruction gaps of normal computation, further reducing the correlation between their execution time and specific data computation processes. Only then is the optimized unified scheduling flow finally submitted to the hardware pipeline controller for execution.

[0134] By centrally coordinating reconfigurable computing clusters, streaming cache networks, and a secure scheduler through dynamic resource management and scheduling, the system achieves dynamic optimization and combination of computing resources according to algorithm stages. This results in deep overlap between data supply and the computing pipeline, effectively improving the overall system throughput and response speed while reducing idle losses caused by fixed resource allocation or data waiting. The flexible reconfiguration and reuse capabilities of hardware resources enable the same set of physical units to efficiently adapt to different core computational modes in the Kyber algorithm, improving hardware utilization efficiency.

[0135] Meanwhile, by seamlessly inserting and filling the inherent gaps in the computation instruction stream with runtime-generated protective operation microcode, synchronous integration of security protection and normal computation is achieved at the hardware level. This approach increases the difficulty of side-channel analysis and enhances the system's physical security without occupying an additional full clock cycle or interfering with the normal data flow. The collaborative architecture of these three elements enables the system to possess excellent adaptability and overall performance when dealing with diverse cryptographic tasks and security threats.

[0136] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0137] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A high-speed hardware acceleration system for Kyber quantum-resistant cryptographic algorithm, integrated in a programmable logic device or an application-specific integrated circuit, characterized in that, include: Dynamic resource management and scheduling hub, reconfigurable NTT computing cluster unit, streaming polynomial coefficient cache network, and runtime safe scheduler; The dynamic resource management and scheduling hub is connected to the reconfigurable NTT computing cluster unit, the streaming multinomial coefficient cache network, and the runtime security scheduler, respectively. It is used to receive cryptographic operation instructions, parse the operation tasks into computing kernels, dynamically allocate and configure computing and storage resources for each computing kernel, generate a unified scheduling flow containing computing control microcode and data transfer instructions, and monitor the system status to trigger dynamic optimization. The reconfigurable NTT computing cluster unit is connected to the dynamic resource management and scheduling center. It is used to dynamically combine multiple basic computing units into a computing cluster that executes the topology required by a specific computing kernel according to the configuration instructions of the dynamic resource management and scheduling center, and to perform number theory transformation, inverse number theory transformation and modular operation under the control of the scheduling flow. The streaming polynomial coefficient caching network is connected to the dynamic resource management and scheduling center and the reconfigurable NTT computing cluster unit. It is used to hierarchically store polynomial coefficients and intermediate data, and according to the data transfer instructions issued by the dynamic resource management and scheduling center, it streams the computation data and writes back the results in a manner that overlaps with the computation process of the reconfigurable NTT computing cluster unit. The runtime security scheduler is connected to the dynamic resource management and scheduling center. During the algorithm execution process, it dynamically generates hardware-level protection operation microcode based on the preset security policy and random signals, and then encodes the protection operation microcode into the unified scheduling flow by the dynamic resource management and scheduling center. When orchestrating the unified scheduling flow, the dynamic resource management and scheduling center mixes the protective operation microcode from the runtime security scheduler with the normal computation microcode from the computation task parsing, so that the protective operation microcode is inserted into the execution gaps of the normal computation instruction flow without introducing independent, predictable idle clock cycles.

2. The high-speed hardware acceleration system for Kyber quantum-resistant cryptographic algorithm of claim 1, wherein: The reconfigurable NTT computing cluster unit includes multiple basic computing units and an on-chip interconnect network; The basic computing unit includes: a Montgomery modular multiplier core, an arithmetic logic array configurable to perform modular addition or modular subtraction operations, and a local coefficient register file; The on-chip interconnect network connects multiple basic computing units, and its connection path can be changed by the configuration of the dynamic resource management and scheduling center; The dynamic resource management and scheduling hub dynamically combines a group of basic computing units into an operational cluster that executes the current computing kernel by configuring the working modes of the on-chip interconnect network and the arithmetic logic array within the basic computing unit.

3. The high-speed hardware acceleration system for Kyber quantum-resistant cryptographic algorithm of claim 2, wherein: The streaming polynomial coefficient cache network includes: a coefficient register window, a dedicated cache for butterfly operations, an on-chip block RAM pool, and a data transfer engine; The coefficient register window is set within each of the basic computing units and is used to temporarily store the individual coefficients currently participating in the calculation; The dedicated cache for butterfly operations has a storage structure that matches the access mode of butterfly operations in number theory transformations. It adopts a multi-volume parallel and interleaved storage method to provide all the coefficient pairs required for a single round of butterfly operations for one of the operation clusters. The on-chip block RAM pool is used to store complete polynomial or matrix data blocks; The data transfer engine is connected to the butterfly operation dedicated cache and the on-chip block RAM pool, and is also connected to the dynamic resource management and scheduling center. It is used to perform prefetch and write-back operations of coefficient data between the on-chip block RAM pool and the butterfly operation dedicated cache according to the prediction of the dynamic resource management and scheduling center.

4. The high-speed hardware acceleration system for Kyber quantum-resistant cryptography algorithm according to claim 3, wherein: The runtime security scheduler includes: a true random number generator, a protection operation microcode library, and a scheduling state machine; The protection operation microcode library stores a variety of hardware operation sequences that have no actual computational meaning and are used to change the power consumption characteristics or state of the circuit. The scheduling state machine is connected to the true random number generator, the protection operation microcode library, and the dynamic resource management and scheduling center, respectively. It is used to select the corresponding protection operation microcode from the protection operation microcode library based on the random number output by the true random number generator, the current computing pipeline status fed back by the dynamic resource management and scheduling center, and the pre-loaded security level configuration, and to determine the timing of its insertion into the unified scheduling flow.

5. The high-speed hardware acceleration system for Kyber quantum-resistant cryptographic algorithm of claim 1, wherein: The dynamic resource management and scheduling center performs the following steps to achieve system control: S1: Receives and parses cryptographic tasks, decomposing the tasks into multiple computational kernels with dependencies; S2: For the computing kernel to be executed, dynamically configure the reconfigurable NTT computing cluster unit to form a matching operation cluster, and allocate a data storage area for the computing kernel in the streaming polynomial coefficient cache network; S3: Generate the unified scheduling flow, wherein synchronization includes: computation control microcode that controls the computation cluster to perform computation, data transfer instructions that control the data transfer engine to perform data prefetching and write-back, and protection operation microcode provided by the runtime security scheduler; S4: Issue and execute the unified scheduling flow to enable computation, data transfer and security protection operations to be performed in a coordinated manner; S5: During task execution, monitor the utilization rate of the computing cluster and the access status of the streaming polynomial coefficient cache network. If the performance index is lower than the preset threshold, trigger dynamic reconfiguration of the internal connection or data prefetching strategy of the computing cluster.

6. The high-speed hardware acceleration system for Kyber quantum-resistant cryptography algorithm of claim 3, wherein: In step S3, generating the unified scheduling flow specifically includes: S31: Based on the data access mode of the computing kernel, generate a data prefetch instruction sequence from the on-chip block RAM pool to the butterfly operation dedicated cache; S32: Based on the configuration of the computing cluster and the algorithm steps of the computing kernel, generate a computing control microcode sequence; S33: While generating the computation control microcode sequence, the protective operation microcode is inserted into the instruction gaps of the computation control microcode sequence according to the output of the runtime security scheduler, forming a hybrid microcode sequence; S34: The data prefetch instruction sequence, the hybrid microcode sequence, and the corresponding data write-back instruction sequence are combined into the unified scheduling flow according to the time-series dependency relationship.

7. The high-speed hardware acceleration system for Kyber quantum-resistant cryptography algorithm according to claim 6, wherein: The butterfly operation-specific cache of the streaming polynomial coefficient cache network is organized in a multi-bank parallel and interleaved manner as follows: coefficient pairs required for different butterfly operations belonging to the same round are stored in different storage banks; when the operation cluster performs a round of butterfly operation, all coefficient pairs required for that round of operation can be read simultaneously from multiple storage banks through a single parallel access operation.

8. A high-speed hardware acceleration method for Kyber quantum-resistant cryptographic algorithm, characterized in that, The method, executed by the dynamic resource management and scheduling center in the high-speed hardware acceleration system as described in any one of claims 1 to 7, comprises: a: Receive cryptographic operation task instructions and security level configuration; b: Parse the cryptographic operation task and decompose it into multiple ordered computational kernels; c: Dynamically configure reconfigurable NTT computing cluster units for the current computing kernel to form an adapted computing cluster topology; d: Based on the data access characteristics of the current computing kernel, plan the data storage path in the streaming multinomial coefficient cache network and start data prefetching; e: Obtain the protection operation microcode generated by the runtime security scheduler based on the security level configuration and random signals; f: Generate a unified scheduling flow, in which computation control microcode, data transfer instructions and the protection operation microcode are mixed and arranged, so that the protection operation is completed in the execution gap of the computation instruction flow; g: Execute the unified scheduling flow, control the operation cluster and the streaming polynomial coefficient cache network to work together, complete the cryptographic operation and output the result.

9. The method of claim 8, wherein the method is a high-speed hardware acceleration method for Kyber quantum-resistant cryptographic algorithm. After generating the unified scheduling flow but before execution, an optimization step is also included: Analyze the timing relationship between computation microcode and data transfer instructions in the unified scheduling flow to identify idle periods of computing units that may occur due to data dependencies; Adjust the insertion position of the protection operation microcode in the unified scheduling flow, and prioritize filling the identified idle time periods with the protection operation microcode.

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