Schottky diode and method of manufacturing the same

Abstract

The present application relates to a kind of Schottky diode and its manufacturing method, Schottky diode includes: first conductive type area, including anode area, cathode area and located between the depletion pinch zone of anode area and cathode area;Schottky metal layer, on anode area;Cathode metal, on cathode area;First well region, with first conductive type, for the annular structure of first conductive type area outside;First conductive type buried region, below first conductive type area and the first well region, with the bottom of first well region and form first conductive type isolation structure;First conductive structure is configured as when Schottky diode is forward working, to the first well region, the potential of first conductive type isolation structure is higher than the potential of substrate by adding voltage.The present application is surrounded by the periphery and bottom of Schottky diode by first conductive type isolation structure, to effectively inhibit the opening of parasitic triode, reduce substrate leakage current.

Description

Technical Field

[0001] This invention relates to the field of semiconductor manufacturing, and in particular to a Schottky diode, and also to a method for manufacturing a Schottky diode. Background Technology

[0002] Schottky diodes are characterized by low forward turn-on voltage and high reverse breakdown voltage. The BCD (Bipolar-CMOS-DMOS) process platform often employs a vertical well pinch-off method to achieve reverse breakdown voltage. Due to the presence of a vertical parasitic PNP in this structure, the Schottky diode generates a large substrate leakage current during forward operation. Summary of the Invention

[0003] Therefore, it is necessary to provide a Schottky diode with low substrate leakage current and its manufacturing method.

[0004] A Schottky diode includes: a first conductivity type region comprising an anode region, a cathode region, and a depletion pinch-off region located between the anode region and the cathode region; a Schottky metal layer located on the anode region, contacting the upper surface of the anode region to form a Schottky barrier, the Schottky metal layer serving as the anode of the Schottky diode; a cathode metal layer located on the cathode region, forming an ohmic contact with the upper surface of the cathode region, the cathode metal serving as the cathode of the Schottky diode; a first well region having a first conductivity type, being a ring structure located outside the first conductivity type region; and a first conductivity type buried region located on the first conductivity type region. Below the type region and the first well region, connected to the bottom of the first well region; the first well region and the first conductivity type buried region are connected together to form a first conductivity type isolation structure, thereby surrounding the sides and bottom of the first conductivity type region; a substrate having a second conductivity type, at least a portion of the substrate being located below the first conductivity type buried region; the first conductivity type and the second conductivity type are opposite conductivity types; a first conductive structure connected to the first well region; the first conductive structure is configured to apply a potential to the first well region such that the potential of the first conductivity type isolation structure is higher than the potential of the substrate when the Schottky diode is in forward operation.

[0005] The aforementioned Schottky diode has a first conductivity type isolation structure that surrounds the sides and bottom of the first conductivity type region. In other words, the first conductivity type isolation structure surrounds the periphery and bottom of the Schottky diode, and by applying an external potential to the first well region to make it higher than the substrate potential, the turn-on of the parasitic transistor is effectively suppressed and the substrate leakage current is reduced.

[0006] In one embodiment, the depletion pinch-off region includes a mesh structure, and the Schottky diode further includes a second conductivity type region located between the anode region and the cathode region, the second conductivity type region serving as the mesh of the mesh structure.

[0007] In one embodiment, the second conductive type region and the mesh structure are arranged in an alternating grid pattern on a plane.

[0008] In one embodiment, the Schottky diode further includes: a third well region having a first conductivity type, located in the first well region, wherein the doping concentration of the third well region is greater than that of the first well region; a first doped region having a first conductivity type, located in the third well region, wherein the doping concentration of the first doped region is greater than that of the third well region; and a first conductive structure being in direct contact with the first doped region.

[0009] In one embodiment, the Schottky diode further includes: a second well region having a second conductivity type, the second well region being an annular structure located outside the first conductivity type region and between the first conductivity type region and the first well region; a second conductivity type buried region located below the first conductivity type region, the second conductivity type region, and the second well region, connected to the second conductivity type region and the second well region, and the second conductivity type buried region being located between the first conductivity type buried region and the first conductivity type region; a second conductive structure connected to the second well region for applying a potential to the second well region; the first conductive structure is configured to apply a potential to the first well region such that, when the Schottky diode is in forward operation, the potential of the first conductivity type isolation structure is higher than the potential of the second conductive structure.

[0010] In one embodiment, the doping concentration of the second conductivity type region is greater than the doping concentration of the substrate.

[0011] In one embodiment, the Schottky diode further includes: a fourth well region located outside the first well region and connected to the substrate; and a third conductive structure connected to the fourth well region for applying an external potential to the substrate.

[0012] In one embodiment, the Schottky diode further includes a first shallow trench isolation structure located between the cathode region and the anode region, above the mesh structure.

[0013] In one embodiment, the depletion pinch-off region includes a plurality of first strips and a plurality of second strips, one end of each first strip is connected to the cathode region and the other end is connected to the mesh structure, one end of each second strip is connected to the anode region and the other end is connected to the mesh structure, a portion of the second conductivity type region is filled between adjacent first strips, and a portion of the second conductivity type region is filled between adjacent second strips.

[0014] A method for manufacturing a Schottky diode includes: obtaining a wafer in which a first conductivity type buried region is formed in a substrate; the substrate having a second conductivity type; forming an annular first well region on the first conductivity type buried region; the first conductivity type buried region being connected to the bottom of the first well region, the first well region having a first conductivity type; forming a first conductivity type region in the area surrounded by the first conductivity type buried region and the first well region; the first conductivity type region including an anode region, a cathode region, and a depletion pinch-off region located between the anode region and the cathode region; forming a Schottky metal layer and a cathode metal; and the... A Schottky metal layer is formed on the anode region, contacting the upper surface of the anode region to form a Schottky barrier, and the Schottky metal layer serves as the anode of the Schottky diode; a cathode metal layer is formed on the cathode region, forming an ohmic contact with the upper surface of the cathode region, and the cathode metal serves as the cathode of the Schottky diode; a first conductive structure is formed, the first conductive structure being connected to the first well region; the first conductive structure is configured to apply a potential to the first well region, such that the potential of the first well region and the first conductivity type buried region is higher than the potential of the substrate, when the Schottky diode is in forward operation.

[0015] The above-mentioned method for manufacturing a Schottky diode involves forming a first conductivity type isolation structure that surrounds the sides and bottom of the first conductivity type region. In other words, the first conductivity type isolation structure surrounds the periphery and bottom of the Schottky diode. By applying an external potential to the first well region to make it higher than the substrate potential, the turn-on of the parasitic transistor is effectively suppressed, and the substrate leakage current is reduced.

[0016] In one embodiment, the step of forming a third well region in the first well region is included while forming the first conductivity type region; the first conductivity type region and the third well region are formed by ion implantation, and the implantation windows of the first conductivity type region and the third well region are formed by photolithography using the same photomask; the third well region has a first conductivity type, and the doping concentration of the third well region is greater than that of the first well region.

[0017] In one embodiment, prior to the step of forming the first conductivity type region, the method further includes a step of forming a second conductivity type buried region within the area surrounded by the first conductivity type buried region and the first well region; the first conductivity type region is formed on the second conductivity type buried region; the manufacturing method further includes a step of forming the second conductivity type region and the second well region by ion implantation; the second conductivity type region is formed between the anode region and the cathode region, the depletion pinch-off region includes a mesh structure, and the second conductivity type region serves as the mesh of the mesh structure; the second well region has a second conductivity type, and the second well region is an annular structure located outside the first conductivity type region and between the first conductivity type region and the first well region; the implantation windows of the second conductivity type region and the second well region are formed by photolithography using the same photomask. Attached Figure Description

[0018] To better describe and illustrate embodiments and / or examples of the inventions disclosed herein, reference may be made to one or more accompanying drawings. Additional details or examples used to describe the drawings should not be considered as limiting the scope of any of the disclosed inventions, the currently described embodiments and / or examples, or the best mode of these inventions as currently understood.

[0019] Figure 1 This is an exemplary Schottky diode structure for a BCD process platform.

[0020] Figure 2 This is a structural diagram of a Schottky diode in one embodiment of this application.

[0021] Figure 3 This is a photolithographic pattern of a portion of the film layer of a Schottky diode in one embodiment of this application.

[0022] Figure 4a and Figure 4b This is a partial enlarged view of the region where the depletion pinch-off region 224 is located in one embodiment of this application.

[0023] Figure 5 This is a flowchart of a method for manufacturing a Schottky diode according to one embodiment of this application.

[0024] Figures 6a to 6c This is a cross-sectional structural diagram of a Schottky diode during the manufacturing process in one embodiment of this application. Detailed Implementation

[0025] To facilitate understanding of the present invention, a more complete description will be given below with reference to the accompanying drawings. Preferred embodiments of the invention are shown in the drawings. However, the invention can be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items.

[0027] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0028] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0029] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0030] Embodiments of the invention are described herein with reference to cross-sectional views that serve as schematic diagrams of ideal embodiments (and intermediate structures). Thus, variations in the shape shown can be anticipated due to, for example, manufacturing techniques and / or tolerances. Therefore, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing processes. For example, implantation regions shown as rectangular typically have rounded or curved features at their edges and / or implantation concentration gradients, rather than a binary change from implantation regions to non-implantation regions. Similarly, the buried regions formed by implantation can result in some implantation in the region between the buried region and the surface traversed during implantation. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shapes of the regions of the device and are not intended to limit the scope of the invention.

[0031] The semiconductor terminology used in this article is the technical terminology commonly used by those skilled in the art. For example, for P-type and N-type impurities, in order to distinguish the doping concentration, P+ type represents heavily doped P-type, P type represents moderately doped P-type, P- type represents lightly doped P-type, N+ type represents heavily doped N-type, N type represents moderately doped N-type, and N- type represents lightly doped N-type.

[0032] Figure 1 This is an exemplary Schottky diode structure based on a BCD process platform, comprising a substrate 110, a buried N-well 122, a deep N-well 124, an N-well 126, and a P-well 132. The current path of the Schottky diode during forward operation is as follows... Figure 1 As shown by the dashed arrow, current flows from the Anode (anode) through the deep N-well 124 to the Cathode (cathode). The current capability is increased by increasing the active region area at the Anode. When the Schottky diode operates in reverse, the Cathode is connected to a high voltage. The current path is cut off by the N-well 124, which depletes the active region through the P-well 132, thus achieving reverse withstand voltage. Figure 1 The dashed elliptical region in the middle represents the corresponding depletion pinch-off region.

[0033] However, Figure 1 When the Schottky diode shown is in forward operation, the diode composed of P-well 132-deep N-well 124 is turned on under high current conditions, which can easily trigger the parasitic PNP transistor composed of P-well 132-deep N-well 124-substrate 110 to turn on, resulting in an increase in substrate leakage current.

[0034] This application proposes a Schottky diode with a lateral fully isolated structure. An isolation structure is added to the bottom and periphery of the Schottky diode to suppress the turn-on of parasitic transistors, thereby effectively reducing substrate leakage current.

[0035] Figure 2 This is a structural diagram of a Schottky diode in one embodiment of the present application, including: a first conductivity type region 220, a first well region 232, a first conductivity type buried region 212, a substrate 210, and a first conductive structure 252. Figure 2 The structure is symmetrical about the first conductivity type region 220, therefore some structures are labeled only for one side. The first conductivity type region 220 includes an anode region 226, a cathode region 222, and a depletion pinch-off region 224 located between the anode region 226 and the cathode region 222. The Schottky diode also includes a Schottky metal layer located on the anode region 226. Figure 2 (not shown), and cathode metal located in cathode region 222 ( Figure 2 (Not shown in the image). The Schottky metal layer forms a Schottky barrier by contacting the upper surface of the anode region 226, and the Schottky metal layer serves as the anode of the Schottky diode. The cathode metal forms an ohmic contact with the upper surface of the cathode region 222, and the cathode metal serves as the cathode of the Schottky diode.

[0036] The first well region 232 has a first conductivity type and is a ring structure located outside the first conductivity type region 220. The first conductivity type buried region 212 is located below the first conductivity type region 220 and the first well region 232, and is connected to the bottom of the first well region 232. The first well region 232 and the first conductivity type buried region 212 are connected together to form a first conductivity type isolation structure, thereby surrounding the sides and bottom of the first conductivity type region 220. The substrate 210 has a second conductivity type, and at least a portion of the substrate 210 is located below the first well region 232 and the first conductivity type buried region 212. The first conductive structure 252 is electrically connected to the first well region 232. The first conductive structure 252 is configured to apply a potential to the first well region 232 such that the potential of the first conductivity type isolation structure is higher than the potential of the substrate 210 when the Schottky diode is in forward operation. That is, when the Schottky diode is operating in the forward direction (the voltage at the anode is greater than the voltage at the cathode), a potential is applied to the first well region 232 through the first conductive structure 252, making the potential of the first well region 232 and the first conductivity type buried region 212 higher than the potential of the substrate 210. Figure 2In the illustrated embodiment, the first conductivity type is N-type and the second conductivity type is P-type.

[0037] The aforementioned Schottky diode has a first conductivity type isolation structure that surrounds the sides and bottom of the first conductivity type region 220. That is, the first conductivity type isolation structure surrounds the periphery and bottom of the Schottky diode, and by applying an external potential to the first well region 232 to make it higher than the substrate potential, the parasitic transistor is effectively suppressed and the substrate leakage current is reduced.

[0038] Figure 3 This is a photolithographic pattern of a portion of the layers (film layers) of a Schottky diode in one embodiment of this application. Figure 3 A top view of the Schottky diode from an embodiment of this application can be viewed. In one embodiment of this application, the depletion pinch-off region 224 includes a mesh structure. Figure 3 The location (region) of the depletion pinch-off region 224 is outlined with a dashed box. The Schottky diode also includes a second conductivity type region 246 located between the anode region 226 and the cathode region 222. The second conductivity type region 246 serves as the mesh of this mesh structure, meaning that N-type and P-type regions are alternately distributed in a mesh pattern between the anode region 226 and the cathode region 222. In one embodiment of this application, the doping concentration of the second conductivity type region 246 is greater than the doping concentration of the substrate 210.

[0039] Figure 4a and Figure 4b This is a partial enlarged view of the region where the depletion pinch-off region 224 is located in one embodiment of this application. Figure 4a The black area in the image is the P-type region (i.e., the second conductivity type region 246). Figure 4b Compared to Figure 4a The added black dots represent pinch-off points. When the Schottky diode is operating in the forward direction, the current starts from the anode region 226, passes through the N-type region of the intermediate mesh structure, and flows to the cathode region 222. By setting the N-type region in the middle of the current path as a mesh structure, a structure like... Figure 4b The dots in the diagram indicate pinch-off points. When the Schottky diode is reverse biased, these pinch-off points are exhausted and pinched off by the surrounding P-type regions, thus blocking reverse leakage. The N-type regions at the locations of these dots are also the circuit flow nodes from the anode region 226 to the cathode region 222 when the Schottky diode is in forward operation.

[0040] Figure 1 The depletion pinch-off region of the Schottky diode shown (i.e. Figure 1The dashed elliptical region (as shown in the image) is limited by the implantation depth / concentration / critical dimension (CD) of the deep N-well 124 and process variations. In actual products, it is not possible to guarantee ideal pinch-off when the Schottky diode is operating in reverse. If even one N-type region of the deep N-well 124 is not depleted and pinched off, the reverse leakage current of the Schottky diode will increase sharply. However, the depletion pinch-off region 224 of the mesh structure shown in this embodiment has pinch-off points similar to a series structure when the Schottky diode is reverse biased. As long as some pinch-off points are pinched off, the reverse leakage current will be blocked, thus effectively reducing the risk of reverse leakage current.

[0041] In one embodiment of this application, the Schottky diode further includes a second well region 244, a second conductivity type buried region 242, and a second conductive structure 254. The second well region 244 has a second conductivity type and is a ring-shaped structure located outside the first conductivity type region 220, between the first conductivity type region 220 and the first well region 232. The second conductivity type buried region 242 is located below the first conductivity type region 220, the second conductivity type region 246, and the second well region 244, and is electrically connected to the second conductivity type region 246 and the second well region 244, and is located between the first conductivity type buried region 212 and the first conductivity type region 220. The second conductive structure 254 is electrically connected to the second well region 244 and is used to apply a potential to the second well region 244. The first conductive structure 252 is configured to apply a potential to the first well region 232 such that the potential of the first conductivity type isolation structure is higher than the potential of the second conductive structure 254 when the Schottky diode is operating in the forward direction. That is, the second conductivity type region 246 is brought out through the second conductivity type buried region 242, the second well region 244 and the second conductivity structure 254, and the potential of the second conductivity type region 246 is adjusted by applying a potential to the second conductivity structure 254.

[0042] In one embodiment of this application, the Schottky diode further includes a fourth well region 248 and a third conductive structure 256. The fourth well region 248 is located outside the first well region 232 and is electrically connected to the substrate 210. The third conductive structure 256 is electrically connected to the fourth well region 248 and is used to apply an external potential to the substrate 210. The potential of the substrate 210 can be conveniently controlled by the third conductive structure 256 to keep it lower than the potential of the first conductive structure 252 (i.e., lower than the potential of the first conductivity type isolation structure).

[0043] In one embodiment of this application, the Schottky diode further includes a first shallow trench isolation structure 262. The first shallow trench isolation structure 262 is located between the cathode region 222 and the anode region 226, above the depletion pinch-off region 224.

[0044] In one embodiment of this application, the depletion pinch-off region 224 includes a plurality of first strips and a plurality of second strips. One end of each first strip is connected to the cathode region 222 and the other end is connected to the mesh structure. One end of each second strip is connected to the anode region 226 and the other end is connected to the mesh structure. A portion of a second conductivity type region 246 is filled between adjacent first strips, and a portion of a second conductivity type region 246 is filled between adjacent second strips.

[0045] In one embodiment of this application, the Schottky diode further includes a third well region 234 and a first doped region 231. The third well region 234 and the first doped region 231 have a first conductivity type. The third well region 234 is located within the first well region 232, and the doping concentration of the third well region 234 is greater than that of the first well region 232. The first doped region 231 is located within the third well region 234, and the doping concentration of the first doped region 231 is greater than that of the third well region 234. A first conductive structure 252 is in direct contact with the first doped region 231; the presence of the first doped region 231 can reduce the contact resistance between the first conductive structure 252 and the third well region 234.

[0046] In one embodiment of this application, the Schottky diode further includes a second doped region 241 located in the second well region 244. The second doped region 241 has a second conductivity type. The doping concentration of the second doped region 241 is greater than the doping concentration of the second well region 244. The second conductive structure 254 is in direct contact with the second doped region 241, and the presence of the second doped region 241 can reduce the contact resistance between the second conductive structure 254 and the second well region 244.

[0047] In one embodiment of this application, the Schottky diode further includes a third doped region 221 located in the cathode region 222. The third doped region 221 has a first conductivity type. The doping concentration of the third doped region 221 is greater than the doping concentration of the cathode region 222. The cathode metal is in direct contact with the third doped region 221, and the presence of the third doped region 221 can reduce the contact resistance between the cathode metal and the third doped region 221.

[0048] In one embodiment of this application, the Schottky diode further includes a fourth doped region 249 located in the fourth well region 248. The fourth doped region 249 has a second conductivity type. The doping concentration of the fourth doped region 249 is greater than the doping concentration of the fourth well region 248. The third conductive structure 256 is in direct contact with the fourth doped region 249, and the presence of the fourth doped region 249 can reduce the contact resistance between the third conductive structure 256 and the fourth well region 248.

[0049] In one embodiment of this application, shallow trench isolation structures (STIs) are also provided between the cathode region 222 and the second well region 244, and between the anode region 226 and the second well region 244. In one embodiment of this application, an STI is also provided between the second well region 244 and the third well region 234. In one embodiment of this application, an STI is also provided between the third well region 234 and the fourth well region 248.

[0050] In one embodiment of this application, the Schottky metal layer includes at least one metal selected from Ti, Pt, Ni, Cr, W, Mo, and Co.

[0051] This application provides a method for manufacturing a Schottky diode, which can be used to manufacture the Schottky diode described in any of the above embodiments. Figure 5 This is a flowchart of a method for manufacturing a Schottky diode according to an embodiment of this application, including the following steps:

[0052] S510, Obtain a wafer in which a buried region of a first conductivity type is formed in a substrate.

[0053] In one embodiment of this application, a pad oxide layer can first be formed on the wafer surface by thermal oxidation. Figure 6a (Not shown in the image), then an implantation window is formed on the front side of the substrate 210 by patterning (e.g., photolithography), and then first conductivity type ions are implanted into the substrate 210 through the implantation window. After removing the photoresist, the implanted first conductivity type ions diffuse to form a first conductivity type buried region 212, as shown in the image. Figure 6a In one embodiment of this application, the first conductivity type is N-type and the second conductivity type is P-type.

[0054] S520, a first well region is formed on the first conductivity type buried region.

[0055] In one embodiment of this application, after removing the pad oxide layer, an epitaxial layer of a first conductivity type is grown on the front side of the substrate 210. Then, an implantation window is formed by patterning, and first conductivity type ions are implanted to form a ring-shaped first well region 232. The first conductivity type buried region 212 is connected to the bottom of the first well region 232 to form a first conductivity type isolation structure. In one embodiment of this application, after removing the pad oxide layer, the step of forming a second conductivity type buried region 242 in the epitaxial layer on the first conductivity type buried region 212 is further included. The second conductivity type buried region 242 is formed in the region surrounded by the first conductivity type buried region 212 and the first well region 232, as shown in the figure. Figure 6b A second conductivity type buried region 242 can be formed by patterning and injecting ions of the second conductivity type.

[0056] S530, a first conductivity type region is formed within the area surrounded by the first conductivity type burial region and the first well region.

[0057] In one embodiment of this application, after step S520, STI is first formed in the wafer. Figure 6c In the illustrated embodiment, a first shallow trench isolation structure 262 is formed.

[0058] After STI formation, a first conductivity type region 220 is formed through patterning and ion implantation (implanting ions of the first conductivity type). (Refer to...) Figure 6c The first conductivity type region 220 includes an anode region 226, a cathode region 222, and a depletion pinch-off region 224 located between the anode region 226 and the cathode region 222.

[0059] In one embodiment of this application, after forming the STI, the method further includes the step of forming a second conductivity type region 246 and a second well region 244 by patterning and ion implantation (implanting ions of a second conductivity type). The second conductivity type region 246 is formed between the anode region 226 and the cathode region 222, and the depletion pinch-off region 224 includes a mesh structure, with the second conductivity type region 246 serving as the mesh of this mesh structure. The second well region 244 has a second conductivity type and is an annular structure located outside the first conductivity type region 220, and between the first conductivity type region 220 and the first well region 232. The implantation windows of the second conductivity type region 246 and the second well region 244 are formed by photolithography using the same photomask.

[0060] In one embodiment of this application, while forming the first conductivity type region 220, a third well region 234 is also formed within the first well region 232. The injection window of the third well region 234 and the first conductivity type region 220 are formed by photolithography using the same photomask.

[0061] In one embodiment of this application, the ion implantation that forms the first conductivity type region 220 and the second conductivity type region 246 is performed using high-energy implantation, which enables the implanted ions to pass through the STI and reach the silicon below the STI.

[0062] S540 forms a Schottky metal layer and a cathode metal.

[0063] In one embodiment of this application, after step S530 and before step S540, the method further includes forming P+ and N+ regions through patterning and ion implantation. Specifically, this includes forming a first doped region 231, a second doped region 241, a third doped region 221, and a fourth doped region 249. The first doped region 231 and the third doped region 221 have a first conductivity type, and the second doped region 241 and the fourth doped region 249 have a second conductivity type. The first doped region 231 is formed in the third well region 234, and the doping concentration of the first doped region 231 is greater than the doping concentration of the third well region 234. The second doped region 241 is formed in the second well region 244, and the doping concentration of the second doped region 241 is greater than the doping concentration of the second well region 244. The third doped region 221 is formed in the cathode region 222, and the doping concentration of the third doped region 221 is greater than the doping concentration of the cathode region 222. The fourth doped region 249 is formed in the fourth well region 248, and the doping concentration of the fourth doped region 249 is greater than that of the fourth well region 248.

[0064] A Schottky metal layer is formed on the anode region 226, forming a Schottky barrier in contact with the upper surface of the anode region 226. The Schottky metal layer serves as the anode of the Schottky diode. A cathode metal layer is formed on the cathode region 222, forming an ohmic contact with the upper surface of the cathode region. The cathode metal serves as the cathode of the Schottky diode.

[0065] S550 forms the first conductive structure.

[0066] In one embodiment of this application, after step S540 and before step S550, a step of forming an interlayer dielectric (ILD) layer is further included. After forming the interlayer dielectric layer, contact holes are formed by photolithography and etching, and then conductive material, such as metal or alloy, is filled into the contact holes. A metal layer is then formed on the contact holes, and the metal layer is patterned to form a first conductive structure 252. The Schottky diode structure after step S550 can be referred to... Figure 2 The first conductive structure 252 is electrically connected to the first well region 232. The first conductive structure 252 is configured to apply a potential to the first well region 232 such that the potential of the first well region 232 and the first conductivity type buried region 212 is higher than the potential of the substrate 210 when the Schottky diode is in forward operation.

[0067] The above-mentioned method for manufacturing a Schottky diode involves forming a first conductivity type isolation structure that surrounds the sides and bottom of the first conductivity type region. In other words, the first conductivity type isolation structure surrounds the periphery and bottom of the Schottky diode. By applying an external potential to the first well region to make it higher than the substrate potential, the turn-on of the parasitic transistor is effectively suppressed, and the substrate leakage current is reduced.

[0068] In one embodiment of this application, a second conductive structure 254 and a third conductive structure 256 are further formed on the metal layer of the patterned interlayer dielectric layer. The second conductive structure 254 is electrically connected to the second well region 244 and is used to apply a potential to the second well region 244. The first conductive structure 252 is configured to apply a potential to the first well region 232 such that the potential of the first conductivity type isolation structure is higher than the potential of the second conductive structure 254 when the Schottky diode is forward-biased. The third conductive structure 256 is electrically connected to the fourth well region 248 and is used to apply a potential to the substrate 210.

[0069] The manufacturing method of the Schottky diode in this application is based on the same inventive concept as the Schottky diode. For details not specifically described in the manufacturing method of the Schottky diode, please refer to the above introduction of the Schottky diode.

[0070] It should be understood that although the steps in the flowchart of this application are shown sequentially as indicated by the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless explicitly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, at least some steps in the flowchart of this application may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times, and the execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least some of the steps or stages of other steps.

[0071] In the description of this specification, references to terms such as "some embodiments," "other embodiments," and "ideal embodiments" indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of the invention. In this specification, the illustrative descriptions of the above terms do not necessarily refer to the same embodiments or examples.

[0072] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0073] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A Schottky diode, characterized in that, include: The first conductivity type region includes an anode region, a cathode region, and a depletion pinch-off region located between the anode region and the cathode region; A Schottky metal layer is located on the anode region and contacts the upper surface of the anode region to form a Schottky barrier. The Schottky metal layer serves as the anode of the Schottky diode. A cathode metal is located on the cathode region and forms an ohmic contact with the upper surface of the cathode region; the cathode metal serves as the cathode of the Schottky diode. The first well region has a first conductivity type and is a ring structure located outside the first conductivity type region; The first conductivity type buried region is located below the first conductivity type region and the first well region, and is connected to the bottom of the first well region; the first well region and the first conductivity type buried region are connected together to form a first conductivity type isolation structure, thereby surrounding the sides and bottom of the first conductivity type region; A substrate having a second conductivity type, at least a portion of which is located below a buried region of the first conductivity type; the first conductivity type and the second conductivity type are opposite conductivity types; A first conductive structure is connected to the first well region; The first conductive structure is configured to apply a potential to the first well region such that the potential of the first conductivity type isolation structure is higher than that of the substrate when the Schottky diode is in forward operation.

2. The Schottky diode according to claim 1, characterized in that, The depletion pinch-off region includes a mesh structure, and the Schottky diode further includes a second conductivity type region located between the anode region and the cathode region, the second conductivity type region serving as the mesh of the mesh structure.

3. The Schottky diode according to claim 1, characterized in that, Also includes: A third well region having a first conductivity type is located in the first well region, and the doping concentration of the third well region is greater than that of the first well region; A first doped region, having a first conductivity type, is located in the third well region, and the doping concentration of the first doped region is greater than the doping concentration of the third well region; the first conductive structure is in direct contact with the first doped region.

4. The Schottky diode according to claim 2, characterized in that, Also includes: The second well region has a second conductivity type. The second well region is a ring structure located outside the first conductivity type region and is located between the first conductivity type region and the first well region. The second conductive type buried area is located below the first conductive type area, the second conductive type area and the second well area, and is connected to the second conductive type area and the second well area. The second conductive type buried area is located between the first conductive type buried area and the first conductive type area. A second conductive structure, connected to the second well region, is used to apply a potential to the second well region; the first conductive structure is configured to apply a potential to the first well region such that the potential of the first conductive type isolation structure is higher than the potential of the second conductive structure when the Schottky diode is in forward operation.

5. The Schottky diode according to claim 2, characterized in that, The doping concentration of the second conductivity type region is greater than the doping concentration of the substrate; and / or The Schottky diode also includes: The fourth well region is located outside the first well region and is connected to the substrate; The third conductive structure is connected to the fourth well region and is used to apply an external potential to the substrate.

6. The Schottky diode according to claim 2, characterized in that, Also includes A first shallow trench isolation structure is located between the cathode region and the anode region, above the mesh structure.

7. The Schottky diode according to claim 6, characterized in that, The depletion pinch-off region includes a plurality of first strips and a plurality of second strips. One end of each first strip is connected to the cathode region and the other end is connected to the mesh structure. One end of each second strip is connected to the anode region and the other end is connected to the mesh structure. A portion of the second conductivity type region is filled between adjacent first strips and a portion of the second conductivity type region is filled between adjacent second strips.

8. A method for manufacturing a Schottky diode, comprising: Obtain a wafer in which a buried region of the first conductivity type is formed in a substrate; The substrate has a second conductivity type; A ring-shaped first well region is formed on the first conductivity type burial region; The first conductivity type buried region is connected to the bottom of the first well region, and the first well region has a first conductivity type; A first conductivity type region is formed within the area enclosed by the first conductivity type burial region and the first trap region; the first conductivity type region includes an anode region, a cathode region, and a depletion pinch-off region located between the anode region and the cathode region; A Schottky metal layer and a cathode metal are formed; the Schottky metal layer is formed on the anode region and contacts the upper surface of the anode region to form a Schottky barrier, and the Schottky metal layer serves as the anode of the Schottky diode; the cathode metal is formed on the cathode region and forms an ohmic contact with the upper surface of the cathode region, and the cathode metal serves as the cathode of the Schottky diode; A first conductive structure is formed, the first conductive structure being connected to the first well region; the first conductive structure is configured to apply a potential to the first well region such that the potential of the first well region and the first conductivity type buried region is higher than the potential of the substrate when the Schottky diode is in forward operation.

9. The method for manufacturing a Schottky diode according to claim 8, characterized in that, The process of forming the first conductivity type region also includes the step of forming a third well region within the first well region; the first conductivity type region and the third well region are formed by ion implantation, and the implantation windows of the first conductivity type region and the third well region are formed by photolithography using the same photomask; the third well region has a first conductivity type, and the doping concentration of the third well region is greater than that of the first well region.

10. The method for manufacturing a Schottky diode according to claim 9, characterized in that, Before the step of forming the first conductivity type region, the method further includes the step of forming a second conductivity type region within the area surrounded by the first conductivity type buried region and the first well region; the first conductivity type region is formed on the second conductivity type buried region. The manufacturing method further includes the step of forming a second conductivity type region and a second well region by ion implantation; the second conductivity type region is formed between the anode region and the cathode region, the depletion pinch-off region includes a mesh structure, and the second conductivity type region serves as the mesh of the mesh structure; the second well region has a second conductivity type, and the second well region is an annular structure located outside the first conductivity type region and located between the first conductivity type region and the first well region; the implantation window of the second conductivity type region and the second well region is formed by photolithography using the same photomask.

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