A method for fabricating a compact package structure with large and small chips.

Abstract

This invention belongs to the field of chip packaging technology, specifically a method for fabricating a compact package structure consisting of two chips, one large and one small. The method involves fabricating circuitry, capacitor pads, mounting positions, and substrate pads on a carrier substrate; forming high copper pillars on the substrate pads; molding the structure to form a molded package; thinning the molded package until the cross-section of the high copper pillars is exposed; electroplating a nickel layer and a solder layer on this cross-section; processing the solder layer to form solder ball bumps; processing the molded package to re-expose the capacitor pads and mounting positions, retaining the molding compound around the high copper pillars; mounting the small chip and surface-mount capacitors on the mounting positions and capacitor pads respectively; forming a mirror structure on the carrier substrate between the remaining molding compound and the small chip; forming a coating on the surface of the mirror structure; mounting the large chip onto the coating; electrically bonding the large chip to the solder ball bumps; and finally, molding to form the final structure. This invention eliminates gold wire interconnects, reduces the overall thickness, and improves signal integrity and heat dissipation performance.

Description

Technical Field

[0001] This invention belongs to the field of chip packaging technology, and in particular, to a method for preparing a compact packaging structure consisting of two chips, one large and one small. Background Technology

[0002] In recent years, the rapid growth in demand for various thin, light, and portable mobile electronic devices has placed new demands on chip packaging. The increasing complexity of device functions drives the integration of more wafers with different functions into chip systems. This requires achieving higher transistor density and more complex three-dimensional heterogeneous integration within a limited unit area (such as solving the problem of co-packaging large and small chips in three-dimensional space). Therefore, chips need to achieve smaller size, shorter signal latency, better heat dissipation, and higher integrated reliability through advanced packaging technologies.

[0003] 3D packaging is a packaging technology leading to high-density integration, aiming to stack multiple IC chips in three dimensions and interconnect them. Chips using 3D packaging are widely used in mobile electronics, high-performance computers, artificial intelligence devices, and other equipment, showing broad market prospects. Currently, the mainstream solutions for 3D chip packaging in the industry include: 3D wire bonding (3D-WB), package-to-package (POP), and integration technology based on through-silicon vias (3D-TSV).

[0004] Among these, 3D wire bonding technology is the most widely used solution due to its maturity and low cost. However, the high arc height of the interconnect wires and potential signal crosstalk limit further miniaturization of the package and improvement of high-frequency performance. POP packaging stacks pre-packaged devices, which increases integration but also increases the overall package thickness, and the signal path between the top and bottom layers is long with significant delay. While 3D-TSV technology can achieve the highest interconnect density and optimal electrical performance, its manufacturing process is complex, technically challenging, and extremely expensive. Therefore, this technology is mainly used in high-end products with extreme performance requirements.

[0005] Against this technological backdrop, the market urgently needs a new type of 3D packaging solution that can be specially designed for heterogeneous chips of different sizes and achieve a better balance between cost, performance, integration and reliability in order to meet the increasingly complex system integration challenges.

[0006] The existing two-chip packaging technology has the following technical problems:

[0007] 1. If two chips of different sizes are mounted using SMT, the footprint will be too large.

[0008] 2. Traditional wire bonding is limited by the lead arc height and bonding point area, resulting in limited I / O density, typically large package size, indistinct heat conduction path, poor heat dissipation performance, long signal transmission path, slow signal transmission speed, and high loss, making it unsuitable for high-frequency and high-speed applications.

[0009] 3. Existing two-chip packaging technology is not simple and symmetrical in structure, has uneven stress distribution, and poor mechanical stability.

[0010] More specifically, for large and small chip packaging structures, the existing solution is to use 3D wire bonding technology and a packaging substrate to stack multiple chips into a single package to increase storage capacity or achieve functional integration.

[0011] In this scheme, chips (such as D1 and D2) are respectively mounted on the substrate and the lower chip via chip bonding film (DAF). The interconnection between the chips is completed through gold wires (or copper wires) and the packaging substrate, and the arc height of the gold wires on the top chip is generally greater than 60μm.

[0012] The disadvantages of this approach include:

[0013] 1. In traditional wire bonding-based upright chip packaging structures, the interconnection between chips relies entirely on gold wire arcs. To ensure bonding reliability and prevent short circuits caused by wire arc collapse, the wire arc height of the topmost chip must be maintained at at least 60μm. This directly increases the vertical space requirement for chip stacking, making it difficult to reduce the overall package thickness and failing to meet the stringent requirements of modern mobile devices for ultra-thin packaging.

[0014] 2. In the above wire bonding scheme, the transmission path of electrical signals is "chip-gold wire-substrate-gold wire-chip". The gold wire in this path is relatively long, which will introduce significant parasitic inductance and resistance, resulting in increased signal transmission delay, increased power consumption, and deterioration of signal integrity. At the same time, the long gold wire is not conducive to the rapid discharge of chip power, resulting in poor overall heat dissipation performance, which seriously affects the speed and reliability of high-performance chip products.

[0015] 3. In terms of thermal stress and mechanical reliability, the wire bonding structure has significant shortcomings. The slender leads and their solder joints are weak points in the mechanical connection, and are prone to fatigue fracture due to stress concentration under temperature cycling or external mechanical stress (such as vibration and bending). At the same time, the chip is only bonded to the substrate by DAF, and its overall structural rigidity is insufficient. When the coefficients of thermal expansion are mismatched, warping or interface delamination can easily occur, affecting the reliability of long-term use. Summary of the Invention

[0016] To overcome the shortcomings of the prior art, the present invention provides a method for fabricating a compact packaging structure consisting of two chips, one large and one small.

[0017] The technical solution of the present invention includes the following:

[0018] A method for fabricating a compact package structure consisting of two chips, one large and one small, includes the following steps:

[0019] The required circuits, capacitor pads, mounting positions, and substrate pads are fabricated on the surface of the carrier board using photolithography and electroplating processes.

[0020] High copper pillars are formed on the substrate pads. Molding material is used to encapsulate the carrier board and all structures on the carrier board. A molding compound is formed on the carrier board. The top of the molding compound is ground and thinned until the cross-section of the high copper pillar is exposed, forming a flat surface. Electroplating is performed on the exposed cross-section of the high copper pillar to form a nickel layer and a solder layer.

[0021] The solder layer is reflow soldered, and the solder layer melts to form smooth solder ball bumps;

[0022] Selective ablation of the molding compound exposes the capacitor pads and mounting positions again, while preserving the molding compound around the high copper pillars;

[0023] Chips and surface mount capacitors are mounted on the exposed mounting positions and capacitor pads respectively. A mirror structure is formed on the carrier between the remaining molding compound and the chips. A coating is formed on the surface of the mirror structure.

[0024] The large chip is mounted onto the coating, and the reflow soldering process is used to electrically bond the large chip to the solder ball bumps at the top of the high copper pillars.

[0025] The entire packaging structure is fully encapsulated to form a compact packaging structure.

[0026] It should be noted that by adopting the above technical solution, this invention creatively combines a series of process steps such as high copper pillar preparation, local molding, laser grooving, mirror structure mounting and PI coating, and chip flip bonding to form a unique packaging process, which is also an integrated process method.

[0027] The present invention ultimately forms a heterogeneous integrated package with two chips on the top and bottom, which is a brand-new package entity. Its bottom layer is a base island containing surface-mount components and high copper pillars, the middle layer is a mirror plane that provides support and interconnection, and the top layer is a flip chip. The three are electrically interconnected and mechanically supported through this innovative structure and high copper pillars.

[0028] Furthermore, forming high copper pillars on the substrate pads includes the following steps:

[0029] After tinning or fluxing is applied to the substrate pads, the pre-formed copper pillars are mounted onto the substrate pads using high-precision mounting equipment. After mounting, the soldering material at the bottom of the pre-formed copper pillars is firmly connected to the substrate pads through a reflow soldering process, forming high copper pillars.

[0030] It should be noted that, by adopting the above technical solution, the present invention provides a packaging architecture jointly supported by high copper pillars and a mirror structure. It proposes a composite packaging structure in which high copper pillars formed by mounting and an independent mirror structure jointly provide mechanical support and electrical connection for the upper-layer chip. This structure effectively solves the support and interconnection reliability problems in multilayer heterogeneous integration.

[0031] Furthermore, forming high copper pillars on the substrate pads includes the following steps:

[0032] The pre-formed copper pillars are processed and connected to the substrate pads. The pre-formed copper pillars are formed by any one or more combinations of processing methods such as pre-formed copper pillar mounting, precision mold casting, precision stamping, precision etching, and laser precision processing.

[0033] Furthermore, the thermal conductivity of the high-copper pillar is ≥400W / mK, and the height of the high-copper pillar is 50-1000μm.

[0034] Furthermore, selective ablation of the encapsulated body is performed using high-precision laser equipment;

[0035] Mounting a large chip onto a coating includes the following steps: mounting a large chip with pre-prepared solder bumps onto the coating in a flip-chip manner;

[0036] Forming a coating on the surface of a mirror structure includes the steps of: applying a layer of PI to the surface of the mirror structure to form a coating.

[0037] Furthermore, high copper pillars include integrated copper pillars, which include dumb pillars for mechanical support and functional copper pillars for signaling, with the dumb pillars being taller than the functional copper pillars.

[0038] Furthermore, the material of the mirror structure includes one or more of silicon, glass, ceramic, metal or organic polymer materials.

[0039] Furthermore, the process of forming a mirror structure on the carrier between the remaining molding compound and the chiplet includes:

[0040] The mirror structure and the carrier plate can be bonded using adhesive film, or the mirror structure can be soldered onto the carrier plate, or the mirror structure can be eutectic bonded to the carrier plate, or a mirror structure with bumps can be selected and flip-chip connected to the pads on the carrier plate through the bumps on the mirror structure.

[0041] It should be noted that, by adopting the above technical solution, this invention provides a mirror structure with DAF (a type of adhesive film) and its surface PI coating layer. It innovatively introduces a mirror structure with DAF and coats and cures a PI layer on its surface. This PI layer provides a planarized, insulating, and highly adhesive bonding interface for the flip chip above it, and is an important component for achieving high-reliability interconnects.

[0042] Furthermore, the process of forming a mirror structure on the carrier between the remaining molding compound and the chiplet includes:

[0043] Under constant temperature stirring conditions of 80-100℃, choline chloride and glycerol were stirred and mixed, and then cooled to obtain a solvent; PDMS main agent and coupling agent were taken, stirred, sealed, and allowed to stand at room temperature, then PDMS curing agent was added and stirred, then nano-SiO2 was added and stirred, and the solvent was slowly added at 40-50℃ while maintaining the temperature and stirring, and vacuum degassing was performed to obtain the bottom layer solution.

[0044] Deionized water and ethanol were mixed, polyacrylic acid was added, and the mixture was stirred. Zinc chloride was added, and stirring was continued. A coupling agent was added, and the mixture was allowed to stand to react, resulting in an intermediate layer solution.

[0045] Deionized water and ethanol were mixed, silane was added and stirred, hydrochloric acid was added and stirred, octavinyl-POSS was added and stirred, nanosheets were added and ultrasonically stirred to obtain the top layer solution;

[0046] First, a base layer solution is coated onto the substrate to form the base layer. Then, an intermediate layer solution is coated onto the base layer to form the intermediate layer. Finally, a top layer solution is coated onto the intermediate layer to form the top layer. The base layer, intermediate layer, and top layer together constitute a mirror structure.

[0047] Preferably, the silane includes triethoxysilane, the nanosheets include hexagonal boron nitride nanosheets, and the coupling agent includes APTES.

[0048] This invention provides a method for fabricating a compact package structure consisting of two chips, one large and one small. Compared with the prior art, the advantages of this invention are as follows:

[0049] This invention discloses a dual flip-chip multi-chip integrated package structure based on high copper pillars and a mirror-coated interposer, along with its fabrication process. This structure utilizes high copper pillars for vertical interconnection and innovatively introduces a mirror-coated interposer to provide mechanical elevation and support for the upper-layer large chip, enabling both the large and small chips to be connected to the substrate via flip-chip bonding. Compared to traditional wire bonding stacked packages, this structure completely eliminates gold wire interconnection, not only reducing the overall package thickness but also effectively improving signal integrity and heat dissipation performance through the short interconnect paths of the high copper pillars. Simultaneously, this solution avoids the complexity and high cost of TSV (Through-Switch) technology, achieving high-density integration while maintaining manufacturing cost advantages.

[0050] It should be noted that the gold wire arc height is typically controlled between 50-150 μm, and a safe distance (generally ≥30 μm) must be maintained between the tip of the arc and the chip surface or the bottom of the metal cover to avoid mechanical stress damage. Therefore, the arc height directly increases the overall height from the packaging substrate to the top cover by approximately 80-180 μm. Thus, this invention eliminates the need for gold wire interconnects, reducing the overall package thickness.

[0051] Specifically, for large and small chip package structures, this invention aims to solve the problems of wire bonding technology in terms of package thickness, electrical performance, mechanical and thermal reliability. The high copper pillar structure provides robust vertical interconnection and support for the chips, greatly enhancing the mechanical stability and heat dissipation of the package. At the same time, the application of flip-chip technology completely eliminates lead arcing, shortens the interconnection distance, reduces package thickness and improves electrical performance. It also allows chips at higher stacks to no longer rely on DAF bonding, but instead use polyimide (PI) with better mechanical properties to protect their flip-chip circuit layers and provide mechanical support, thus comprehensively solving the prominent contradictions faced by existing technologies.

[0052] More specifically,

[0053] 1. Traditional wire bonding requires reserving 150-200μm of space around the chip for wire bonding, resulting in a significant waste of package area. This invention employs high copper pillars (50-1000μm in height) for vertical interconnection and flip-chip technology to achieve Z-axis stacking, thereby increasing the chip integration density per unit area and ultimately forming a compact package with a size much smaller than that of traditional methods.

[0054] 2. The parasitic inductance generated by wire bonding interconnects is typically 1-2 nH, becoming a bottleneck for high-frequency performance. This invention provides extremely short vertical interconnect paths through high copper pillars and flip-chip microbumps, reducing parasitic inductance to the pH level, increasing signal transmission rate to over 10 Gbps, and improving signal integrity.

[0055] 3. Traditional upright chip thermal resistance is typically 20-40℃ / W. This solution utilizes high copper pillars (thermal conductivity ≥400W / mK) to construct vertical heat dissipation channels, combined with a flip-chip structure, to reduce overall thermal resistance and chip junction temperature, thereby improving product lifespan and reliability.

[0056] 4. Mechanical support is provided by local molding compound around the high copper pillars to prevent tilting; at the same time, the PI layer (thickness 5-15μm) on the mirror structure is used as a stress buffer interface to improve the thermomechanical reliability of the package structure and enhance the robustness of the package.

[0057] 5. The present invention ultimately forms a heterogeneous integrated package with two chips on the top and bottom, which is a brand-new package entity. Its bottom layer is a base island containing surface-mount components and high copper pillars, the middle layer is a mirror plane that provides support and interconnection, and the top layer is a flip chip. The three are electrically interconnected and mechanically supported through this innovative structure and high copper pillars. Attached Figure Description

[0058] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0059] Figure 1 This is a schematic diagram of the structure of step S1 of the present invention;

[0060] Figure 2 This is a schematic diagram of the structure of step S2 of the present invention;

[0061] Figure 3 This is a schematic diagram of the structure of step S3 of the present invention;

[0062] Figure 4 This is a schematic diagram of the structure of step S4 of the present invention;

[0063] Figure 5 This is a schematic diagram of the structure of step S5 of the present invention;

[0064] Figure 6 This is a schematic diagram of the structure of step S6 of the present invention;

[0065] Figure 7 This is a structural schematic diagram of step S7 of the present invention;

[0066] Figure 8 This is a schematic diagram of the structure of step S8 of the present invention;

[0067] Figure 9 This is a schematic diagram of the structure of step S9 of the present invention;

[0068] Figure 10 This is a schematic diagram of the integrated copper pillar structure of the present invention. Figure 10 For ease of illustration, not all other parts are shown.

[0069] The markings in the diagram are as follows: 1. Carrier board; 2. Capacitor pad; 3. Mounting position; 4. Substrate pad; 5. Pre-formed copper pillar; 6. High copper pillar; 7. Molded body; 8. Nickel layer; 9. Solder layer; 10. Solder ball bump; 11. Die A; 12. Surface mount capacitor; 13. Adhesive film; 14. Mirror structure; 15. Coating; 16. Die B; 17. Molding material; 18. Dumb pillar; 19. Functional copper pillar. Detailed Implementation

[0070] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described below in conjunction with specific embodiments. Unless otherwise specified, the methods described are conventional methods, and the raw materials described are all available from publicly available commercial sources.

[0071] Any embodiment described herein as “exemplary” is not necessarily superior to other embodiments. Although various aspects of the embodiments are shown in the accompanying drawings, the drawings are not necessarily drawn to scale unless specifically indicated otherwise.

[0072] Example 1

[0073] A compact package structure consisting of two chips, one large and one small, is fabricated using the following steps:

[0074] For ease of description, the small chip is named DieA 11 and the large chip is named DieB 16.

[0075] S1. Reference Figure 1 Prepare a carrier board 1 for packaging. On the surface of the carrier board 1, the required circuits, capacitor pads 2 for soldering chip capacitors, mounting positions 3 for mounting DieA 11, and substrate pads 4 for mounting to form high copper pillars 6 are made by photolithography and electroplating processes.

[0076] Specifically, a thin, uniform copper layer, 0.3-1.0 μm thick, is deposited on the entire surface of the substrate 1 using chemical plating. A layer of photoresist sensitive to specific ultraviolet light is spin-coated onto the copper layer and then cured by baking. Exposure: A photomask is used and aligned with the substrate. The photomask has transparent and opaque areas for circuits and pads. When irradiated with ultraviolet light, the light passes through the transparent areas of the photomask, causing a chemical reaction in the photoresist in these areas. Development: The substrate is rinsed with a developer. The photoresist (positive photoresist) in the ultraviolet-exposed areas is dissolved, exposing the copper layer that needs to be thickened by electroplating underneath, while the photoresist in the unexposed areas remains, acting as a barrier to electroplating. Selective electroplating is then performed on the copper layer exposed after development. By electroplating copper, circuits for transmitting electrical signals, capacitor pads 2, mounting positions 3, and substrate pads 4 are electroplated in different specific areas.

[0077] S2, Reference Figure 2 After soldering or fluxing is applied to the substrate pads 4, the pre-formed copper pillars 5 are mounted onto the substrate pads 4 using high-precision mounting equipment, forming high-copper pillars 6. The thermal conductivity of the high-copper pillars 6 is ≥400W / mK.

[0078] The core of this process lies in using specialized tools to precisely position and fix the pre-formed copper pillars 5, ensuring a good electrical and mechanical connection between the pre-formed copper pillars 5 and the substrate pads 4. After mounting, a reflow soldering process is used to firmly connect the solder material at the bottom of the pre-formed copper pillars 5 to the substrate pads 4, thereby constructing a vertical interconnect structure with a height range of 50-1000μm.

[0079] S3. Reference Figure 3 A molding compound is used to mold and encapsulate the entire carrier board 1 structure, forming a molding compound 7 on the carrier board 1. The molding compound completely encapsulates the carrier board 1, capacitor pads 2, mounting positions 3, and high copper pillars 6, forming a single unit that provides mechanical protection and secures all components. The height of the molding compound 7 must completely cover the high copper pillars 6.

[0080] S4, Reference Figure 4 The top of the molding compound 7 is ground and thinned until the cross-section of the high copper pillar 6 is exposed, forming a flat surface. Subsequently, electroplating is performed on the exposed cross-section of the high copper pillar 6 to form a nickel layer 8 and a solder layer 9 as a barrier layer, with the nickel layer 8 at the bottom and the solder layer 9 at the top, in preparation for subsequent reflow soldering to form solder balls.

[0081] S5. Reference Figure 5 The structure after S4 electroplating is then reflow soldered. At high temperature, the solder layer 9 at the top of the high copper pillar 6 melts and forms smooth solder ball bumps 10 due to surface tension. After completion, it is cleaned to remove flux residue.

[0082] S6, Reference Figure 6 High-precision laser equipment is used to selectively ablate the molded body 7. This step aims to remove the molding compound around the high copper pillar 6, exposing them (capacitor pads 2, mounting positions 3) again, while retaining the molding compound around the high copper pillar 6 to continue providing mechanical support for it and prevent it from tipping over. The amount, thickness, and height of the retained molding compound around the high copper pillar 6 need not be excessive; it only needs to ensure that the substrate pads 4 or the base of the high copper pillar 6 are not exposed.

[0083] S7, Reference Figure 7 After laser grooving, the corresponding components are mounted above the exposed mounting positions 3 and capacitor pads 2, and a mirror structure 14 with an adhesive film 13 is mounted on the carrier board 1. The adhesive film can be DAF adhesive film.

[0084] Specifically, Die A 11 is flip-chip mounted on mounting position 3, surface mount capacitor 12 is mounted on capacitor pad 2, and a mirror structure 14 with adhesive film 13 is mounted on the carrier board 1 between the remaining molding compound and Die A 11. This structure, from bottom to top, consists of carrier board 1, adhesive film 13, and mirror structure 14. This achieves the electrical connection between Die A 11 and surface mount capacitor 12 and carrier board 1.

[0085] Regarding the mirror structure 14, it is essentially an interposer or spacer layer. Its core function is not for optical reflection (like a mirror), but to provide a height difference and a robust, flat mounting surface between the large chip (DieB 16) and the small chip (DieA 11). "Mirror" here describes its smooth, mirror-like physical properties to ensure that the large chip can be stably and reliably mounted on it.

[0086] Subsequently, a layer of PI (polyimide) is uniformly coated on the surface of the mirror structure 14 to form a coating 15 with a thickness of 5-15 μm. After curing, the coating 15 forms a flat surface with good thermomechanical properties.

[0087] S8. Reference Figure 8 Another chip, DieB 16, with pre-prepared solder bumps, is precisely flip-chip mounted onto the coating 15. Through a reflow soldering process, DieB 16 is electrically bonded to the solder ball bumps 10 at the top of the high-copper pillar 6 via circuit connections.

[0088] S9, Reference Figure 9 The entire package structure is then subjected to a final, comprehensive molding process. The high-copper pillar 6, DieB 16, mirror structure 14, and all components on the underlying carrier board 1 are completely encapsulated using molding material 17, forming a highly integrated and fully protected single package.

[0089] After completing the above steps, a completely new packaging structure is formed.

[0090] Example 2

[0091] To further explain Example 1, the copper pillar 5 in Example 1 is formed by mounting. The copper pillar structure is not necessarily limited to the prefabricated copper pillar mounting structure in Example 1. It can be formed by any one or more combinations of processing methods such as prefabricated copper pillar mounting, precision mold casting, precision stamping, precision etching, and laser precision machining. That is, the copper pillar 5 is not limited to mounting; any metal columnar interconnect structure that can form the required height and shape falls within the protection scope of this solution.

[0092] Example 3

[0093] To further illustrate Example 1, the types of DieA 11 and DieB 16 chips are not limited to a single chip type and chip size. Any package structure that uses copper pillars to achieve vertical interconnection and combines an intermediate support structure (such as mirror structure 14) to provide a padding and interconnection platform for the upper-layer chip, thereby enabling flip-chip connection of both the upper and lower layers, falls within the protection scope of this invention.

[0094] Example 4

[0095] To further illustrate Example 1, the functions of the high-copper pillar 6 can be subdivided and integrated.

[0096] The high copper pillar 6 can be an integrated copper pillar, which includes a dummy pillar 18 for mechanical support and a functional copper pillar 19 for signaling. The height of the dummy pillar 18 can be slightly higher than that of the functional copper pillar 19 to provide physical support before the reflow soldering of S8 and prevent DieB 16 from tilting.

[0097] This invention provides a practical, specific, and referable solution. Figure 10 The height of the dumb pillar 18 is 10-15 μm higher than that of the functional copper pillar 19. The dumb pillar 18 can be directly mechanically bonded to the substrate pad 4 without the need for the S8 reflow soldering process. The functional copper pillar 19 needs to be electrically bonded to the DieB 16.

[0098] It should be noted that, Figure 10 For ease of illustration, not all other parts are shown.

[0099] Example 5

[0100] Further explanation of Example 1,

[0101] Regarding the mirror structure 14 with adhesive film 13 in Example 1, the mirror structure 14 is not limited to a flat plate made of a single material, but can be made of one or more of silicon, glass, ceramic, metal or organic polymer materials. Regarding adhesive film 13, it is not limited to using DAF adhesive to bond the mirror structure 14 and the carrier plate 1, but can also be fixed and electrically connected by welding, eutectic bonding, or flip-chip connection through the bumps on the mirror structure 14 and the pads on the carrier plate 1.

[0102] The specific fabrication process of mirror structure 14 is given below, and a small-scale experiment is conducted.

[0103] Example 6

[0104] Prepare the bottom layer solution by weight, as follows:

[0105] raw material:

[0106] Choline chloride: ≥99%;

[0107] Glycerin: ≥99.5%;

[0108] PDMS: Two-component, consisting of a main agent and a curing agent, Sylgard 184 is an option;

[0109] Nano SiO2: Evonik, AEROSIL® 200 is an option;

[0110] Silane coupling agent: APTES;

[0111] Preparation using raw materials: Under constant temperature stirring conditions of 80-100℃, add 1 mol of choline chloride and 2 mol of glycerol to a three-necked flask, keep stirring for 15-25 min to mix thoroughly, and then cool to 40℃ to obtain the solvent.

[0112] Take 100 parts of PDMS main agent and 0.5 parts of silane coupling agent, stir, seal, and let stand at room temperature for 30 min. Then add 9 parts of PDMS curing agent, stir, then add 2 parts of nano SiO2, and stir at high speed shearing 2000-3000 rpm for 3-5 min. Slowly add 10 parts of solvent at 40-50℃, maintain the temperature and stir for 5-8 min, and then degas under vacuum of -0.095MPa for 4 min to obtain the bottom layer solution.

[0113] Example 7

[0114] The intermediate layer solution is prepared by weight, and the specific steps are as follows:

[0115] raw material:

[0116] Polyacrylic acid (PAA), molecular weight 5000, 50% aqueous solution;

[0117] Zinc chloride: ZnCl2, ≥98%;

[0118] Silane coupling agent: APTES;

[0119] Ethanol: Anhydrous ethanol, ≥99.7%;

[0120] Preparation using raw materials:

[0121] Mix 63 parts of deionized water and 25 parts of ethanol, add 10 parts of polyacrylic acid, stir, then add 0.8 parts of zinc chloride, continue stirring, then add 2 parts of silane coupling agent, let stand for 20 minutes to obtain the intermediate layer solution.

[0122] Example 8

[0123] The top layer solution is prepared by weight, and the specific steps are as follows:

[0124] raw material:

[0125] Silane: Triethoxysilane;

[0126] Hydrochloric acid: 0.01M standard aqueous solution;

[0127] Octadecyl-POSS: Purity >98%;

[0128] Nanosheets: Hexagonal boron nitride nanosheets, with a sheet diameter <200 nm and a diameter <200 nm;

[0129] Ethanol: Anhydrous ethanol, ≥99.7%;

[0130] Preparation using raw materials:

[0131] Mix 4 parts deionized water and 52 parts ethanol, add 20 parts silane, stir, then add 1 part hydrochloric acid, stir for 15 min, add 20 parts octavinyl-POSS, stir for 45 min, add 3 parts nanosheets, and sonicate for 20 min to obtain the top layer solution.

[0132] Example 9

[0133] Take a 0.5 mm thick carrier plate 1, which is made of BT resin. Apply the bottom solution of Example 6 onto the carrier plate 1.

[0134] Then, pre-cur at 80°C for 12 minutes and fully cure at 120°C for 40 minutes to form the bottom layer on the carrier plate 1.

[0135] Then the intermediate solution from Example 7 was scraped onto the bottom layer.

[0136] Then dry at 70°C for 1 hour to form an intermediate layer on the bottom layer.

[0137] Then the top layer solution from Example 8 was scraped onto the intermediate layer.

[0138] Then, it is initially dried at 60°C for 1 hour, followed by hot pressing at 120°C for 30 minutes; finally, the surface is mechanically polished by CMP to make the roughness Ra < 5nm, forming the top layer on the intermediate layer.

[0139] Thus, the bottom layer, the middle layer, and the top layer together form a mirror structure 14 without adhesive film 13 on the carrier 1.

[0140] After curing, the overall thickness of the mirror structure 14 is 54 μm. The thickness ratio of the bottom layer: middle layer: top layer is 12:1:5.

[0141] It should be noted that the mirror structure 14 in Example 9 has a three-layer structure: the bottom layer is an elastic buffer layer, the middle layer is an ion-crosslinked intermediary layer, and the top layer is a rigid layer. The top layer provides a rigid platform with high flatness, high thermal conductivity, and low thermal expansion; the middle layer, as a synergistic intermediary layer, has reversible crosslinking to adjust stress distribution; the bottom layer provides viscoelastic buffering and interface charge redistribution to absorb shocks; and there are physicochemical interface interactions (Si-O-Si bonds, ion bridges, hydrogen bond networks) between the three layers.

[0142] Example 10

[0143] Similar to Example 9, a carrier plate 1 with a thickness of 0.5 mm was used, and the carrier plate 1 was made of BT resin.

[0144] Prepare DAF film; Hitachi Nitto DAF is a good choice.

[0145] Prepare mirror structure 14, which can be made from silicon wafers.

[0146] Attach one side of the DAF adhesive film to the back of the mirror structure 14 and gently press to remove air bubbles; pre-bond and cure at 90°C for 4 minutes, then align the other side of the DAF adhesive film with the carrier plate 1, and hot-press and cure at 170°C for 70 minutes under a pressure of 0.8MPa. After cooling to room temperature, remove the film to complete the bonding.

[0147] Thus, the DAF film and the mirror structure 14 together form a mirror structure 14 with the film 13 on the carrier 1. After curing, the overall thickness of the mirror structure 14 is 54 μm. The thickness ratio of the DAF film to the mirror structure 14 is 5:13.

[0148] It should be noted that the overall thickness of the mirror structure 14 in Embodiment 9 and Embodiment 10 is the same in order to facilitate subsequent testing and comparison. In application, the thickness can be adjusted according to actual needs.

[0149] The mirror structure 14 of Examples 9 and 10 was tested.

[0150] Evaluation of the load-bearing capacity of different mirror structures 14:

[0151] Under two conditions, at room temperature of 25℃ and high temperature of 125℃, a universal material testing machine was used to apply a vertical indenter to the center of the mirror structure 14 and gradually load it.

[0152] Record: 1. Yield point, i.e., the pressure at which the initial permanent deformation occurs, in MPa;

[0153] 2. Maximum compressive strength, i.e., the load at which deformation is reduced to 5%;

[0154] The results are shown in Table 1 below:

[0155] Table 1

[0156]

[0157] Further observation of the mirror structure 14 after the experiment at 125°C yielded the following results:

[0158] Slight surface depressions were observed in the mirror structure 14 of Example 9, but no through cracks were found.

[0159] It was observed that the mirror structure 14 of Example 10 exhibited DAF interface microcracks that propagated to the edge of the silicon wafer, resulting in localized rupture.

[0160] analyze:

[0161] Regarding the yield point, Example 10 is generally higher than that of Example 9;

[0162] Regarding the maximum compressive strength, Example 10 is stronger at room temperature, but the decrease at 125°C is greater than that of Example 9, indicating poor thermal adaptability.

[0163] Regarding the structure after the experiment, Example 9 maintained its structural integrity at high temperatures without any signs of cracking, demonstrating the synergistic buffering effect of the bottom and middle layers.

[0164] Example 9 constructed a three-layer mirror structure 14. The bottom layer is a composite elastic layer of PDMS and nano-SiO2, providing compressibility and micro-deformation absorption capabilities to buffer mechanical loading and thermal expansion and contraction stress during the encapsulation process. The middle layer is a PAA and zinc ion crosslinked polymer layer, which has stress-harmonizing effects, plasticity, and reversible crosslinking capabilities, and can dynamically adjust the interfacial stress field. The top layer is a composite rigid layer of POSS and hexagonal boron nitride nanosheets, which provides high modulus, high flatness, and high support, ensuring the structural stability of the chip flip-chip mounting. The three layers are connected by chemical bonds (such as Si-O-Si bonds), hydrogen bond networks, and metal ion bridges to form a stable layered composite system that takes into account the encapsulation requirements of soft and hard adjustment, stress absorption, and interfacial stability.

[0165] In summary, the specific embodiments and comparative examples described above are merely for clearly illustrating the present invention and should not be construed as limiting the present invention. Those skilled in the art should understand that various equivalent substitutions, modifications, changes, or improvements can be made to the technical solutions and implementation methods of the present invention without departing from the spirit and scope of the invention, and all such changes or improvements fall within the scope of the present invention. The scope of protection of the present invention is defined by the appended claims.

Claims

1. A method for fabricating a compact package structure consisting of two chips, one large and one small, characterized in that, Includes the following steps: The required circuits, capacitor pads, mounting positions, and substrate pads are fabricated on the surface of the carrier board using photolithography and electroplating processes. High copper pillars are formed on the substrate pads. Molding material is used to encapsulate the carrier board and all structures on the carrier board. A molding compound is formed on the carrier board. The top of the molding compound is ground and thinned until the cross-section of the high copper pillar is exposed, forming a flat surface. Electroplating is performed on the exposed cross-section of the high copper pillar to form a nickel layer and a solder layer. The solder layer is reflow soldered, and the solder layer melts to form smooth solder ball bumps; Selective ablation of the molding compound exposes the capacitor pads and mounting positions again, while preserving the molding compound around the high copper pillars; Chips and surface mount capacitors are mounted on the exposed mounting positions and capacitor pads respectively. A mirror structure is formed on the carrier between the remaining molding compound and the chips. A coating is formed on the surface of the mirror structure. The large chip is mounted onto the coating, and the reflow soldering process is used to electrically bond the large chip to the solder ball bumps at the top of the high copper pillars. The entire packaging structure is fully encapsulated to form a compact packaging structure.

2. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, Forming high copper pillars on substrate pads includes the following steps: After tinning or fluxing is applied to the substrate pads, the pre-formed copper pillars are mounted onto the substrate pads using high-precision mounting equipment. After mounting, the soldering material at the bottom of the pre-formed copper pillars is firmly connected to the substrate pads through a reflow soldering process, forming high copper pillars.

3. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, Forming high copper pillars on substrate pads includes the following steps: The pre-formed copper pillars are processed and connected to the substrate pads. The pre-formed copper pillars are formed by any one or more combinations of processing methods such as pre-formed copper pillar mounting, precision mold casting, precision stamping, precision etching, and laser precision processing.

4. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, The thermal conductivity of the high-copper column is ≥400W / mK, and the height of the high-copper column is 50-1000μm.

5. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, characterized in that, Selective ablation of the encapsulated material is performed using high-precision laser equipment; Mounting a large chip onto a coating includes the following steps: mounting a large chip with pre-prepared solder bumps onto the coating in a flip-chip manner; Forming a coating on the surface of a mirror structure includes the steps of: applying a layer of PI to the surface of the mirror structure to form a coating.

6. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, High copper pillars include integrated copper pillars, which include dumb pillars for mechanical support and functional copper pillars for signaling. The height of the dumb pillars is higher than that of the functional copper pillars.

7. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, The materials used for mirror structures include one or more of silicon, glass, ceramics, metals, or organic polymers.

8. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, The process of forming a mirror structure on a carrier between the remaining molding compound and the chiplet includes: The mirror structure and the carrier plate can be bonded using adhesive film, or the mirror structure can be soldered onto the carrier plate, or the mirror structure can be eutectic bonded to the carrier plate, or a mirror structure with bumps can be selected and flip-chip connected to the pads on the carrier plate through the bumps on the mirror structure.

9. The method for fabricating a compact package structure with two chips, large and small, according to claim 1, is characterized in that, The process of forming a mirror structure on a carrier between the remaining molding compound and the chiplet includes: Under constant temperature stirring conditions of 80-100℃, choline chloride and glycerol were stirred and mixed, and then cooled to obtain a solvent; PDMS main agent and coupling agent were taken, stirred, sealed, and allowed to stand at room temperature, then PDMS curing agent was added and stirred, then nano-SiO2 was added and stirred, and the solvent was slowly added at 40-50℃ while maintaining the temperature and stirring, and vacuum degassing was performed to obtain the bottom layer solution. Deionized water and ethanol were mixed, polyacrylic acid was added, and the mixture was stirred. Zinc chloride was added, and stirring was continued. A coupling agent was added, and the mixture was allowed to stand to react, resulting in an intermediate layer solution. Deionized water and ethanol were mixed, silane was added and stirred, hydrochloric acid was added and stirred, octavinyl-POSS was added and stirred, nanosheets were added and ultrasonically stirred to obtain the top layer solution; First, a base layer solution is coated onto the substrate to form the base layer. Then, an intermediate layer solution is coated onto the base layer to form the intermediate layer. Finally, a top layer solution is coated onto the intermediate layer to form the top layer. The base layer, intermediate layer, and top layer together constitute a mirror structure.

10. The method for fabricating a compact package structure with two chips, large and small, according to claim 9, is characterized in that, Silanes include triethoxysilanes, nanosheets include hexagonal boron nitride nanosheets, and coupling agents include APTES.

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