An intelligent water-saving irrigation control terminal and method based on artificial intelligence edge computing multi-source data fusion

Abstract

The application discloses a kind of based on artificial intelligence edge computing multi-source data fusion intelligent water-saving irrigation control terminal and method, it is related to intelligent control technical field, comprising the following steps: S1, in the power input end of irrigation control system configuration voltage buffer chain, utilize capacitor energy storage and filter voltage stabilizing technology to carry out edge capture and fluctuation suppression to input voltage, output stable continuous electric energy;S2, utilize the stable electric energy of power output to maintain the constant of processor operating tempo in edge computing node, and freeze signal output tempo on the basis of constant tempo, simultaneously establish the control gate of synchronization with power output tempo.The application starts from power, tempo, signal, pump body, water pressure five aspects, constructs multilevel collaborative control mechanism, effectively avoids false triggering and frequent start-stop, reduces impact and interference, improves irrigation equipment stability and life, realizes water-saving, efficient, accurate control goal.

Description

Technical Field

[0001] This invention relates to the field of intelligent control technology, specifically to an intelligent water-saving irrigation control terminal and method based on artificial intelligence edge computing and multi-source data fusion. Background Technology

[0002] Intelligent water-saving irrigation control based on AI edge computing and multi-source data fusion refers to a smart agricultural irrigation system that, through the deployment of a data acquisition and control system, relies on AI algorithms and edge computing architecture to fuse and analyze multi-source heterogeneous data (such as soil moisture, meteorological elements, water level, flow rate, images, and videos) locally in the field in real time. This generates targeted irrigation decisions and executes them immediately, achieving precise, water-saving, and efficient irrigation control. The data acquisition and control system utilizes on-site computing and intelligent algorithms at edge nodes to identify and predict collected environmental parameters, avoiding the latency and energy consumption caused by uploading all data to the cloud. By integrating multi-dimensional information such as soil moisture, light intensity, wind speed and direction, and crop growth, it dynamically determines the optimal irrigation time and water volume threshold. This is then linked with the pump station and solenoid valve execution unit to automatically start / stop and adjust water supply. This model achieves closed-loop intelligent control of monitoring, analysis, decision-making, and execution, not only saving water resources and significant labor costs but also ensuring a more balanced water supply for crops, improving yield and quality.

[0003] The existing technology has the following shortcomings:

[0004] In existing technologies, when field edge computing nodes operate under extreme temperature and humidity conditions, they are prone to momentary voltage drops due to moisture in the power module or energy fluctuations, causing the processor to automatically enter a frequency reduction state. At this time, the algorithm's computation cycle and output cycle become unbalanced, and the processor outputs null signals prematurely before the computation is complete. The system misinterprets these null values ​​as emergency commands, triggering frequent start-stop cycles of the irrigation pump. This dynamic mis-triggering process can easily lead to a chain reaction of consequences such as overheating of the motor coil, impact on mechanical bearings, and transient oscillations in water pressure, resulting in pump burnout and damage to irrigation pipelines, causing technical problems such as unstable operation of the irrigation system.

[0005] The information disclosed in the background section is only intended to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0006] The purpose of this invention is to provide an intelligent water-saving irrigation control terminal and method based on artificial intelligence edge computing and multi-source data fusion to solve the problems mentioned in the background art.

[0007] To achieve the above objectives, the present invention provides the following technical solution: a smart water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion, comprising the following steps:

[0008] S1, a voltage regulator buffer chain is configured at the power input terminal of the irrigation control system. Capacitor energy storage and filtering voltage regulation technology are used to capture the edge and suppress fluctuations of the input voltage, and output stable and continuous electrical energy.

[0009] S2 utilizes the stable power output to maintain a constant processor clock speed in the edge computing node, freezes the signal output clock speed on the basis of the constant clock speed, and establishes a control gate synchronized with the power output clock speed.

[0010] S3 uses a synchronous control gate to delay the output of the processor before the calculation is completed, caches the control signal of the delay stage as a placeholder frame, and updates the output content after the calculation is completed to maintain the stability of the signal output.

[0011] S4. The placeholder frame is transmitted to the irrigation pump control terminal. The control terminal builds a time sequence buffer structure for signal release and sets the execution interval rhythm to avoid frequent pump start-stop and reduce the risk of mechanical shock.

[0012] S5 performs micro-step start and stop operations at the pump body actuator end according to the rhythm, and cooperates with the parallel pulse pressure relief mechanism. At the same time, it constructs an energy buffer structure between the power supply path and the load path to achieve dynamic power supply compensation and stable water pressure control.

[0013] Preferably, step S1 includes:

[0014] By connecting a three-stage capacitor energy storage structure in series at the AC input terminal, a rapid energy absorption and buffering capability is constructed, and energy balance is achieved by using capacitors with different capacitance values ​​and frequency band responses.

[0015] A multi-stage filter network is connected in series after the capacitor energy storage structure, and high-frequency noise and low-frequency ripple are suppressed simultaneously through the combination structure of inductor coil and RC absorption.

[0016] The stable electrical energy from the filtered output drives the crystal oscillator to maintain a constant processor clock speed, and the clock speed freeze window is controlled by an electronic switch trigger structure.

[0017] By setting multiple sets of latches in the delayed output channel to buffer the processing results in a timely manner, and then outputting them uniformly after the cycle time is restored, the steady state of the power supply is maintained and the signal timing is synchronized.

[0018] Preferably, step S2 includes:

[0019] The stable electrical energy after voltage regulation, buffering and multi-stage filtering is introduced into the processor's main control circuit. The voltage is stabilized by voltage regulators and the operating frequency is maintained constant by a temperature-controlled crystal oscillator.

[0020] An electronic trigger control circuit is set in the signal output path to monitor the rate of change of the input voltage and perform a clock freeze operation through a voltage comparator and an asynchronous trigger.

[0021] After the power supply is restored to stability, a control channel matching the input power cycle is established, and synchronous latching and cycle recovery are completed through cascaded delay units.

[0022] By establishing a feedback path with the output signal duty cycle as the criterion, the self-monitoring and dynamic adjustment of the cycle time are realized, forming a closed-loop stable control.

[0023] Preferably, the electronic trigger control circuit in the clock synchronization control adopts a voltage comparator and an asynchronous trigger in series. When the input voltage change rate is detected by the voltage comparator and exceeds a preset threshold, a high-level signal is triggered. After detecting the trigger signal, the asynchronous trigger starts the clock freeze operation and is unfrozen by a delay unit after the power supply recovers and stabilizes, so as to achieve strict synchronization between the signal output and the power supply clock.

[0024] Preferably, step S3 includes:

[0025] The cycle freeze and control gate synchronization mechanism are connected to the signal path, and a three-state buffer circuit is set to block the output signal that has not been calculated.

[0026] A latch structure is set at the output of the buffer circuit to keep the control signal as a neutral reference frame to form a placeholder frame in order to maintain signal continuity;

[0027] After the processor completes the calculation, the latch structure is switched by driving the identification signal, the placeholder frame is replaced with the calculation result and the signal is smoothly transitioned.

[0028] A feedback stabilization circuit is set at the back end of the latch structure to perform anomaly detection and delayed retransmission control based on the duty cycle of the output signal, thereby ensuring the stability of the signal output.

[0029] Preferably, the signal output by the latch structure is controlled by a dual-edge triggering circuit to control the switching process, and the level edge is smoothed by a filter buffer to prevent abrupt changes in the output signal during the conversion between the placeholder frame and the calculation result. At the same time, after the signal output is completed, the feedback stabilization circuit recalibrates the clock synchronization state to ensure the timing consistency and level stability of the continuous signal output.

[0030] Preferably, step S4 includes:

[0031] The placeholder frame is input to the receiving end of the pump control circuit. The signal validity is determined by the level identifier and the input signal is converted into a low-speed drive signal.

[0032] A delay control channel is set in the signal path, and a time series buffer structure is constructed through multi-level series delay triggers to achieve rhythm transmission;

[0033] A frequency limiting unit is set at the end of the delay buffer, and frequency constraint control is completed by monitoring the signal interval time and combining temperature and humidity compensation sensors.

[0034] During the output phase, the signal is guided to the power control channel, and the slow start and stop and water pressure release operation are realized through the bidirectional power switching device and soft start voltage controller to reduce the risk of mechanical shock.

[0035] Preferably, the time-series buffer structure in the delay control channel transmits signals sequentially through stage-by-stage delay triggers. Each stage trigger is filtered by a steady-state circuit to remove input jitter. In the output stage, a bidirectional power switching device and a soft-start voltage controller work in sync to make the voltage change during pump start-up and shutdown exhibit a slow rise and fall characteristic, thereby achieving stable water pressure and suppression of current surges.

[0036] Preferably, step S5 includes:

[0037] After the pump body receives the rhythm control signal, it performs micro-step start-up through a voltage graded control structure composed of a power resistor and an electronic switch connected in series to achieve smooth acceleration.

[0038] A parallel pulse pressure relief structure is set up during the micro-step start-up process, and the initial pressure peak is released by periodically opening and closing the electromagnetic control valve.

[0039] After a stable water supply is established, a dynamic energy compensation structure is formed between the power supply path and the load path through the energy buffer unit and the voltage regulator to maintain voltage stability.

[0040] During the shutdown phase, a micro-step power cut is performed in reverse order, and the pulse pressure relief channel continues to complete the segmented unloading of water pressure to achieve stable control of power supply and water pressure.

[0041] A smart water-saving irrigation control terminal based on artificial intelligence edge computing and multi-source data fusion includes a power supply voltage regulation and buffer module, a cycle synchronization control module, a delay output and placeholder buffer module, a pump control rhythm release module, and a dynamic pressure relief and energy compensation module.

[0042] The power supply voltage regulation and buffer module is configured with a voltage regulation and buffer chain at the power input terminal of the irrigation control system. It uses capacitor energy storage and filtering voltage regulation technology to capture the edge and suppress fluctuations of the input voltage, and outputs stable and continuous electrical energy.

[0043] The cycle synchronization control module uses the stable power output to maintain a constant operating cycle of the processor in the edge computing node, freezes the signal output cycle on the basis of the constant cycle, and establishes a control gate that is synchronized with the power output cycle.

[0044] The delayed output and placeholder buffer module delays the output of the processor before the calculation is completed by using a synchronous control gate, buffers the control signals of the delayed phase as placeholder frames, and updates the output content after the calculation is completed to maintain the stability of the signal output.

[0045] The pump control rhythm release module transmits the placeholder frame to the irrigation pump control terminal, constructs a time sequence buffer structure for signal release at the control terminal, and sets the execution interval rhythm to avoid frequent pump start-stop and reduce the risk of mechanical shock.

[0046] The dynamic pressure relief and energy compensation module performs micro-step start and stop operations at the pump body actuator according to the rhythm, and cooperates with the parallel pulse pressure relief mechanism. At the same time, it constructs an energy buffer structure between the power supply path and the load path to achieve dynamic power supply compensation and stable water pressure control.

[0047] The technical effects and advantages provided by the present invention in the above technical solution are as follows:

[0048] This invention systematically addresses the issues of false triggering and frequent start-stop cycles caused by unstable power supply in edge computing irrigation systems. It employs a multi-pronged collaborative strategy encompassing a voltage stabilization buffer chain, a clock synchronization mechanism, a placeholder signal buffer, time-series delay control, micro-step start-stop, parallel pulse decompression, and dynamic energy compensation. This strategy systematically solves the problems of power supply instability leading to false triggering and frequent start-stop cycles, addressing five dimensions: power supply stability, processor clock consistency, signal output accuracy, pump response rhythm, and water pressure control stability. This method not only effectively prevents abnormal pump startup caused by null signals but also significantly reduces the risks of mechanical shock, electromagnetic interference, and water hammer effects, greatly improving the service life and operational stability of irrigation equipment, and achieving a harmonious balance between water conservation, high efficiency, and precise control. Attached Figure Description

[0049] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this invention. For those skilled in the art, other drawings can be obtained based on these drawings.

[0050] Figure 1 This is a flowchart of a method for intelligent water-saving irrigation control based on artificial intelligence edge computing and multi-source data fusion according to the present invention.

[0051] Figure 2 This is a schematic diagram of a module of an intelligent water-saving irrigation control terminal based on artificial intelligence edge computing and multi-source data fusion according to the present invention. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that the description of this disclosure will be more complete and fully convey the concept of the exemplary embodiments to those skilled in the art.

[0053] This invention provides, for example Figure 1 The method for intelligent water-saving irrigation control based on artificial intelligence edge computing and multi-source data fusion includes the following steps:

[0054] S1, a voltage regulator buffer chain is configured at the power input terminal of the irrigation control system. Capacitor energy storage and filtering voltage regulation technology are used to capture the edge and suppress fluctuations of the input voltage, and output stable and continuous electrical energy.

[0055] In intelligent water-saving irrigation control methods, to ensure the stable operation of the edge computing processing unit under extreme environments, a voltage regulation and buffer strategy needs to be introduced at the power input end. This ensures that even when the input voltage fluctuates drastically, a continuous and stable power output can still be provided to maintain system cycle time and operational stability. The specific steps are as follows:

[0056] A three-stage capacitor energy storage structure is connected in series at the AC input terminal to construct a rapid energy absorption and buffering capability. Each stage uses aluminum electrolytic capacitors with different capacitance values ​​and response frequency bands. The first group is a 470 microfarad capacitor to respond to low-frequency interference from the main power supply; the second group is a 220 microfarad capacitor for mid-frequency fluctuation absorption; and the third group is a 100 microfarad low equivalent series resistance ceramic capacitor to respond to high-frequency spike interference. The three groups of capacitors are arranged in a hybrid series-parallel configuration. In actual power supply environments, through a high-capacitance buffer followed by a fast-response filtering mechanism, the structure effectively absorbs the voltage drop edge and avoids energy gaps. Actual measurements show that when the input voltage drop reaches 15% and lasts for less than 10 milliseconds, this structure can maintain the output voltage at more than 92% of the rated voltage, meeting the basic power supply continuity requirements of subsequent processors.

[0057] A multi-stage LC filter network is connected in series after the capacitor energy storage structure. This network uses a combination of magnetic core wound inductors and RC absorption structures to simultaneously suppress high-frequency noise and low-frequency ripple at the input, improving the smoothness of the voltage output. The first filter group consists of a π-type architecture formed by two 10 μH inductors, combined with a 100 μF filter capacitor to perform primary elimination of residual AC ripple. The second group uses a series structure of a self-resetting fuse resistor and an absorption capacitor to quickly share some energy when abnormal voltage pulses occur, and temporarily store and buffer the energy through the capacitor to form a stable transition. Through this LC combined filter network, the output voltage fluctuation can be controlled within 1.5%, effectively avoiding processor instability caused by high-frequency disturbances. The filtered power flow will serve as the input basis for the next step of the processor clock maintenance strategy, ensuring that the signal processing section will not experience clock drift or clock asynchrony when any short-term fluctuations occur.

[0058] Based on the stable power input from the first two steps, it is introduced into the steady-state clock control unit, where a high-precision crystal oscillator serves as the master clock source to maintain a constant processor operating frequency. In this structure, a 25 MHz crystal oscillator, combined with a temperature compensation module and an internal phase-locked loop (PLL) within the processor, is used to achieve clock locking, ensuring that the clock frequency does not shift with changes in temperature and humidity. Building upon this, an electronic switch triggering structure is constructed to respond to the edge signal of the voltage curve from the stable power input, controlling the trigger window of the output clock frequency. Specifically, when the input voltage edge change rate exceeds 5 volts per microsecond, the trigger latch closes after a delay, causing the output channel to enter a frozen state until stable power is rebuilt and maintained for more than 20 milliseconds, at which point the system resumes normal output. This design ensures that the processor clock frequency is not erroneously continued during sudden voltage edge changes, avoiding the problem of misaligned calculation and output cycles caused by clock frequency misalignment, and laying the foundation for the synchronization of subsequent signal output rhythms.

[0059] Based on the frozen output cycle mechanism, a set of controllable delayed output channels is established to ensure that the signal output always lags behind the processor's calculation completion time window. This channel is configured with three sets of displacement latches, which sequentially receive and temporarily store the processor's final calculation results. The latches do not enter the main output path until the control cycle resumes and internal verification is completed. Each set of latches has an independent hold period: 5 milliseconds for the first set, 10 milliseconds for the second set, and the third set dynamically adjusts its hold time between 15 and 30 milliseconds based on computational complexity. A unified output is triggered only when the final data remains consistent across all hold windows, ensuring that the output signal does not precede the actual calculation completion time. Furthermore, to address the impact of short-term output freezing on the overall control flow, the signal in the channel is continuously transmitted as a constant value output frame during the latch hold period. This frame signal is encoded with a set value and outputs a fixed reference signal value to maintain stable equipment operation in the downstream irrigation control section, preventing malfunctions caused by data interruption or null values. Thus, through the four-level progressive control and input response collaborative design, the steady-state maintenance of processor power supply and cycle control under unstable voltage environment have been effectively realized, providing a basic stability guarantee for the entire intelligent control process of water-saving irrigation.

[0060] S2 utilizes the stable power output to maintain a constant processor clock speed in the edge computing node, freezes the signal output clock speed on the basis of the constant clock speed, and establishes a control gate synchronized with the power output clock speed.

[0061] In edge computing-based water-saving irrigation control, to prevent processor clock drift due to unstable power supply, it is necessary to maintain a constant processor clock speed through stable power. Based on this clock speed, a signal output freezing and synchronization control mechanism is constructed to ensure that the output signal remains consistent with power supply stability in time. The specific steps are as follows:

[0062] The stable power output, after voltage regulation, buffering, and multi-stage filtering, is introduced into the processor's main control circuit. A dedicated voltage regulator stabilizes the voltage within a 3.3-volt error range, and a high-precision temperature-controlled crystal oscillator serves as the processor's master clock source. This crystal oscillator has a fixed frequency of 25 MHz and a temperature drift compensation capability of ±2 ppm, enabling it to maintain a constant oscillation frequency during long-term operation, thus ensuring the processor always operates at a fixed clock speed. In actual deployment, the crystal oscillator output is multiplied to 100 MHz via a phase-locked loop (PLL) for use by each core subunit of the processor. The PLL structure ensures clock signal synchronization across all functional units. Testing showed that under ambient temperatures ranging from 5 degrees Celsius to 45 degrees Celsius, the processor clock offset was controlled within 0.01%, ensuring absolute clock stability and laying the foundation for subsequent signal output control.

[0063] Based on constant-cycle output, an electronic trigger control circuit is added to the signal output path. This circuit consists of a high-speed voltage comparator and two asynchronous flip-flops connected in series. The former monitors the rate of change of the input voltage, while the latter locks the output cycle. During the real-time operation of the edge computing node, when the power input fluctuation exceeds a preset threshold (e.g., 0.2 volts / microsecond), the voltage comparator triggers a high-level output signal, and simultaneously, the asynchronous flip-flops initiate a cycle freeze operation, temporarily cutting off the pulse signal that was originally used to drive the signal output path. The freeze duration is set by configuring a time constant in a programmable capacitor delay network. For example, using a 100 nanofarad capacitor paired with a 47 kΩ resistor to form an RC delay network can achieve an output freeze time window of approximately 4.7 milliseconds. Within this time window, any data processing results from the processor will not be able to pass through the output path, ensuring that the output signal is not transmitted during periods of power instability.

[0064] After the clock freeze control is completed, to ensure the accuracy of freeze release and the synchronization of the recovery signal output, a control channel that strictly matches the input power clock is established after the power supply stabilizes. This control channel transmits the rising edge of the input voltage to the synchronization latch of the output channel through three cascaded delay units. Each delay unit consists of a digital shift register controlled by a temperature-controlled crystal oscillator, with a shift period completely consistent with the input voltage clock. For example, a state transfer is performed every 5 milliseconds to achieve the judgment of voltage recovery and the gradual reconstruction of clock synchronization. When the delay chain completes three cycles of signal confirmation, and the voltage change rate within each cycle is less than 0.05 volts / microsecond, the power supply is considered to have stabilized. Subsequently, the output channel latch state is released, and the clock drive resumes external output. This method effectively avoids the problem of erroneous signal output when the power supply has just recovered but is still in an unstable edge state, and ensures that the output after recovery is strictly aligned with the stable power supply through a multi-cycle synchronization mechanism.

[0065] Building upon the established clock freeze and clock synchronization control, a feedback path is set up for continuous monitoring of clock stability. This path uses the duty cycle of each processor output cycle as the criterion, feeding back the time structure of the output signal to the clock control input through voltage division sampling and integral amplification. A signal accumulation circuit with an integral time window of 20 milliseconds is incorporated into this path and coupled with a threshold recognition circuit. When the output pulse duty cycle deviation exceeds 10% for three consecutive cycles, the system automatically enters an output channel lockout state and relinquishes control to the clock freeze unit to determine whether to re-enable the output channel. This step utilizes the inherent time characteristics of the output signal to establish clock self-monitoring and dynamic adjustment capabilities, achieving closed-loop stable control during clock driving. This further enhances the system's fault tolerance and output stability in complex environments, laying a high-precision foundation for subsequent signal buffering and delay operations.

[0066] S3 uses a synchronous control gate to delay the output of the processor before the calculation is completed, caches the control signal of the delay stage as a placeholder frame, and updates the output content after the calculation is completed to maintain the stability of the signal output.

[0067] In intelligent irrigation control, to avoid erroneous signal output by the processor before calculation is complete, control signals in the incomplete calculation phase need to be delayed and buffered as placeholder frames using a synchronization structure. The signals are then output only after the calculation is complete, thus ensuring the stability of both signal timing and content. The specific steps are as follows:

[0068] The completed cycle freezing and control gate synchronization mechanism is integrated into the signal processing path, and signal truncation and delayed triggering settings are configured through a gate control circuit connected to the output channel. Specifically, a tri-state buffer circuit is placed between the processor output pin and the peripheral execution circuit. This circuit contains two independent control terminals, controlled by a power supply stabilization signal and a calculation completion flag, respectively. When the processor enters the calculation state but has not yet completed the calculation, the tri-state buffer circuit is in a high blocking state, blocking all output signal paths and ensuring that no intermediate calculation results are transmitted to the external execution loop during the incomplete calculation period. In this structure, the control signal comes from the processor's internal flag bit level conversion signal, which drives the buffer circuit to close after delay calibration. In environmental testing, even when the processor's computational complexity causes a single calculation cycle to exceed 100 milliseconds, there is still no signal leakage at the output terminal, ensuring that external behavior is not interfered with by incomplete calculation data.

[0069] To address the issue of floating output signals in the buffered state, a holding structure is introduced at the output of the tri-state buffer circuit. This structure consists of a set of latching elements and a fixed reference signal generator. The latching elements are a set of triple NOT gate latches, where each control signal is forced to remain in a stable state, with a default output of a neutral reference frame. For example, in the default state, all signal outputs are set to a continuous high level, forming a placeholder frame without triggering characteristics. This simulates the continuous existence of the execution signal but does not contain specific control information. The duration of this placeholder frame output is equal to the maximum value of the calculation period plus a redundancy delay, typically set to 150 milliseconds. During this period, signals received by external devices will not trigger any response due to null values ​​or fluctuations, thus maintaining continuous signal output. During periods of power instability, this reference frame maintains a stable output state and does not generate jitter signals with changes in the calculation state.

[0070] After the processor completes its internal calculations and generates valid control data, the output channel is restarted via a preceding clock synchronization structure. A completion flag signal drives the latch structure to switch, replacing the buffered placeholder frame with the actual calculation result. This replacement process is controlled by a dual-edge trigger circuit to ensure no intermediate level changes during signal switching. Specifically, when the rising edge of the calculation completion signal is detected, the output switching channel is activated, and the latch releases its buffer, terminating the placeholder frame output. Simultaneously, the processor output pin loads the current control data. The entire switching process uses a five-stage filter buffer to slowly raise and lower the level edges, preventing accidental level triggering and ensuring a smooth signal transition. The output data is released in a stable clock cycle, maintaining synchronization with the power supply stabilization period, thus achieving the conversion of the signal content from placeholder to actual data. Furthermore, the output time is strictly later than the processor's calculation completion point.

[0071] To ensure the stability and robustness of the delayed output structure during long-term operation, a feedback stabilization circuit is designed at the back end of the latch structure. This circuit constructs an anomaly detection mechanism based on the signal duty cycle. When the output signal duty cycle is detected to be significantly lower than a preset reference threshold over multiple cycles (e.g., below 30% for three consecutive cycles), the feedback structure is activated, driving the signal holding path into a safe standby state, and simultaneously sending a secondary calculation request flag to the processor. This design allows for adaptive control through an automatic delayed retransmission mechanism when occasional abnormal data occurs during the calculation output process, further improving the stability and continuity of the signal output link. In actual operation, this method effectively prevents erroneous outputs caused by processor overflow, external interference, etc., ensuring the accuracy and stability of signal output from edge control nodes in long-term high-load field environments.

[0072] S4. The placeholder frame is transmitted to the irrigation pump control terminal. The control terminal builds a time sequence buffer structure for signal release and sets the execution interval rhythm to avoid frequent pump start-stop and reduce the risk of mechanical shock.

[0073] After the processor completes its output calculation, the placeholder frame is transmitted to the irrigation pump control terminal as a stable signal holding structure. A time-series buffer mechanism needs to be constructed to ensure the rhythmic release of the output signal, preventing frequent pump starts and stops due to sudden changes in the control signal, thereby reducing the risk of mechanical shock to the motor and pipeline. The specific steps are as follows:

[0074] The generated and output placeholder frame is input to the receiving end of the pump control circuit in standard voltage level form. This receiving end uses a set of level identifiers to distinguish the received signal. To avoid identification errors caused by signal jitter or inconsistent levels, the level identifiers employ a three-stage comparison structure to statistically analyze the voltage stability of the input signal under three time windows. For example, a cascaded method using 10ms, 30ms, and 50ms time windows is used; if the identification results of the three are consistent, the signal is confirmed as a valid input. After confirmation, the input signal is converted into a low-speed drive signal to avoid instantaneous electrical stress impact on the solenoid valve and pump body caused by high-speed triggering. After voltage recognition stabilizes, the signal does not directly drive the pump body to start; instead, it first enters the delay control channel for staged rhythmic processing.

[0075] To ensure the pump's operation exhibits smooth start-stop characteristics, a time-series buffer structure for signal release is incorporated into the delay control channel. This structure consists of a series of cascaded delay triggers, each delaying signal transmission by a fixed duration. For example, setting each stage's delay to 10 milliseconds results in a maximum release delay of 70 milliseconds through a seven-stage structure. The signal is re-latched at each delay stage and denoised by a filtering steady-state circuit to eliminate the risk of accidental triggering due to input jitter. The trigger output of each stage automatically updates its control level in the next stage, ultimately transmitting a stable rhythm signal to the pump's action execution pin. During this process, the pump receives control signals at varying speeds, achieving preheating before operation and smooth stopping after operation. This allows time for the current to build up in the motor's internal magnetic coils, preventing repeated impacts from inrush current and reverse current on the windings.

[0076] To further enhance rhythmicity and controllability, a frequency limiting unit is installed at the end of the delay buffer structure. This unit automatically blocks over-frequency control signals by monitoring the interval between consecutive signals. For example, if the minimum action interval is set to 5 seconds, when the interval between two start signals is less than this threshold, the second signal will be intercepted by the frequency limiting unit and replaced with a placeholder signal, thus preventing the pump from repeatedly operating within a short period. This structure not only extends the equipment's lifespan but also improves the overall stability of the water pressure system. In practical deployment, by adjusting this frequency threshold, it can adapt to the irrigation response characteristics of different crop types and soil conditions, exhibiting high scene adaptability. Furthermore, to prevent misjudgment of frequency in extreme environments, the input channel of the frequency limiting unit is equipped with temperature and humidity compensation sensors. Their signals are quantified as weighting factors to participate in interval judgment, ensuring stable operation even under high temperature and high humidity conditions.

[0077] After delay buffering and frequency limiting, the signal is finally guided to the power control channel of the pump actuator, which consists of a bidirectional power switching device and a soft-start voltage controller. The bidirectional power switching device selects the energy supply path at the moment of pump startup, ensuring that voltage surges are not directly applied to the coil terminals. Upon receiving the action signal, the soft-start voltage controller first injects a starting current into the pump at 60% of the rated voltage, and then gradually increases it to the rated voltage over the next 200 milliseconds, forming a gradual start-up process for the motor. When the pump stops operating, the control channel performs a voltage reduction operation in reverse order, first lowering the voltage to 40%, and then completely shutting off the current, a process that takes approximately 250 milliseconds. During this stage, to further reduce mechanical shock, the water flow guidance path controlled by the solenoid valve synchronously switches to the slow-release branch, preventing water hammer impact on the pipeline caused by sudden drops in main water pressure. Through this integrated time-series control strategy, the placeholder frame signal not only achieves rhythmic transmission but also ensures the long-term operational stability and shock resistance of the pump and its auxiliary structures through a multi-stage slow-release mechanism.

[0078] S5 performs micro-step start and stop operations at the pump body actuator end according to the rhythm, and cooperates with the parallel pulse pressure relief mechanism. At the same time, it constructs an energy buffer structure between the power supply path and the load path to achieve dynamic power supply compensation and stable water pressure control.

[0079] At the pump's actuator end, when irrigation commands arrive rhythmically, to reduce water pressure fluctuations and electrical shocks during pump start-up and shutdown, a micro-step operation is required, supplemented by parallel pulse pressure relief and energy buffering strategies, thereby achieving dynamic balance between power supply and load and water pressure stability. The specific steps are as follows:

[0080] After receiving the rhythmic control signal, which has been buffered over time, the pump body activates the voltage-level control structure in the front-end execution circuit. This structure consists of multiple power resistors connected in series with electronic switches, achieving a micro-step start-up process by setting step voltage levels. Specifically, three sets of power resistors are connected sequentially to the pump body's main coil circuit at 5%, 20%, and 50% of rated power, with each level lasting approximately 80 milliseconds, and the total step time not exceeding 300 milliseconds. When the first set of power resistors is connected, the pump body only produces a low-speed initial rotation to establish a micro-flow within the pipeline; the second set increases the pump speed, causing the water flow to increase linearly; the third set reaches the rated flow rate start-up threshold, and the pump body enters the normal water supply stage. This micro-step method effectively reduces the strong current surge caused by instantaneous full-load energization in traditional irrigation, lowering the risk of motor winding overheating and electromagnetic interference during startup.

[0081] A parallel pulse pressure relief structure is simultaneously constructed during the micro-step start-up process to release the initial pressure spike caused by the inertia of the water column during the initial rise of the water flow. This structure uses a set of electromagnetic control valves to create a bypass branch, which is connected in parallel with the main water supply pipeline. The control valves open and close according to a set cycle. The duration of each opening is controlled between 50 and 70 milliseconds, accompanied by a gradual opening and closing throttling process to control the water release rate. Each time the pump completes a voltage boost, the pulse valves respond synchronously with an opening cycle, thereby clipping the rising peak in the water pressure curve. Before the pump fully enters the rated water supply stage, the pulse pressure relief branch continues to operate, forming a stable pressure rise curve and ensuring that the main pipeline water pressure does not exceed 110% of the rated water pressure during startup. This structure is particularly important for long-distance, low-slope irrigation areas, as it can significantly reduce the probability of water hammer.

[0082] After a stable water supply is established, an energy buffer structure is constructed between the power supply path and the load path to form a dynamic energy compensation mechanism. This structure consists of a set of energy buffer units connected in series with a voltage regulator on the pump's power supply line. The energy buffer units adopt a parallel structure of ultra-large capacity capacitor banks, including four sets of 10,000 microfarad industrial-grade capacitors, which can store sufficient electrical energy in a short time. The voltage regulator monitors changes in the pump's load in real time. When the current rises instantaneously by more than 10%, the buffer units release the stored energy to compensate the pump; when the load decreases, the regulator guides the excess energy back to the capacitor bank for recharging. Through this cyclical energy regulation process, the pump maintains stable voltage under different load fluctuations, suppressing feedback current surges caused by instantaneous valve closures or branch switching in the irrigation area. At the same time, the energy buffer structure forms a voltage stabilizing source for the entire power supply chain, protecting upstream power supply equipment from reverse disturbances.

[0083] During the pump shutdown phase, a micro-step power-off operation is performed in the reverse sequence of the startup phase, while the pulse pressure relief channel continues to function, completing the segmented unloading of water pressure. 200 milliseconds before the power-off, the power control circuit is switched to step-reduction control mode, gradually reducing the input voltage. For example, first reducing it to 70%, then to 40%, and finally completely cutting off the power. Each power-off action is coordinated with the release cycle of the pulse pressure relief branch, resulting in a step-like decrease in the water pressure curve. Simultaneously, the buffer capacitor bank absorbs the reverse induced current in the coil in the load path, preventing the current from rebounding and forming an arc or causing localized burning at the moment of power-off. After all power is disconnected, the pulse valve enters a continuous release state, lasting 90 milliseconds for complete pressure relief, ensuring that the residual water pressure in the irrigation pipe remains below 30% of the initial pressure, reducing the backflow's impact on the pump impeller structure. Thus, through the coordinated operation of three components—micro-step voltage control, synchronous pulse pressure release, and dynamic energy buffering—dual stable control of electrical energy regulation and water pressure slow release is achieved throughout the pump's start-up and shutdown process, ensuring the smooth and efficient operation of the entire irrigation system in both electrical and hydraulic aspects.

[0084] This invention systematically addresses the issues of false triggering and frequent start-stop cycles caused by unstable power supply in edge computing irrigation systems. It employs a multi-pronged collaborative strategy encompassing a voltage stabilization buffer chain, a clock synchronization mechanism, a placeholder signal buffer, time-series delay control, micro-step start-stop, parallel pulse decompression, and dynamic energy compensation. This strategy systematically solves the problems of power supply instability leading to false triggering and frequent start-stop cycles, addressing five dimensions: power supply stability, processor clock consistency, signal output accuracy, pump response rhythm, and water pressure control stability. This method not only effectively prevents abnormal pump startup caused by null signals but also significantly reduces the risks of mechanical shock, electromagnetic interference, and water hammer effects, greatly improving the service life and operational stability of irrigation equipment, and achieving a harmonious balance between water conservation, high efficiency, and precise control.

[0085] This invention provides, for example Figure 2 The intelligent water-saving irrigation control terminal based on artificial intelligence edge computing and multi-source data fusion, shown, includes a power supply voltage regulation and buffer module, a cycle synchronization control module, a delay output and placeholder buffer module, a pump control rhythm release module, and a dynamic pressure relief and energy compensation module.

[0086] The power supply voltage regulation and buffer module is configured with a voltage regulation and buffer chain at the power input terminal of the irrigation control system. It uses capacitor energy storage and filtering voltage regulation technology to capture the edge and suppress fluctuations of the input voltage, and outputs stable and continuous electrical energy.

[0087] The cycle synchronization control module uses the stable power output to maintain a constant operating cycle of the processor in the edge computing node, freezes the signal output cycle on the basis of the constant cycle, and establishes a control gate that is synchronized with the power output cycle.

[0088] The delayed output and placeholder buffer module delays the output of the processor before the calculation is completed by using a synchronous control gate, buffers the control signals of the delayed phase as placeholder frames, and updates the output content after the calculation is completed to maintain the stability of the signal output.

[0089] The pump control rhythm release module transmits the placeholder frame to the irrigation pump control terminal, constructs a time sequence buffer structure for signal release at the control terminal, and sets the execution interval rhythm to avoid frequent pump start-stop and reduce the risk of mechanical shock.

[0090] The dynamic pressure relief and energy compensation module performs micro-step start and stop operations at the pump body actuator according to the rhythm, and cooperates with the parallel pulse pressure relief mechanism. At the same time, it constructs an energy buffer structure between the power supply path and the load path to achieve dynamic power supply compensation and stable water pressure control.

[0091] This invention provides an intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion. This method is implemented through an intelligent water-saving irrigation control terminal based on artificial intelligence edge computing and multi-source data fusion. For details on the specific method and process of the intelligent water-saving irrigation control terminal based on artificial intelligence edge computing and multi-source data fusion, please refer to the above-mentioned embodiment of the intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion, which will not be repeated here.

[0092] The foregoing has only described certain exemplary embodiments of the present invention by way of illustration. Undoubtedly, those skilled in the art can modify the described embodiments in various ways without departing from the spirit and scope of the present invention. Therefore, the foregoing drawings and descriptions are illustrative in nature and should not be construed as limiting the scope of protection of the claims of the present invention.

Claims

1. A smart water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion, characterized in that, Includes the following steps: S1, a voltage regulator buffer chain is configured at the power input terminal of the irrigation control system. Capacitor energy storage and filtering voltage regulation technology are used to capture the edge and suppress fluctuations of the input voltage, and output stable and continuous electrical energy. S2 utilizes the stable power output to maintain a constant processor clock speed in the edge computing node, freezes the signal output clock speed on the basis of the constant clock speed, and establishes a control gate synchronized with the power output clock speed. S3 uses a synchronous control gate to delay the output of the processor before the calculation is completed, caches the control signal of the delay stage as a placeholder frame, and updates the output content after the calculation is completed to maintain the stability of the signal output. S4. The placeholder frame is transmitted to the irrigation pump control terminal. The control terminal builds a time sequence buffer structure for signal release and sets the execution interval rhythm to avoid frequent pump start-stop and reduce the risk of mechanical shock. S5 performs micro-step start and stop operations at the pump body actuator end according to the rhythm, and cooperates with the parallel pulse pressure relief mechanism. At the same time, it constructs an energy buffer structure between the power supply path and the load path to achieve dynamic power supply compensation and stable water pressure control. Step S5 includes: After the pump body receives the rhythm control signal, it performs micro-step start-up through a voltage graded control structure composed of a power resistor and an electronic switch connected in series to achieve smooth acceleration. A parallel pulse pressure relief structure is set up during the micro-step start-up process, and the initial pressure peak is released by periodically opening and closing the electromagnetic control valve. After a stable water supply is established, a dynamic energy compensation structure is formed between the power supply path and the load path through the energy buffer unit and the voltage regulator to maintain voltage stability. During the shutdown phase, a micro-step power cut is performed in reverse order, and the pulse pressure relief channel continues to complete the segmented unloading of water pressure to achieve stable control of power supply and water pressure.

2. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 1, characterized in that, Step S1 includes: By connecting a three-stage capacitor energy storage structure in series at the AC input terminal, a rapid energy absorption and buffering capability is constructed, and energy balance is achieved by using capacitors with different capacitance values ​​and frequency band responses. A multi-stage filter network is connected in series after the capacitor energy storage structure, and high-frequency noise and low-frequency ripple are suppressed simultaneously through the combination structure of inductor coil and RC absorption. The stable electrical energy from the filtered output drives the crystal oscillator to maintain a constant processor clock speed, and the clock speed freeze window is controlled by an electronic switch trigger structure. By setting multiple sets of latches in the delayed output channel to buffer the processing results in a timely manner, and then outputting them uniformly after the cycle time is restored, the steady state of the power supply is maintained and the signal timing is synchronized.

3. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 2, characterized in that, Step S2 includes: The stable electrical energy after voltage regulation, buffering and multi-stage filtering is introduced into the processor's main control circuit. The voltage is stabilized by voltage regulators and the operating frequency is maintained constant by a temperature-controlled crystal oscillator. An electronic trigger control circuit is set in the signal output path to monitor the rate of change of the input voltage and perform a clock freeze operation through a voltage comparator and an asynchronous trigger. After the power supply is restored to stability, a control channel matching the input power cycle is established, and synchronous latching and cycle recovery are completed through cascaded delay units. By establishing a feedback path with the output signal duty cycle as the criterion, the self-monitoring and dynamic adjustment of the cycle time are realized, forming a closed-loop stable control.

4. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 3, characterized in that, The electronic trigger control circuit in the clock synchronization control adopts a series structure of voltage comparator and asynchronous trigger. When the voltage comparator detects that the rate of change of the input voltage exceeds the preset threshold, it triggers a high-level signal. After detecting the trigger signal, the asynchronous trigger starts the clock freeze operation and is unfrozen by the delay unit after the power supply recovers and stabilizes, so as to achieve strict synchronization between the signal output and the power supply clock.

5. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 3, characterized in that, Step S3 includes: The cycle freeze and control gate synchronization mechanism are connected to the signal path, and a three-state buffer circuit is set to block the output signal that has not been calculated. A latch structure is set at the output of the buffer circuit to keep the control signal as a neutral reference frame to form a placeholder frame in order to maintain signal continuity; After the processor completes the calculation, the latch structure is switched by the identification signal, the placeholder frame is replaced with the calculation result and the signal is smoothly transitioned. A feedback stabilization circuit is set at the back end of the latch structure to perform anomaly detection and delayed retransmission control based on the duty cycle of the output signal, thereby ensuring the stability of the signal output.

6. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 5, characterized in that, The signal output by the latch structure is controlled by a dual-edge triggering circuit to control the switching process, and the level edge is smoothed by a filter buffer to prevent abrupt changes in the output signal during the conversion between the placeholder frame and the calculation result. At the same time, after the signal output is completed, the feedback stabilization circuit recalibrates the clock synchronization state to ensure the timing consistency and level stability of the continuous signal output.

7. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 5, characterized in that, Step S4 includes: The placeholder frame is input to the receiving end of the pump control circuit. The signal validity is determined by the level identifier and the input signal is converted into a low-speed drive signal. A delay control channel is set in the signal path, and a time series buffer structure is constructed through multi-level series delay triggers to achieve rhythm transmission; A frequency limiting unit is set at the end of the delay buffer, and frequency constraint control is completed by monitoring the signal interval time and combining temperature and humidity compensation sensors. During the output phase, the signal is guided to the power control channel, and the slow start and stop and water pressure release operation are realized through the bidirectional power switching device and soft start voltage controller to reduce the risk of mechanical shock.

8. The intelligent water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion according to claim 7, characterized in that, The time-series buffer structure in the delay control channel transmits signals sequentially through stage-by-stage delay triggers. Each stage of the triggers is filtered and stabilized by a filter circuit to remove input jitter. In the output stage, the bidirectional power switching device and the soft-start voltage controller work in sync to make the voltage change during pump start-up and shutdown exhibit a slow rise and fall characteristic, thereby achieving stable water pressure and suppression of current surges.

9. A smart water-saving irrigation control terminal based on artificial intelligence edge computing and multi-source data fusion, used to implement the smart water-saving irrigation control method based on artificial intelligence edge computing and multi-source data fusion as described in any one of claims 1-8, characterized in that, It includes a power supply voltage regulation and buffer module, a clock synchronization control module, a delay output and placeholder buffer module, a pump-controlled rhythm release module, and a dynamic pressure relief and energy compensation module. The power supply voltage regulation and buffer module is configured with a voltage regulation and buffer chain at the power input terminal of the irrigation control system. It uses capacitor energy storage and filtering voltage regulation technology to capture the edge and suppress fluctuations of the input voltage, and outputs stable and continuous electrical energy. The cycle synchronization control module uses the stable power output to maintain a constant operating cycle of the processor in the edge computing node, freezes the signal output cycle on the basis of the constant cycle, and establishes a control gate that is synchronized with the power output cycle. The delayed output and placeholder buffer module delays the output of the processor before the calculation is completed by using a synchronous control gate, buffers the control signals of the delayed phase as placeholder frames, and updates the output content after the calculation is completed to maintain the stability of the signal output. The pump control rhythm release module transmits the placeholder frame to the irrigation pump control terminal, constructs a time sequence buffer structure for signal release at the control terminal, and sets the execution interval rhythm to avoid frequent pump start-stop and reduce the risk of mechanical shock. The dynamic pressure relief and energy compensation module performs micro-step start and stop operations at the pump body actuator according to the rhythm, and cooperates with the parallel pulse pressure relief mechanism. At the same time, it constructs an energy buffer structure between the power supply path and the load path to achieve dynamic power supply compensation and stable water pressure control.

Images