Data processing apparatus and method, electronic device

Abstract

The present disclosure provides a data processing apparatus and method, and an electronic device. The apparatus comprises an instruction input module, an internal storage module and an instruction execution module. The instruction input module is configured to read an unexecuted target instruction from a first and / or second instruction queue according to a target identifier of a first entry which is idle in the internal storage module and an instruction category in a second entry which is not idle, and store instruction information of the target instruction to the first entry. The instruction execution module is configured to execute the target instruction according to the instruction category in the case that the instruction information is stored in the first entry, and send an interrupt signal of the target instruction to the instruction input module in the case that the execution result is successful. According to embodiments of the present disclosure, the instruction execution efficiency can be improved.

Description

Technical Field

[0001] This disclosure relates to the field of computer technology, and in particular to a data processing apparatus and method, and an electronic device. Background Technology

[0002] In modern computer systems, System-on-a-Chip (SoC) architecture, integrated within a chip, has been widely adopted as a high-performance computing architecture. A chip typically contains a Central Processing Unit (CPU), on-chip memory, and other components to perform tasks and perform data storage functions. During normal operation, the CPU needs to read data from memory and move it to internal caches (e.g., Static Random-Access Memory (SRAM)); it also needs to perform other types of tasks such as data comparison.

[0003] However, CPUs operate at different efficiencies for different types of data processing tasks. Existing technologies cannot simultaneously meet the demands of high-concurrency data comparison (small data, low latency) and large-scale data transfer (high throughput). Summary of the Invention

[0004] This disclosure provides a data processing apparatus and method, and an electronic device.

[0005] In a first aspect, this disclosure provides a data processing apparatus, comprising: an instruction input module, an internal storage module, and an instruction execution module. The instruction input module is configured to: read unexecuted target instructions from a first instruction queue and / or a second instruction queue based on the entry identifier of a first idle entry among a plurality of instruction entries in the internal storage module and the instruction category of instructions in a non-idle second entry; and store the instruction information of the target instructions into the first entry; wherein the first instruction queue includes instructions of a first category with an instruction execution count of 1, and the second instruction queue includes instructions of a second category with an instruction execution count greater than or equal to 1. The instruction execution module is configured to: execute the target instruction according to its instruction category when the instruction information of the target instruction is stored in the first entry; and send an interrupt signal for the target instruction to the instruction input module if the execution result of the target instruction is successful.

[0006] Secondly, this disclosure provides a data processing method, which includes: reading unexecuted target instructions from a first instruction queue and / or a second instruction queue based on the entry identifier of an idle first entry among a plurality of instruction entries and the instruction category of instructions in a non-idle second entry; and storing the instruction information of the target instructions into the first entry; wherein the first instruction queue includes instructions of a first category with an instruction execution count of 1, and the second instruction queue includes instructions of a second category with an instruction execution count greater than or equal to 1; executing the target instructions according to the instruction category of the target instructions to obtain the execution result of the target instructions; and, if the execution result of the target instructions is successful, reporting an interrupt signal for the target instructions.

[0007] Thirdly, this disclosure provides an electronic device that includes the aforementioned data processing apparatus.

[0008] The embodiments provided in this disclosure can manage different types of instruction queues simultaneously. The instruction input module reads the target instruction from the instruction queue and stores it in the idle instruction entry according to the identifier of the idle instruction entry in the internal storage module and the instruction category in the non-idle instruction entry. The instruction execution module executes the target instruction according to the instruction category and returns the interrupt signal of the target instruction when the execution is successful, thereby realizing the scheduling of different instruction queues and executing different types of instructions in the queue at the same time, reducing the system's processing overhead and improving the system's instruction execution efficiency.

[0009] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this disclosure, nor is it intended to limit the scope of this disclosure. Other features of this disclosure will become readily apparent from the following description. Attached Figure Description

[0010] The accompanying drawings are provided to further illustrate the present disclosure and form part of the specification. They are used together with the embodiments of the present disclosure to explain the disclosure and do not constitute a limitation thereof. The above and other features and advantages will become more apparent to those skilled in the art from the detailed exemplary embodiments described with reference to the accompanying drawings.

[0011] Figure 1 This is a schematic diagram of the structure of a data processing device provided in an embodiment of the present disclosure.

[0012] Figure 2 This is a flowchart of a data processing method provided in an embodiment of the present disclosure.

[0013] Figure 3 This is a block diagram of an electronic device provided in an embodiment of the present disclosure. Detailed Implementation

[0014] To enable those skilled in the art to better understand the technical solutions of this disclosure, exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments of this disclosure to aid understanding. These should be considered merely exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and conciseness, descriptions of well-known functions and structures are omitted in the following description.

[0015] Where there is no conflict, the various embodiments of this disclosure and the features thereof in the embodiments may be combined with each other.

[0016] As used herein, the term “and / or” includes any and all combinations of one or more related enumerated entries.

[0017] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this disclosure. As used herein, the singular forms “a” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that when the terms “comprising” and / or “made of” are used in this specification, the presence of the stated feature, integral, step, operation, element, and / or component is specified, but the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof is not excluded. Words such as “connected” or “linked” are not limited to physical or mechanical connections but can include electrical connections, whether direct or indirect.

[0018] Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and this disclosure, and will not be interpreted as having an idealized or overly formal meaning, unless expressly so defined herein.

[0019] In a SoC chip, the host usually refers to the software program running on the upper layer of the SoC chip, which is used to receive external tasks and send them to the chip for execution. Firmware (FW) usually refers to the hardware program running on the chip, which is used to drive the hardware (such as the CPU) to execute the tasks and instructions sent by the host.

[0020] In actual task processing, the tasks to be processed may include data transfer tasks and data comparison tasks. In data comparison tasks, a semaphore is a mechanism used to synchronize access to shared resources by multiple execution threads (or tasks); essentially, it is a counter. If the host side wants the firmware to execute a task, but this task depends on the completion of some other preceding tasks, the host side will quantify this dependency into a value, namely the semaphore's dependency value, and write it into the firmware's instruction queue. Simultaneously, there is a shared variable in on-chip memory, namely the current value of the semaphore. Each time a preceding task completes, a release operation is performed, atomically incrementing the semaphore's current value by 1. The on-chip CPU needs to frequently read this current value from memory and compare it with the dependency value sent by the host side. If the condition is met, the firmware can execute the task; otherwise, it needs to be checked again later—this is the polling mechanism.

[0021] In related technologies, the firmware typically controls the CPU to initiate data reading and comparison operations sequentially. This is a sequential operation, and it is impossible to control the CPU to initiate a large number of data reading operations at the same time. This results in low efficiency of the CPU when executing data comparison instructions, requiring a dedicated data comparison unit (Value Compare Engine, VCE) to perform the comparison processing.

[0022] In data transfer tasks, the CPU needs to read data from memory and move it to the internal cache, which can be considered to be a direct memory access (DMA) operation. Related technologies will design a dedicated DMA module to accelerate the data transfer process.

[0023] DMA instructions are typically few in number and have short execution cycles, while VCE instructions are typically numerous but have long execution cycles, requiring constant polling and repeated comparisons. However, the CPU's operation of reading the current value of a semaphore is similar to the implementation of data transfer operations. Related DMA engines struggle to simultaneously meet the demands of high-concurrency data comparison (small data, low latency) and large-scale data transfer (high throughput). Therefore, a new data management architecture, also known as a high-speed Data Management Unit (DMU), is urgently needed to efficiently support both long and short loop queues.

[0024] According to embodiments of this disclosure, a data processing apparatus is provided that can simultaneously manage instruction queues of different types. The instruction input module reads a target instruction from the instruction queue and stores it in a free instruction entry based on the identifier of a free instruction entry in the internal storage module and the instruction category in a non-free instruction entry. The instruction execution module executes the target instruction according to the instruction category and returns an interrupt signal for the target instruction when the execution is successful. This enables the scheduling of different instruction queues and the simultaneous execution of instructions of different types in the queues, reducing the system's processing overhead and improving the system's instruction execution efficiency.

[0025] The data processing apparatus according to embodiments of this disclosure, also known as a data management unit, can be applied to a chip system and can be any chip system itself, or a device or component within the chip system. The chip system can be, for example, a central processing unit (CPU), a graphics processing unit (GPU), a data processing unit (DPU), etc. This disclosure does not limit the specific type of chip system corresponding to the data processing apparatus.

[0026] Figure 1 This is a schematic diagram of a data processing apparatus provided in an embodiment of the present disclosure. (Refer to...) Figure 1 The data processing apparatus according to embodiments of this disclosure may include an instruction input module 11, an internal storage module 12, an instruction execution module 13, and a register control (REG_CTRL) module 14. The instruction input module 11 connects to the on-chip cache of the firmware FM via a preset communication interface to retrieve instructions from the instruction queue in the on-chip cache. The host side can send the instructions corresponding to the tasks to be executed by the firmware to the instruction queue.

[0027] In the example, when the communication interface uses an Advanced eXtensible Interface (AXI) and static random-access memory (SRAM) is used as internal storage, the instruction input module 11 can be referred to as AXI_I; the internal storage module 12 can be referred to as DESC_SRAM; and the instruction execution module 13 can be referred to as AXI_D. This disclosure does not limit the specific type of the communication interface or the specific storage type of the internal storage.

[0028] In some possible implementations, the instruction queue may include a first instruction queue and a second instruction queue, wherein the first instruction queue includes instructions of a first category that are executed once, and the second instruction queue includes instructions of a second category that are executed once or more.

[0029] In other words, the first instruction queue is a short circular queue, where the lifetime of each instruction is 1, meaning the instruction is executed 1 time, and they are executed sequentially. The second instruction queue is a long circular queue, where the lifetime of each instruction depends on the number of times it is executed, requiring polling until the instruction is successfully executed, meaning the number of times an instruction is executed is greater than or equal to 1, and they are executed out of order.

[0030] In some possible implementations, the first category of instructions includes data transfer instructions based on direct memory access (DMA); the second category of instructions includes data comparison instructions based on the data comparison unit (VCE).

[0031] In the exemplary use case, data transfer instructions based on Direct Memory Access (DMA) can also be directly referred to as DMA instructions and are executed in a short circular queue; data comparison instructions based on the Data Comparison Unit (VCE) can also be directly referred to as VCE instructions and are executed in a long circular queue.

[0032] In some possible implementations, the instruction input module 11 is configured to: read unexecuted target instructions from the first instruction queue and / or the second instruction queue according to the entry identifier of the first idle entry among the multiple instruction entries of the internal storage module 12 and the instruction category of the instructions in the non-idle second entry; and store the instruction information of the target instructions into the first entry.

[0033] The instruction execution module 13 is configured to: execute the target instruction according to the instruction category of the target instruction when the instruction information of the target instruction is stored in the first entry; and send an interrupt signal of the target instruction to the instruction input module when the execution result of the target instruction is successful.

[0034] For example, the instruction input module 11 is responsible for reading instructions and maintaining instruction identifiers (IDs); the internal storage module 12 has multiple instruction entries, each of which stores the instruction information of an instruction. Each instruction entry has an entry identifier, which indicates the storage address corresponding to the instruction entry; the instruction execution module 13 is used to read instruction information from the instruction entries and perform the corresponding processing.

[0035] In the case of using the AXI interface, the entry identifier can be the AXI interface identifier, supporting concurrent processing of outstanding transactions within the AXI interface. This allows the master device (e.g., the CPU) to initiate multiple bus transactions consecutively without receiving a response from the previous transaction. In the example, the number of instruction entries (or the depth of the internal storage module) can be 32, storing a maximum of one instruction of the first category and 31 instructions of the second category. It should be understood that those skilled in the art can set the number of instruction entries and the maximum number of instructions in each category according to actual circumstances, and this disclosure does not impose any limitations on this.

[0036] In some possible implementations, if there is a free first entry in the instruction entries of the internal storage module, the internal storage module will send the entry identifier of the first entry to the instruction input module; after receiving the entry identifier of the first entry, the instruction input module can read instructions from the first instruction queue and the second instruction queue and arbitrate.

[0037] In some possible implementations, instructions in both the first and second instruction queues have flag bits indicating the instruction category. For example, a flag bit of 1 indicates that the instruction is a first-category instruction, i.e., a DMA instruction; a flag bit of 0 indicates that the instruction is a second-category instruction, i.e., a VCE instruction. These flag bits are stored in a non-free second entry in the internal memory module.

[0038] In some possible implementations, the instruction input module arbitrates the instruction category of the instruction in the non-free second entry of the instruction entries in the internal storage module; if the second entry includes instructions of the first category, the arbitration result is to read instructions of the second category this time; if the second entry does not include instructions of the first category, the arbitration result is to prioritize reading at least one instruction of the first category this time; and the total number of instructions to be read this time is determined according to the number of the first entries, thereby obtaining the target instruction to be read this time.

[0039] In the example, the second entry does not include instructions of the first category. The number of first entries is 5, so one instruction of the first category and four instructions of the second category can be read to obtain 5 target instructions.

[0040] In some possible implementations, the instruction input module can read the target instruction, delete the reserved bits in the target instruction, and write the remaining content as instruction information into the corresponding first entry.

[0041] In this way, the instruction entries of the internal storage module can store two types of instructions at the same time, enabling parallel processing of different types of instructions and improving processing efficiency.

[0042] In some possible implementations, after the instruction information of the target instruction is stored in the first entry of the internal storage module 12, it notifies the instruction execution module 13 to read the data. Upon receiving the notification from the internal storage module 12, the instruction execution module 13 can read the instruction information of the target instruction from the internal storage module 12 to determine the category of the target instruction; it then executes the target instruction according to the instruction category, for example, by moving or comparing corresponding data. If the execution result of the target instruction is successful, it sends the entry identifier and interrupt signal corresponding to the target instruction to the instruction input module for reporting.

[0043] In this way, different instruction queues can be scheduled, enabling parallel execution of different types of instructions in the queues, reducing system processing overhead and improving system execution efficiency.

[0044] The data processing apparatus according to embodiments of the present disclosure will now be described in detail.

[0045] After system startup, the host side can send the instructions corresponding to the tasks to be executed by the firmware to the instruction queue in the on-chip cache. The instruction input module 11 connects to the on-chip cache through a preset communication interface to read the instructions in the instruction queue. Different types of instructions are sent to different instruction queues. The first instruction queue includes instructions of the first type with an execution count of 1, and the second instruction queue includes instructions of the second type with an execution count greater than or equal to 1.

[0046] In some possible implementations, the data processing apparatus of this disclosure embodiment further includes a register control module 14 for maintaining the execution state of instructions.

[0047] In some possible implementations, the instruction input module is also configured to: when there is a new instruction in the first instruction queue and / or the second instruction queue, set the execution status bit corresponding to the new instruction in the register control module and set the execution status bit to the first value.

[0048] In other words, whenever the first instruction queue and / or the second instruction queue receives a new instruction, referred to as a new instruction, the instruction ID of the new instruction is recorded in the register control module, and the execution status bit corresponding to the new instruction is set. The value of the execution status bit is set to a first value, which indicates that the instruction has not been executed; correspondingly, a second value is used to indicate that the instruction has been executed. In the example, the first value can be set to 0, and the second value can be set to 1. In this way, the instruction execution status can be maintained.

[0049] In some possible implementations, the instruction input module can detect the value of the execution status bit of the instruction in the register control module. When there is an instruction with the execution status bit set to the first value in the first instruction queue and / or the second instruction queue, that is, when there is an instruction that has not been executed, the instruction input module starts the polling and reading of instructions.

[0050] At startup, all instruction entries in the internal storage module 12 are idle. The instruction input module can directly start reading the instruction from the head of the first instruction queue and the second instruction queue. During processing, whenever the instruction corresponding to the instruction entry in the internal storage module 12 is executed, it will send the entry identifier of the first idle entry to the instruction input module so that the instruction input module can start reading the instruction again.

[0051] In some possible implementations, during each instruction read process, the instruction input module reads the unexecuted target instruction from the first instruction queue and / or the second instruction queue based on the entry identifier of the first free entry among multiple instruction entries in the internal storage module and the instruction category of the instruction in the non-free second entry; and stores the instruction information of the target instruction into the first entry.

[0052] The process includes: if the instructions in the second entry include instructions of the first category, reading a first number of target instructions from the second instruction queue according to a first number of the first entry; if the instructions in the second entry do not include instructions of the first category, reading a second number of target instructions from the first instruction queue according to the first number of the first entry, and reading a third number of target instructions from the second instruction queue, wherein the first number is the sum of the second number and the third number.

[0053] In other words, the instruction input module arbitrates the instruction category based on the second non-idle instruction entry in the internal storage module. If the second entry includes an instruction of the first category (i.e., a short loop instruction is already being executed), then the long loop instruction can be read, and the arbitration result is that the instruction of the second category is read. This improves the execution efficiency of long loop instructions.

[0054] In some possible implementations, if the second entry does not include instructions of the first category (i.e., there are no short loop instructions in execution), then instructions of the first category should be read first to ensure the parallel execution of short loop instructions. The arbitration result is that instructions of the first category are read first in this instance. In this way, parallel processing of both categories of instructions can be maintained.

[0055] In some possible implementations, the number of instructions to be read in this instance can be determined based on the first quantity of the first entry. If the second entry includes instructions of the first category, then the first quantity of target instructions are read from the second instruction queue; the reserved bits in each target instruction are deleted, and the remaining content is written as instruction information into the corresponding first entry.

[0056] In some possible implementations, if the second entry does not include instructions of the first category, then a second number of target instructions are read from the first instruction queue, and a third number of target instructions are read from the second instruction queue; the reserved bits in each target instruction are deleted, and the remaining content is written as instruction information into the corresponding first entry.

[0057] In some possible implementations, the first quantity is the sum of the second and third quantities. The second quantity is typically a preset value, such as 1 or 2, and the third quantity is the difference between the first and second quantities. In the example, the second entry does not include instructions of the first category, and the first entry has 5 items. Therefore, one instruction of the first category and four instructions of the second category can be read, resulting in 5 target instructions.

[0058] In this way, the instruction entries of the internal storage module can store two types of instructions at the same time, enabling parallel processing of different types of instructions and improving processing efficiency.

[0059] In some possible implementations, reading a first number of target instructions from the second instruction queue includes: starting from the target position in the second instruction queue, selecting a first number of instructions with an execution status bit of a first value as target instructions, and reading the target instructions, wherein the target position is the position after the last position of the previously selected instruction.

[0060] In other words, the instruction input module reads instructions in a polling manner, that is, it starts reading from the position after the last read in the instruction queue, and when it reaches the end of the instruction queue, it continues reading from the head of the instruction queue.

[0061] When reading a first number of target instructions from the second instruction queue, the position after the last selected instruction can be used as the target position; starting from the target position, a first number of instructions with the execution status bit set to the first value (not executed) are selected as target instructions and read.

[0062] Correspondingly, the processing methods for reading a second number of target instructions from the first instruction queue and a third number of target instructions from the second instruction queue are the same as those described above, and will not be repeated here.

[0063] In this way, unexecuted instructions can be selected by polling, reducing the number of instructions that fail to execute multiple times and improving the overall execution efficiency of instructions.

[0064] In some possible implementations, the internal storage module 12 is configured to send the entry identifier of the first entry to the instruction execution module when the instruction information of the target instruction is stored in the first entry, so that the instruction execution module initiates a request to read the instruction information of the target instruction.

[0065] In other words, after the instruction information of the target instruction is stored in the first entry of the internal storage module 12, it notifies the instruction execution module 13 to read the data. After receiving the notification from the internal storage module 12, the instruction execution module 13 can send a read request for the instruction information of the target instruction to the internal storage module 12, and the read request includes an entry identifier; in response to the read request, the internal storage module 12 sends the instruction information of the target instruction in the corresponding first entry to the instruction execution module 13; the instruction execution module 13 parses the received instruction information and determines the instruction category according to the instruction category flag in the instruction information; and executes the target instruction according to the instruction category, such as performing corresponding data transfer or data comparison.

[0066] In some possible implementations, when the target instruction is of the first category, the instruction information includes the amount of data to be transferred, the first source address and the destination address of the data to be transferred, and may also include information such as instruction identifier, entry identifier, and address translation page table identifier ID, etc. This disclosure does not limit this.

[0067] When the target instruction is of the first category, the instruction execution module executes the target instruction according to the instruction category of the target instruction, including: determining at least one first read request of the target instruction based on the data volume of the data to be transferred, the first source address, and the preset data volume of the data read request, and sending the first read request respectively; when the return data of the first read request is received, caching the return data; and when the cached return data is the complete data to be transferred, writing the data to be transferred to the destination address.

[0068] For example, for any target instruction, the instruction execution module 13 parses the received instruction information. If the instruction category flag indicates that the target instruction is a first-category instruction, i.e., a DMA instruction, then data can be read according to the source address and data volume. Specifically, based on the data volume to be transferred, the first source address, and the preset data volume of the data read request, at least one first read request for the target instruction can be determined.

[0069] In the example, using the AXI interface, the maximum data size for each data transfer instruction is 512 bytes, which can be divided into 8 first read requests, meaning 8 read requests can be considered as incomplete transactions. The default data size for each read request is 64 bytes, meaning each first read request transfers 64 bytes, sent over 4 time ticks, each time tick being 16 bytes (128 bits). Each time tick corresponds to one clock cycle. Thus, the 512 bytes of data to be transferred require a total of 32 time ticks.

[0070] In this way, based on the amount of data to be transferred, the first source address, and the preset data amount of the data read request, at least one first read request of the target instruction can be determined. For example, if the amount of data to be transferred is 256 bytes and the preset data amount of the data read request is 64 bytes, then four first read requests can be determined; and based on the first source address, the request addresses of the four first read requests are determined respectively. Then, each first read request is sent.

[0071] In some possible implementations, when the instruction execution module receives the return data of the first read request, it can cache the return data in the cache space (DATA_SRAM) inside the instruction execution module. The size of the cache space can be 128 bits × 32 so as to be able to accommodate the largest size of data to be transferred.

[0072] It should be understood that those skilled in the art can set the maximum amount of data to be transferred and the preset amount of data for data reading requests based on actual conditions such as interface type, and this disclosure does not impose any restrictions on this.

[0073] In some possible implementations, when the instruction execution module receives the return data of all first read requests, that is, when the cached return data is the complete data to be transferred, it can write the data to be transferred to the destination address through the AXI interface, thus completing the execution process of the data transfer instruction.

[0074] In some possible implementations, after receiving a valid write response from the AXI interface and confirming that no errors have occurred, the instruction execution module sends the interrupt information and entry identifier of the target instruction to the instruction input module to indicate that the target instruction has been executed. Furthermore, the instruction execution module can also send the entry identifier to the internal storage module, causing the internal storage module to set the corresponding entry to free for reading subsequent instructions.

[0075] In this way, data transfer instructions can be executed, meeting the needs of high-throughput, large-scale data transfer and improving execution efficiency.

[0076] In some possible implementations, when the target instruction is of the second category, the instruction information includes data comparison logic, the second source address of the current value and dependent values, and may also include instruction identifier, entry identifier, address translation page table identifier ID, etc. This disclosure does not limit this.

[0077] The data comparison logic may include: current value is greater than dependent value; current value is less than dependent value; current value is equal to dependent value; current value is greater than or equal to dependent value; current value is less than or equal to dependent value; current value is not equal to dependent value, etc. This disclosure does not limit the specific data comparison logic.

[0078] When the target instruction is of the second category, the instruction execution module executes the target instruction according to the instruction category of the target instruction, including: reading the current value according to the second source address of the current value; if the current value is read, reading the data comparison logic and dependency value of the target instruction; and comparing the current value and the dependency value according to the data comparison logic to obtain the execution result of the target instruction.

[0079] For example, for any target instruction, the instruction execution module 13 parses the received instruction information. If the instruction category flag indicates that the target instruction is a second-category instruction, i.e., a VCE instruction, the instruction execution module can send a read request based on the second source address of the current value to read the current value of the semaphore. After reading the current value, it reads the data comparison logic and dependency values ​​of the target instruction from the internal storage module. Based on the data comparison logic, it compares the current value and dependency values ​​to obtain the execution result of the target instruction. Then, it sends the execution result to the instruction input module 11. The execution result may include execution success or execution failure. If the execution is successful, a corresponding interrupt signal will be sent.

[0080] In some possible implementations, the instruction execution module may also send the entry identifier to the internal storage module so that the internal storage module sets the corresponding entry to free so that subsequent instructions can be read.

[0081] In this way, parallel processing of data comparison instructions in multiple first entries can be achieved, satisfying high-concurrency data comparison, realizing low-latency parallel processing, and improving the execution efficiency of this type of instruction.

[0082] In some possible implementations, the instruction execution module reads data from the internal storage module twice when executing second-category instructions. When multiple instructions are executed in parallel, there may be arbitration, in which case the second read takes precedence over the first read.

[0083] In some possible implementations, the internal storage module is configured to respond to the third read request if the received read request includes both a second read request for instruction information for the first target instruction and a third read request for data comparison logic and dependency values ​​for the second target instruction.

[0084] In other words, for the internal storage module, if the multiple read requests received simultaneously include a second read request for instruction information for the first target instruction and a third read request for data comparison logic and dependency values ​​for the second target instruction, the third read request can be responded to first, and the response information of the third read request can be sent to the instruction execution module so that the instruction execution module can complete the data comparison process; after the third read request is completed, the second read request is executed so that the instruction execution module can determine the instruction type and process it accordingly.

[0085] In this way, the second read can be prioritized to quickly complete the processing of instructions in progress, thereby improving the overall instruction processing efficiency of the system.

[0086] In some possible implementations, the instruction input module is further configured to update the execution status bit of the target instruction in the register control module from a first value to a second value upon receiving an interrupt signal for the target instruction.

[0087] In other words, if the instruction input module receives an interrupt signal for the target instruction, it can update the execution status bit of the target instruction in the register control module from the first value to the second value, for example, from 0 to 1, indicating that the target instruction has been executed and will be skipped during the next instruction selection poll. Conversely, if the module receives information that the target instruction has failed to execute, it will not update the value of the corresponding execution status bit, or it will set the corresponding execution status bit to the first value, indicating that the target instruction has not been executed or has failed to execute, and will continue to select the target instruction during the next instruction selection poll.

[0088] In this way, the execution state can be controlled, thereby reducing the occurrence of duplicate instruction selection and omission, and making the processing logic more complete.

[0089] In some possible implementations, the register control module is configured to report an interrupt signal for the target instruction when the execution status bit of the target instruction is updated from a first value to a second value.

[0090] In other words, if the execution status bit of the target instruction is updated from the first value to the second value, indicating that the target instruction has been executed, the register control module can report the interrupt signal of the target instruction to the firmware, informing the firmware that the target instruction has been executed and enabling the firmware to control the CPU to perform subsequent processing, such as mathematical operations or graphics processing based on the transferred data.

[0091] In this way, instruction interruptions can be reported so that subsequent processing can be carried out.

[0092] In some possible implementations, the instruction input module is also configured to stop reading instructions when the execution status bit of the instruction in both the first instruction queue and the second instruction queue is the second value.

[0093] In other words, if the execution status bits of both instructions in the first and second instruction queues of the register control module are at the second value, meaning that all instructions in both queues have been executed, the instruction input module does not need to continue polling to select instructions. In this case, the instruction input module can also stop reading instructions. This allows the hardware to automatically exit the loop without software intervention, improving system efficiency.

[0094] The data processing apparatus according to embodiments of this disclosure can distinguish and process different types of instructions, such as short-cycle VCE instructions and long-cycle DMA instructions, through dual circular queues, and simultaneously schedule different types of instruction queues to improve overall processing efficiency; it can arbitrate the priority of instructions in different instruction queues and poll to select instructions through the instruction input module to avoid instruction execution conflicts and resource conflicts; and it can automatically control the start, exit and status update of instruction queues through hardware to reduce software intervention.

[0095] In related technologies, there are no dedicated hardware resources for polling and comparing semaphores. Software control is required to initiate data reading and comparison. This only allows for sequential operations and cannot initiate a large number of data reading operations in parallel, resulting in low efficiency. Furthermore, it is similar to the on-chip CPU's requirement for a DMA engine, which can lead to some functional redundancy.

[0096] The data processing apparatus according to the embodiments of this disclosure can implement concurrent control based on hardware, and execute instructions with different lifecycles simultaneously. VCE instructions and DMA instructions can be executed out of order and concurrently. It is also highly scalable and supports a variety of instructions. For example, VCE instructions can support more complex comparison logic, or DMA instructions can move larger amounts of data. It can also support cyclic self-starting and exiting in hardware, realize automated control, reduce the software overhead and burden on the host side.

[0097] The data processing apparatus according to embodiments of this disclosure can also support concurrent processing of multiple incomplete transactions through identifier maintenance, thereby improving data read / write throughput and data comparison efficiency. According to embodiments of this disclosure, the process of on-chip CPU reading and comparing memory values ​​can be accelerated and merged with DMA functionality, avoiding module redundancy and improving efficiency.

[0098] Figure 2 A flowchart illustrating a data processing method provided in an embodiment of this disclosure. (Refer to...) Figure 2 The method includes the following steps S21-S23.

[0099] In step S21, based on the entry identifier of the first idle entry among multiple instruction entries and the instruction category of the instructions in the non-idle second entry, unexecuted target instructions are read from the first instruction queue and / or the second instruction queue; and the instruction information of the target instructions is stored in the first entry. The first instruction queue includes instructions of the first category with an execution count of 1, and the second instruction queue includes instructions of the second category with an execution count greater than or equal to 1.

[0100] In step S22, the target instruction is executed according to its instruction category to obtain the execution result of the target instruction.

[0101] In step S23, if the execution result of the target instruction is successful, an interrupt signal for the target instruction is reported.

[0102] In some possible implementations, the method further includes: upon receiving an interrupt signal for the target instruction, updating the execution status bit of the target instruction from a first value to a second value, wherein the first value indicates that the instruction has not been executed and the second value indicates that the instruction has been executed.

[0103] In some possible implementations, step S21 includes: if the instructions in the second entry include instructions of the first category, reading a first number of target instructions from the second instruction queue according to a first number of the first entry; if the instructions in the second entry do not include instructions of the first category, reading a second number of target instructions from the first instruction queue according to the first number of the first entry, and reading a third number of target instructions from the second instruction queue, wherein the first number is the sum of the second number and the third number.

[0104] In some possible implementations, step S21 includes: starting from the target position of the second instruction queue, selecting the first number of instructions with the execution status bit set to the first value as target instructions, and reading the target instructions, wherein the target position is the position after the last position of the previously selected instruction.

[0105] In some possible implementations, when the target instruction is of the first category, the instruction information includes the data volume of the data to be transferred, the first source address of the data to be transferred, and the destination address. Step S22 includes: determining at least one first read request of the target instruction based on the data volume of the data to be transferred, the first source address, and the preset data volume of the data read request, and sending the first read request respectively; when the return data of the first read request is received, caching the return data; and when the cached return data is the complete data to be transferred, writing the data to be transferred to the destination address.

[0106] In some possible implementations, when the target instruction is of the second category, the instruction information includes data comparison logic, the second source address of the current value, and dependent values. Step S22 includes: reading the current value based on the second source address of the current value; if the current value is read, reading the data comparison logic and dependent values ​​of the target instruction; and comparing the current value and the dependent values ​​based on the data comparison logic to obtain the execution result of the target instruction.

[0107] In some possible implementations, the method further includes: sending the entry identifier of the first entry when the instruction information of the target instruction is stored in the first entry; and responding to the third read request when the received read request includes both a second read request for instruction information of the first target instruction and a third read request for data comparison logic and dependency values ​​of the second target instruction.

[0108] In some possible implementations, the method further includes: when there is a new instruction in the first instruction queue and / or the second instruction queue, setting an execution status bit corresponding to the new instruction, and setting the execution status bit to the first value.

[0109] In some possible implementations, the method further includes: reporting an interrupt signal for the target instruction when the execution status bit of the target instruction is updated from a first value to a second value.

[0110] In some possible implementations, the method further includes: stopping instruction reading when the execution status bits of instructions in both the first instruction queue and the second instruction queue are both of the second value.

[0111] In some possible implementations, the instructions of the first category include data transfer instructions based on direct memory access (DMA); the instructions of the second category include data comparison instructions based on the data comparison unit (VCE).

[0112] It is understood that the various method embodiments mentioned above in this disclosure can be combined with each other to form combined embodiments without violating the principle and logic. Due to space limitations, this disclosure will not elaborate further. Those skilled in the art will understand that in the above methods of specific implementation, the specific execution order of each step should be determined by its function and possible internal logic.

[0113] Figure 3 This is a block diagram of an electronic device provided in an embodiment of the present disclosure.

[0114] Reference Figure 3 This disclosure provides an electronic device comprising: at least one processor 701; at least one memory 702; and one or more I / O interfaces 703 connected between the processor 701 and the memory 702; wherein the memory 702 stores one or more computer programs executable by the at least one processor 701, the one or more computer programs being executed by the at least one processor 701 to enable the at least one processor 701 to include the aforementioned data processing apparatus or to execute the aforementioned data processing method.

[0115] This disclosure also provides a computer-readable storage medium storing a computer program thereon, wherein the computer program, when executed by a processor, implements the data processing method described above. The computer-readable storage medium may be volatile or non-volatile.

[0116] This disclosure also provides a computer program product, including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, wherein when the computer-readable code is run in a processor of an electronic device, the processor in the electronic device performs the above-described data processing method.

[0117] Those skilled in the art will understand that all or some of the steps, systems, and apparatuses disclosed above, and their functional modules / units, can be implemented as software, firmware, hardware, or suitable combinations thereof. In hardware implementations, the division between functional modules / units mentioned above does not necessarily correspond to the division of physical components; for example, a physical component may have multiple functions, or a function or step may be performed collaboratively by several physical components. Some or all physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit (ASIC). Such software can be distributed on a computer-readable storage medium, which may include computer storage media (or non-transitory media) and communication media (or transient media).

[0118] Example embodiments have been disclosed herein, and while specific terminology has been used, it is for illustrative purposes only and should be construed as such, and is not intended to be limiting. In some instances, it will be apparent to those skilled in the art that features, characteristics, and / or elements described in connection with particular embodiments may be used alone, or in combination with features, characteristics, and / or elements described in connection with other embodiments, unless otherwise expressly indicated. Therefore, those skilled in the art will understand that various changes in form and detail may be made without departing from the scope of this disclosure as set forth by the appended claims.

Claims

1. A data processing apparatus, characterized in that, include: The module consists of an instruction input module, an internal storage module, and an instruction execution module. The instruction input module is configured to: read unexecuted target instructions from a first instruction queue and / or a second instruction queue based on the entry identifier of a free first entry among multiple instruction entries in the internal storage module and the instruction category of instructions in a non-free second entry; and store the instruction information of the target instructions in the first entry; wherein the first instruction queue includes instructions of a first category with an instruction execution count of 1, and the second instruction queue includes instructions of a second category with an instruction execution count greater than or equal to 1; if the instructions in the second entry do not include instructions of the first category, the target instruction includes at least one instruction of the first category; The instruction execution module is configured to: execute the target instruction according to its instruction category when the instruction information of the target instruction is stored in the first entry; and send an interrupt signal of the target instruction to the instruction input module when the execution result of the target instruction is successful.

2. The apparatus according to claim 1, characterized in that, The device further includes a register control module, and the instruction input module is further configured to: Upon receiving an interrupt signal for the target instruction, the execution status bit of the target instruction in the register control module is updated from a first value to a second value. The first value indicates that the instruction has not been executed, and the second value indicates that the instruction has been executed.

3. The apparatus according to claim 2, characterized in that, The instruction input module reads unexecuted target instructions from the first instruction queue and / or the second instruction queue based on the entry identifier of the first free entry among multiple instruction entries in the internal storage module and the instruction category of the instructions in the non-free second entry, including: If the instruction in the second entry includes an instruction of the first category, a first number of target instructions are read from the second instruction queue according to the first number of the first entry; If the instructions in the second entry do not include instructions of the first category, a second number of target instructions are read from the first instruction queue and a third number of target instructions are read from the second instruction queue according to the first number of the first entry, wherein the first number is the sum of the second number and the third number.

4. The apparatus according to claim 3, characterized in that, The step of reading a first number of target instructions from the second instruction queue includes: Starting from the target position in the second instruction queue, select the first number of instructions with the execution status bit set to the first value as target instructions, and read the target instructions. The target position is the position after the last position of the previously selected instruction.

5. The apparatus according to claim 1, characterized in that, When the target instruction is of the first category, the instruction information includes the amount of data to be transferred, the first source address of the data to be transferred, and the destination address. The instruction execution module executes the target instruction according to its instruction category, including: Based on the amount of data to be transferred, the first source address, and the preset amount of data for the data read request, at least one first read request for the target instruction is determined, and the first read request is sent respectively. Upon receiving the return data from the first read request, cache the return data; If the cached return data is the complete data to be transferred, the data to be transferred is written to the destination address.

6. The apparatus according to claim 1, characterized in that, When the target instruction is of the second category, the instruction information includes data comparison logic, the second source address of the current value, and dependent values. The instruction execution module executes the target instruction according to its instruction category, including: Read the current value based on the second source address of the current value; If the current value is read, the data comparison logic and dependency values ​​of the target instruction are read; According to the data comparison logic, the current value and the dependency value are compared to obtain the execution result of the target instruction.

7. The apparatus according to claim 6, characterized in that, The internal storage module is configured as follows: If the instruction information of the target instruction is stored in the first entry, the entry identifier of the first entry is sent to the instruction execution module so that the instruction execution module initiates a request to read the instruction information of the target instruction. If the received read request includes both a second read request for instruction information for the first target instruction and a third read request for data comparison logic and dependency values ​​for the second target instruction, the third read request shall be responded to.

8. The apparatus according to claim 2, characterized in that, The instruction input module is further configured to: when there is a new instruction in the first instruction queue and / or the second instruction queue, set an execution status bit corresponding to the new instruction in the register control module, and set the execution status bit to the first value.

9. The apparatus according to claim 2, characterized in that, The register control module is configured to report an interrupt signal for the target instruction when the execution status bit of the target instruction is updated from a first value to a second value.

10. The apparatus according to claim 3, characterized in that, The instruction input module is further configured to stop reading instructions when the execution status bit of the instructions in both the first instruction queue and the second instruction queue is a second value.

11. The apparatus according to claim 1, characterized in that, The first category of instructions includes data transfer instructions based on direct memory access (DMA); the second category of instructions includes data comparison instructions based on the data comparison unit (VCE).

12. A data processing method, characterized in that, include: Based on the entry identifier of the first idle entry among multiple instruction entries and the instruction category of the instruction in the non-idle second entry, read the unexecuted target instruction from the first instruction queue and / or the second instruction queue; and store the instruction information of the target instruction into the first entry; Wherein, the first instruction queue includes instructions of the first category with an instruction execution count of 1, and the second instruction queue includes instructions of the second category with an instruction execution count greater than or equal to 1; if the instructions in the second entry do not include instructions of the first category, the target instruction includes at least one instruction of the first category; The target instruction is executed according to its instruction category to obtain the execution result of the target instruction; If the execution result of the target instruction is successful, an interrupt signal for the target instruction is reported.

13. An electronic device, characterized in that, include: The data processing apparatus as described in any one of claims 1-11.

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