An electronic memory cell, array and method of fabricating an electronic device

Abstract

The application discloses an electronic storage computing unit, an array and an electronic component preparation method, which comprise a storage summation unit, a computing unit, a first scanning line, a first signal line and a second signal line; the control end of the storage summation unit is connected with the first scanning line, the first input end is connected with the first signal line, and the second input end is connected with the second signal line, so as to read a second electric signal on the second signal line; the first scanning line controls a first electric signal to be transmitted to the first port of the storage summation unit through the first signal line; the storage summation unit realizes addition of the first electric signal and the second electric signal, and transmits an addition result to the computing unit, so as to realize multiplication of the second electric signal and the first electric signal. The single-gate neural network structure provided by the application avoids dependence on a double-gate structure in traditional design, and significantly improves the expansibility of the circuit.

Description

Technical Field

[0001] This invention belongs to the field of electronic circuit technology, and particularly relates to an electronic storage computing unit, array, and method for preparing electronic components. Background Technology

[0002] Artificial neural networks (ANNs) are biomimetic parallel signal processing systems inspired by the human brain, designed to process massive amounts of data by mimicking the brain's adaptability, interconnectivity, and noise tolerance. However, most widely used general-purpose ANN systems currently operate on computers with the von Neumann architecture, which suffers from low computational efficiency, high power consumption, and difficulty in realistically replicating the complex connectivity and dynamic adjustment of neuron weights in biological neural networks. To overcome these challenges, researchers have begun to focus on non-traditional computing platforms, particularly analog computing circuits with the potential to perform neural network tasks. These innovative circuit designs do not rely on the traditional von Neumann model but instead employ physical forms closer to biological neural networks, thus providing significant improvements in the ability to simulate animal neural networks. These advanced circuit designs utilize novel technologies such as memristors, optical computing elements, and special semiconductor materials to provide both data storage and computational capabilities, thereby avoiding frequent data transfers between memory and computing units.

[0003] Figure 1 An artificial neural network unit based on a dual-gate thin-film transistor is demonstrated, where the dual-gate transistor W11 is the computation unit, and capacitor C11 and switch S11 constitute the storage unit. During circuit operation, transistor S11 is turned on via L50; a weight signal is written via L10 and stored on capacitor C11; a data signal is written via L40; and a current signal is read from L30 as the output signal. The additional gate of the dual-gate transistor can modulate the threshold voltage of the transistor; assuming the voltage on one gate is... The voltage on the other gate is The current flowing through the transistor is When a transistor operates in the saturation region and its source is grounded, the current flowing through the transistor... Therefore, when weights and data are applied to the two gates of a dual-gate transistor, respectively, the transistor can add the two together, and the output current can contain the information of their multiplication. However, the fabrication of dual-gate transistors requires special process requirements, mostly relying on thin-film transistor technology, and using organic semiconductors, low-temperature polycrystalline silicon, amorphous silicon, or metal oxides. Dual-gate transistors cannot be fabricated in traditional silicon-based complementary metal-oxide-semiconductor (CMOS) processes, greatly limiting the application scenarios of artificial neural network units. Summary of the Invention

[0004] Purpose of the invention: In order to solve the problems existing in the prior art, the present invention provides an electronic storage computing unit, array and electronic components.

[0005] Technical solution: This invention discloses an electronic storage computing unit, including a storage summation unit, a computing unit, a first scan line, a first signal line, and a second signal line;

[0006] The control terminal of the storage summation unit is connected to the first scan line, the first input terminal is connected to the first signal line, and the second input terminal is connected to the second signal line. It is used to read the second electrical signal on the second signal line. The first scan line controls the first electrical signal to be transmitted to the first port of the storage summation unit through the first signal line. The storage summation unit realizes the addition of the first electrical signal and the second electrical signal, and transmits the addition result to the calculation unit to realize the multiplication of the second electrical signal and the first electrical signal.

[0007] Furthermore, the storage summation unit includes a storage component and a first switching component;

[0008] The input terminal of the first switching component is connected to the first signal line, the output terminal of the first switching component is connected to one end of the storage component and the computing unit, the control terminal of the first switching component is connected to the first scan line, and the other end of the storage component is connected to the second signal line.

[0009] Furthermore, the first switching component includes a first field-effect transistor, and the storage component includes a capacitor; the computing unit includes a second field-effect transistor, the gate of the first field-effect transistor serves as a control terminal, the drain serves as a first input terminal of the storage summation unit, the source is connected to one end of the capacitor, and the other end of the capacitor serves as a second input terminal of the storage summation unit; the gate of the second field-effect transistor is connected to the storage summation unit, the drain is connected to the power supply, and the source serves as an output port.

[0010] Furthermore, both the first and second field-effect transistors are single-gate transistors.

[0011] Furthermore, both the first and second field-effect transistors are fabricated using thin-film transistor technology, and the semiconductor materials used in the devices are organic semiconductors, amorphous silicon, low-temperature polycrystalline silicon, or metal oxides.

[0012] Furthermore, both the first and second field-effect transistors are silicon-based field-effect transistors.

[0013] Furthermore, the first field-effect transistor is a low-leakage metal-oxide thin-film transistor; the second field-effect transistor is a high-mobility silicon-based field-effect transistor; the first field-effect transistor, the second field-effect transistor, and the capacitor are monolithically integrated.

[0014] A method for fabricating electronic components in an electronic storage computing unit, the method comprising:

[0015] A first insulating layer is formed on a substrate; the substrate is a P-type or N-type silicon substrate;

[0016] A second insulating layer is formed in the middle region of a substrate that does not have a first insulating layer.

[0017] Conductive wells are formed by ion implantation on a substrate without a first insulating layer and a second insulating layer.

[0018] The first conductor is deposited in the second insulating layer;

[0019] A third insulating layer is deposited on the first insulating layer and the first conductor;

[0020] A second conductor is deposited on the third insulating layer, the conductive well, and the first conductor. The second conductor contacts the first conductor and the conductive well to form the source, gate, and drain of the second field-effect transistor.

[0021] Two third conductors are deposited on the third insulating layer, with one third conductor serving as the gate of the first field-effect transistor and the other third conductor serving as the electrode of the capacitor.

[0022] A fourth insulating layer is deposited on the third insulating layer and the third conductor;

[0023] Two first semiconductors are deposited on the fourth insulating layer;

[0024] A fifth insulating layer is deposited on the fourth insulating layer and the first semiconductor, thereby exposing a portion of the first semiconductor.

[0025] Two third conductors are deposited on one first semiconductor exposed region as the source and drain of the first field-effect transistor; a third conductor is deposited on another first semiconductor exposed region as the top layer of the capacitor.

[0026] An array in an electronic storage computing unit includes M*N electronic storage computing units;

[0027] The control terminal of the storage summation unit in the electronic storage computing unit of row i and column j is connected to the first scan line of row i; the first input terminal of the storage summation unit in all electronic storage computing units of column j is connected to the first signal line of column j; the second input terminal of the storage summation unit in all electronic storage computing units of column j is connected to the second signal line of column j; i=1,2,…,M, j=1,2,…,N;

[0028] First, the first scan line of the first row is used to enable the first signal reading function of all storage summation units in the first row. The storage summation unit in the j-th electronic storage calculation unit of the first row reads the first electrical signal on the first signal line of the j-th column. When all storage summation units in the first row have read and stored the corresponding first electrical signal, the first scan line of the first row is used to disable the first signal reading function of all storage summation units in the first row. Then, the first scan line of the second row is used to enable the first signal reading function of all storage summation units in the second row, until all storage summation units in all rows have read and stored the corresponding first electrical signal. The first electrical signal read by each storage summation unit can be different. Then, the second electrical signal is transmitted to the storage summation unit in the storage calculation unit of the first column through the second signal line of the first column, and the calculation unit outputs the calculation result. Then, the second electrical signal is transmitted to the storage summation unit in the storage calculation unit of the second column through the second signal line of the second column, thus completing the calculation result in sequence.

[0029] Beneficial effects:

[0030] 1. The single-gate neural network structure proposed in this invention avoids the dependence on dual-gate structures in traditional designs, significantly improving circuit scalability. Since it eliminates the need for thin-film transistor (TFT) technology (which dual-gate structures require), it overcomes the limitations of low-mobility materials such as metal oxides, amorphous silicon, and polycrystalline silicon, and is directly compatible with mainstream silicon-based CMOS processes, thus achieving higher circuit operating speeds. It can be directly integrated with existing large-scale integrated circuit production lines, shortening the process development cycle. The single-gate structure reduces gate stacking and alignment processes, lowering process complexity and improving device manufacturing yield (dual-gate structures have large parasitic capacitance, leading to slow device speeds). Simplified structure reduces device parasitic capacitance, optimizes circuit power consumption, and improves energy efficiency.

[0031] 2. The number of photolithography steps is reduced, and the number of photomasks is reduced accordingly, which effectively reduces manufacturing costs.

[0032] 3. Due to the reduction in the number of dielectric interfaces, the risk of interface defects and stress mismatch is reduced, thereby enhancing the reliability and thermal stability of the device. Attached Figure Description

[0033] Figure 1 This refers to the artificial neural network unit in existing technologies.

[0034] Figure 2 This is the artificial neural network unit of the present invention.

[0035] Figure 3 This invention provides a circuit implementation method for an artificial neural network unit.

[0036] Figure 4This invention describes the working method of the artificial neural network unit proposed in this invention.

[0037] Figure 5 This is a schematic diagram of a 3×3 array of artificial neural network units according to the present invention.

[0038] Figure 6 This is a cross-sectional view of the electronic components of the present invention. Detailed Implementation

[0039] The accompanying drawings, which form part of this invention, are used to provide a further understanding of the invention. The illustrative embodiments of the invention and their descriptions are used to explain the invention and do not constitute an improper limitation of the invention.

[0040] This invention proposes a novel artificial neural network computing unit, such as... Figure 2 As shown, the system includes a summation storage unit 101 and a calculation unit 102. The summation storage unit receives two input signals, which are input through a weight voltage line 105 and a data voltage line 106, respectively, for writing the weight voltage signal and the data voltage signal. The weight voltage line 105 is controlled by a scan signal line 104. The output signal processed by the calculation unit 102 is output through a signal line 103. The storage summation unit is responsible for storing the weight signal and adding the weight to the data voltage. The calculation unit controls the magnitude of the output current by receiving the voltage signal from the storage summation unit.

[0041] Figure 3 This paper demonstrates a circuit implementation method for an artificial neural network computing unit. In the circuit, capacitor 207 and switching transistor 206 constitute a summing and storage unit, responsible for storing the weight voltage WT and summing the weight voltage and data voltage DT. A single-gate thin-film transistor 206 is used as an electronic switch to control signal flow. A single-gate transistor 208 is used as a computing unit to multiply the weight voltage and data voltage. A scan signal line 202 controls the switching state of the connected switching transistor 206. This switching control mechanism ensures that the signal on the weight signal line 204 can be stored in capacitor 207 under correct timing conditions. The data signal line 205 is responsible for writing the data signal into capacitor 207. The gate of the single-gate transistor 208 is connected to the storage capacitor 207, while its source and drain are connected to power supply port 201 and signal output port 203, respectively. The output signal of the computing unit is the drain current of transistor 208.

[0042] The specific process of this embodiment is as follows:

[0043] The data signal line provides the data signal DT to 205;

[0044] Weight signal line 204 provides the weight signal WT;

[0045] The real-phase addition DT+WT is achieved through the bootstrap effect of capacitor 207;

[0046] At this time, the gate voltage of transistor 208 is the sum of DT and WT;

[0047] The output current of transistor 208, i.e., the current I on transistor 203, is proportional to... The current after taking the square root of 203 contains the product of DT and WT, thus achieving multiplication.

[0048] like Figure 4 As shown, the specific operating mode of this implementation circuit is as follows: the circuit operation is divided into two cycles: a weight writing cycle (writing WT) and a data and weight summation cycle (summation). HV refers to the voltage value that allows the switching transistor 206 to turn on, and LV refers to the voltage value that allows the transistor 206 to turn off. During the convolution kernel writing cycle, transistor 206 is turned on via control signal line 202. The weight signal WT is written to one side of the capacitor via weight signal line 204; a 0V voltage signal is written to the other side of the capacitor via data signal line 205, at which point the voltage difference across the capacitor is WT. During the summation cycle, transistor 206 is turned off via control signal line 202. The data voltage DT is written to the other side of the capacitor via data signal line 205. Through the capacitor bootstrap effect, the voltage on the gate of transistor 208 becomes WT + DT, realizing the summation of weight and data. When transistor 208 operates in the saturation region, the current read on line 203 contains the information of WT multiplied by DT.

[0049] In the M×N array constructed by the artificial neural network computing units of this embodiment, the control terminal of the storage summation unit in the electronic storage computing unit in the i-th row and j-th column is connected to the first scan line in the i-th row; the first input terminal of the storage summation unit in all electronic storage computing units in the j-th column is connected to the first signal line in the j-th column; the second input terminal of the storage summation unit in all electronic storage computing units in the j-th column is connected to the second signal line in the j-th column; i=1,2,…,M, j=1,2,…,N;

[0050] The specific working mode is as follows: First, the first scan line of the first row is used to enable the first signal reading function of all storage summation units in the first row. The storage summation unit in the j-th electronic storage calculation unit of the first row reads the first electrical signal on the first signal line of the j-th column. When all storage summation units in the first row have read and stored the corresponding first electrical signal, the first scan line of the first row is used to disable the first signal reading function of all storage summation units in the first row. Then, the first scan line of the second row is used to enable the first signal reading function of all storage summation units in the second row, until all storage summation units in all rows have read and stored the corresponding first electrical signal. The first electrical signal read by each storage summation unit can be different. Then, the second electrical signal is transmitted to the storage summation unit in the storage calculation unit of the first column through the second signal line of the first column, and the calculation unit outputs the calculation result. Then, the second electrical signal is transmitted to the storage summation unit in the storage calculation unit of the second column through the second signal line of the second column, thereby completing the calculation result in sequence.

[0051] Figure 5 This is a schematic diagram of the 3×3 array composed of artificial neural network computing units in this embodiment. The power signal lines in each row are connected together and labeled 301, 302, and 303. The scan signal lines in each row are labeled 304, 305, and 306. The output signals in each column are connected and labeled 307, 308, and 309. Similarly, the weight signal input lines associated with each column are labeled 310, 311, and 312. Furthermore, the data signal input lines within each column are independently combined and labeled 314, 315, and 316. The array operates as follows:

[0052] When the first row is working, the weights for the first row are first loaded onto signal lines 310, 311, and 312. Simultaneously, data lines 314, 315, and 316 remain at 0V. Then, transistor 304 turns on the first row transistor, and the weights are written to one end of the capacitor; after the weights are written, transistor 304 turns off the first row transistor. Following this method, the weight signals are further stored in the second and third rows. After storing the weight signals (the weights written to each cell can be different), data signals are written to the first column, summed, multiplied, and output from line 307. Then, the second column (output from 308) and the third column (output from 309) are calculated sequentially.

[0053] Because the computing unit has changed from a dual-gate transistor to a single-gate transistor, more options are available for the fabrication process of the neural network. Figure 3For example, the first type is: both switch 206 and computing transistor 208 in the design use thin-film transistor technology, and the semiconductor material of the device can be organic semiconductor, amorphous silicon, low-temperature polycrystalline silicon, or metal oxide. The second type is: both switch 206 and computing transistor 208 in the design use silicon-based field-effect transistors. The third type is: switch 206 uses a low-leakage metal oxide thin-film transistor, while computing transistor 208 is a high-mobility silicon-based field-effect transistor.

[0054] The third method implements two transistors formed on a single substrate, specifically as follows: Figure 6 As shown:

[0055] Figure 6 The left side shows a silicon-based field-effect transistor, while the right side shows a thin-film transistor and a capacitor. Figure 6 A cross-sectional view of the third implementation method is shown, which can monolithically integrate two types of transistors and capacitors. From left to right, the red box represents a silicon-based field-effect transistor as a computing transistor, the green box represents a thin-film transistor as a switching transistor, and the orange box represents a storage capacitor. The computing transistor comprises a P-type or N-type silicon substrate 401 (the substrate is semiconductor); a first insulating layer 402; a second insulating layer 403; a first conductor 404; heavily doped P-type or N-type transistors 405A and 405B; a third insulating layer 406; and second conductors 407A, 407B, and 407C. The switching transistor includes a third conductor 409A; a fourth insulating layer 410; a first semiconductor layer 411A; a fifth insulating layer 412; and fourth conductors 413A and 413B. Semiconductor layer 411A is the gate of the switching transistor, and 413A and 413B are the source and drain of the switching transistor. The capacitor includes a fourth conductor 413C (as the top electrode of the capacitor), a fifth insulating layer 412, a fourth insulating layer 410 (as the dielectric layer of the capacitor), and a third conductor 409B (as the bottom electrode layer of the capacitor).

[0056] The specific method for fabricating the transistor in the third implementation scenario is as follows:

[0057] Substrate 401 is generated, which is a silicon wafer, constituting a semiconductor;

[0058] The first insulating layer 402 is patterned and is formed by the reaction of an external gas with the substrate. The portion without the first insulating layer is where the first type of electronic component is located.

[0059] The patterned second insulating layer 403 is generated by the reaction of external gas with the substrate.

[0060] The first conductor 404 is patterned, formed by deposition and contact with the second insulating layer.

[0061] The heavily doped conductive well 405 is formed by ion implantation, and the portion of the conductive well not covered by the second insulating layer and the first conductor is formed by ion implantation.

[0062] The third insulating layer 406 is graphically represented. The insulating layer is obtained by deposition.

[0063] A patterned second conductor 407, obtained by deposition, is in contact with the first conductor and the conductive well.

[0064] The channel semiconductor material used in the first type of electronic component is silicon.

[0065] The second type of electronic component includes,

[0066] A third conductor 409 is patterned on a third insulating layer, the conductor being obtained by deposition.

[0067] The fourth insulator 410 is graphically represented, and the fourth insulator is obtained by deposition.

[0068] The first semiconductor 411 is patterned and obtained by deposition. The semiconductor can be metal oxide, amorphous silicon, or low-temperature polycrystalline silicon.

[0069] The fifth insulator 412 is graphically represented and is obtained by deposition.

[0070] A patterned third conductor is in contact with the exposed portion of the first semiconductor.

[0071] It should also be noted that the various specific technical features described in the above embodiments can be combined in any suitable manner without contradiction. To avoid unnecessary repetition, the present invention will not describe the various possible combinations separately.

Claims

1. An electronic storage computing unit, characterized in that, It includes a storage summation unit, a calculation unit, a first scan line, a first signal line, and a second signal line; The control terminal of the storage summation unit is connected to the first scan line, the first input terminal is connected to the first signal line, and the second input terminal is connected to the second signal line. It is used to read the second electrical signal on the second signal line. The first scan line controls the first electrical signal to be transmitted to the first port of the storage summation unit through the first signal line. The storage summation unit adds the first electrical signal and the second electrical signal, and transmits the addition result to the calculation unit to multiply the second electrical signal and the first electrical signal; the storage summation unit includes a storage component and a first switching component; The input terminal of the first switching component is connected to the first signal line, the output terminal of the first switching component is connected to one end of the storage component and the computing unit, the control terminal of the first switching component is connected to the first scan line, and the other end of the storage component is connected to the second signal line. The first switching component includes a first field-effect transistor, and the storage component includes a capacitor; the computing unit includes a second field-effect transistor, the gate of the first field-effect transistor serves as a control terminal, the drain serves as a first input terminal of the storage summation unit, the source is connected to one end of the capacitor, and the other end of the capacitor serves as a second input terminal of the storage summation unit; the gate of the second field-effect transistor is connected to the storage summation unit, the drain is connected to the power supply, and the source serves as an output port. Both the first and second field-effect transistors are single-gate transistors.

2. The electronic storage computing unit according to claim 1, characterized in that, Both the first and second field-effect transistors are fabricated using thin-film transistor technology, and the semiconductor materials used in the devices are organic semiconductors, amorphous silicon, low-temperature polycrystalline silicon, or metal oxides.

3. The electronic storage computing unit according to claim 1, characterized in that, Both the first and second field-effect transistors are silicon-based field-effect transistors.

4. The electronic storage computing unit according to claim 1, characterized in that, The first field-effect transistor is a low-leakage metal-oxide thin-film transistor; the second field-effect transistor is a high-mobility silicon-based field-effect transistor; the first field-effect transistor, the second field-effect transistor, and the capacitor are monolithically integrated.

5. A method for fabricating a transistor in an electronic storage computing unit according to any one of claims 1-4, characterized in that, The preparation method is as follows: A first insulating layer is formed on the substrate; The substrate is a P-type or N-type silicon substrate; A second insulating layer is formed in the middle region of a substrate that does not have a first insulating layer. Conductive wells are formed by ion implantation on a substrate without a first insulating layer and a second insulating layer. The first conductor is deposited in the second insulating layer; A third insulating layer is deposited on the first insulating layer and the first conductor; A second conductor is deposited on the third insulating layer, the conductive well, and the first conductor. The second conductor contacts the first conductor and the conductive well to form the source, gate, and drain of the second field-effect transistor. Two third conductors are deposited on the third insulating layer, with one third conductor serving as the gate of the first field-effect transistor and the other third conductor serving as the electrode of the capacitor. A fourth insulating layer is deposited on the third insulating layer and the third conductor; Two first semiconductors are deposited on the fourth insulating layer; A fifth insulating layer is deposited on the fourth insulating layer and the first semiconductor, thereby exposing a portion of the first semiconductor. Two third conductors are deposited on a first semiconductor exposed region to serve as the source and drain of the first field-effect transistor; A third conductor is deposited on another first semiconductor exposed area as the TOP layer of the capacitor.

6. The array in the electronic storage computing unit according to claim 1, characterized in that, It includes M*N electronic storage computing units; The control terminal of the storage summation unit in the electronic storage computing unit of row i and column j is connected to the first scan line of row i; the first input terminal of the storage summation unit in all electronic storage computing units of column j is connected to the first signal line of column j; the second input terminal of the storage summation unit in all electronic storage computing units of column j is connected to the second signal line of column j; i=1,2,…,M, j=1,2,…,N; First, the first scan line of the first row is used to enable the first signal reading function of all storage summation units in the first row. The storage summation unit in the j-th electronic storage calculation unit of the first row reads the first electrical signal on the first signal line of the j-th column. Once all storage summation units in the first row have read and stored the corresponding first electrical signal, the first scan line of the first row is used to disable the first signal reading function of all storage summation units in the first row. Then, the first scan line of the second row is used to enable the first signal reading function of all storage summation units in the second row, until all storage summation units in all rows have read and stored the corresponding first electrical signal. The first electrical signal read by each storage summation unit can be different. Then the second electrical signal is transmitted through the second signal line of the first column to the storage summation unit in the storage calculation unit of the first column, and the calculation unit outputs the calculation result; then the second electrical signal is transmitted through the second signal line of the second column to the storage summation unit in the storage calculation unit of the second column, thereby completing the calculation result in sequence.

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