De-interlacing device based on a shared register array

Abstract

The present disclosure provides a de-interlacing device based on a shared register array. The device comprises: a de-interlacing processing module configured to successively perform a plurality of processes on interlaced image field data by a plurality of processing modules to generate de-interlaced image frame data; a shared register array configured to store respective block information associated with the plurality of processes in a plurality of register groups corresponding to the plurality of processing modules respectively; and a control module configured to control the plurality of processing modules to perform the plurality of processes based on the block information stored in the corresponding register group of the plurality of register groups respectively, and control a preceding register group of the plurality of register groups to update and store the stored block information to a subsequent register group. The present disclosure implements de-interlacing processing of images through a hardware architecture of a shared register array, reduces the complexity of the circuit, and also saves the chip area.

Description

Technical Field

[0001] This disclosure relates to the field of image processing technology, and in particular to a deinterlacing device based on a shared register array. Background Technology

[0002] Interlaced scanning and progressive scanning are both methods of representing moving images on a display device. In interlaced scanning, each frame is divided into two fields that are displayed alternately, while in progressive scanning, all the frames in each frame are displayed simultaneously. Typically, LCD TVs scan from left to right and top to bottom, scanning a fixed number of frames per second.

[0003] Progressive scanning displays the entire scan frame at a time. If the frame rate of progressive scanning is the same as that of interlaced scanning, the human eye will see a smoother image than interlaced scanning, with less flicker compared to interlaced scanning.

[0004] Interlaced scanning divides each frame into two fields. Each field contains all the odd-numbered or even-numbered scan lines of a frame. Typically, the odd-numbered lines are scanned first to obtain the first field, and then the even-numbered lines are scanned to obtain the second field. This halves the overall data volume of the video source, thus reducing the overall data storage and transmission volume. Due to the persistence of vision, the human eye will see smooth motion instead of flickering half-frame images. However, a barely noticeable flicker will appear, causing eye fatigue. This flicker is particularly noticeable when the screen content is horizontal stripes. In addition, when performing post-processing on images (such as keying), directly processing interlaced scan material will produce jagged edges, leading to a decrease in image quality. When converting interlaced digital format to film and constructing relatively perfect progressive scan video, each frame needs to be a high-quality, non-interlaced image. Therefore, it is necessary to convert the interlaced image to a progressive scan image, i.e., to perform deinterlacing.

[0005] In existing technologies, image deinterlacing is typically achieved through software algorithms, such as those based on motion detection, motion estimation, motion compensation, and motion adaptation. However, these algorithms require extensive cache, leading to excessive chip size and increased system power consumption. Summary of the Invention

[0006] The embodiments of this disclosure provide a deinterlacing device based on a shared register array. The deinterlacing processing of images is realized through the hardware architecture of the shared register array, which reduces the complexity of the circuit, reduces the workload of chip design and verification, and saves a lot of resources and chip area.

[0007] This disclosure provides a deinterlacing device based on a shared register array. The device includes: a deinterlacing processing module comprising multiple cascaded processing modules, configured to sequentially perform multiple processes on interlaced image field data to generate deinterlaced image frame data; a shared register array comprising multiple cascaded register groups, configured to store block information associated with the multiple processes in the register groups corresponding to the multiple processing modules; and a control module configured to control the multiple processing modules to perform the multiple processes based on the block information stored in the corresponding register groups in the multiple register groups, and to control the preceding register group in the multiple register groups to update the stored block information to the next-level register group.

[0008] In one embodiment of this disclosure, the control module is configured to generate a start signal for executing the current block processing, such that the subsequent processing module among the plurality of processing modules performs processing corresponding to the current block processing based on the processing result received from the previous processing module and the block information retrieved from the corresponding register group, according to the start signal.

[0009] In one embodiment of this disclosure, the control module is configured to generate an update signal after each of the plurality of processing modules has completed its corresponding processing, such that the previous level register group in the plurality of register groups stores the stored block information to the next level register group according to the update signal.

[0010] In one embodiment of this disclosure, the deinterlacing processing module includes a motion detection module, a motion estimation module, a motion compensation module, an enhanced edge-based interpolation module, a motion adaptation module, and an output detection module.

[0011] The motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module are configured to share block information associated with the plurality of processes to achieve deinterlacing of the image field data.

[0012] In one embodiment of this disclosure, the plurality of register groups are configured to store block information associated with a plurality of consecutive image field data.

[0013] In one embodiment of this disclosure, the control module is configured to control the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module to simultaneously perform their respective processing on an image patch basis.

[0014] In one embodiment of this disclosure, the control module is configured to update the shared register array once after a deinterlacing process is completed for an image block, such that the block information of the previous register group is updated in the subsequent register group, and the block information associated with the newly read image field data is updated in the first register group.

[0015] In one embodiment of this disclosure, the shared register array stores only the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module for the image block.

[0016] In one embodiment of this disclosure, the deinterlacing device based on a shared register array further includes a storage module configured to store multiple block information associated with multiple image field data, and to provide the multiple block information associated with the multiple image field data to the shared register array based on a DMA controller.

[0017] In one embodiment of this disclosure, the deinterlacing device based on a shared register array further includes a first data cache and a second data cache, the first data cache and the second data cache being configured to provide multiple block information associated with the multiple image field data provided by the DMA controller to the shared register array via a ping-pong mechanism.

[0018] In one embodiment of this disclosure, the deinterlacing device based on a shared register array further includes a cache module. The cache module is configured to acquire multiple block information associated with the multiple image field data in the storage module based on a DMA controller, and to provide the multiple block information associated with the multiple image field data to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module, respectively, based on the DMA controller.

[0019] In one embodiment of this disclosure, when the DMA controller provides multiple block information associated with the multiple image field data to the shared register array, the multiple block information associated with the image field data is first read based on rows, and then the multiple block information associated with the image field data is read based on image blocks, wherein the image blocks are read in a left-to-right and top-to-bottom order.

[0020] In one embodiment of this disclosure, the deinterlacing device based on a shared register array further includes a parameter detection module. The parameter detection module is configured to perform frame field detection, field order detection, drop-down detection, and subtitle detection on the current image field data to generate detection parameters, and to adjust the deinterlacing processing of the next image field data based on the detection parameters.

[0021] According to embodiments of this disclosure, image deinterlacing is achieved through a hardware architecture using a shared register array, effectively improving the efficiency of deinterlacing and significantly reducing chip area. Simultaneously, it greatly reduces circuit complexity and alleviates the workload of circuit design and verification. Attached Figure Description

[0022] Figure 1 The diagram shown is a schematic representation of a motion detection algorithm in one embodiment.

[0023] Figure 2 The diagram shown is a schematic representation of a motion detection algorithm in one embodiment.

[0024] Figure 3 The diagram shows a search schematic of a motion estimation algorithm in one embodiment.

[0025] Figure 4 This is a schematic diagram of a motion estimation algorithm in the time domain in one embodiment;

[0026] Figure 5 The diagram shown is a schematic representation of a motion compensation calculation method in one embodiment.

[0027] Figure 6 A schematic diagram of an embodiment is shown as enhanced edge-based interpolation;

[0028] Figure 7 The diagram shown is a schematic representation of a motion adaptive algorithm in one embodiment;

[0029] Figure 8A The diagram shown is a block diagram of a shared register array-based deinterlacing device according to one embodiment of the present disclosure;

[0030] Figure 8B The diagram shown is a schematic representation of the deinterlacing device based on a shared register array in one embodiment of the present disclosure.

[0031] Figure 9 This is a schematic diagram of the data flow in a deinterlacing device in one embodiment;

[0032] Figure 10 This is shown as a schematic diagram of shared register array updates in one embodiment of the present disclosure;

[0033] Figure 11The diagram shows a storage schematic of a shared register array in one embodiment of the present disclosure;

[0034] Figure 12 This diagram illustrates a data reading method for a shared register array in one embodiment of the present disclosure.

[0035] Figure 13 This is a schematic diagram showing the data reading sequence of a shared register array in one embodiment of the present disclosure; Detailed Implementation

[0036] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. This disclosure can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure.

[0037] It should be noted that the illustrations provided in this embodiment are only schematic representations of the basic concept of this disclosure. Therefore, the drawings only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0038] During deinterlacing, it is necessary to fill in the unscanned half-field pixels; these pixels that need to be filled are simply called padding points. The initial points obtained in order to acquire padding points are called candidate padding points. Typically, these candidate padding points come from multiple sources.

[0039] The main purpose of motion detection is to determine whether each point in an image is dynamic or static, so as to perform deinterlacing processing on dynamic and static points. For dynamic points, if a matching block can be found, candidate padding points are obtained from the positions after the movement in the temporal domain before and after the frame; if no matching block is found, the missing data is obtained by interpolation in the spatial domain (current frame). Figure 1 This is a schematic diagram illustrating a motion detection algorithm in an embodiment of the prior art. For example... Figure 1 As shown, a 16×4 block in the current frame is searched on the reference frame, with a range of ±20 in the vertical direction and ±XX in the horizontal direction. Normally, each block should store the image data from its left and right sides for use in the search.

[0040] Figure 2 This is a schematic diagram illustrating a motion estimation algorithm in an embodiment of the prior art. For example... Figure 2As shown, four fields of data are combined to form two frames (Frame0 and Frame1). Then, by performing an MxN matrix operation on the same location, it is determined whether each point (such as the center point in the box) is dynamic or static.

[0041] Motion estimation is used to determine whether a matching block can be found. Figure 3 This diagram illustrates a search scenario in one embodiment of a prior art motion estimation algorithm. Figure 3 As shown, T2 and B3 are the current input fields, and matching blocks will be searched on T4 and B5 or T0 and B1. This search is performed on a block-by-block basis, with each block searched a certain number of times. For example, if the block size is set to 16×4, it will actually be searched using 16×6 or similar methods. The search method can be based on algorithms such as 3-dimensional recursive search (3DRS). Figure 4 The display shows a temporal search diagram of the block in the current field relative to the previous and next fields. Finally, motion estimation generates a motion vector for each block.

[0042] Motion compensation involves finding candidate fill points by moving them from the front and back fields in the time domain after a matching block has been found. Figure 5 This is a schematic diagram illustrating a motion compensation calculation method in the prior art in one embodiment. For example... Figure 5 As shown, motion compensation is performed based on the motion vector (mv) and the foreground and background fields.

[0043] Enhanced Edge-based Interpolation (EEDI) refers to the process of backtracking to use interpolation points to fill in missing data when a pixel is in motion but no matching block can be found. Figure 6 The diagram shown illustrates an embodiment of enhanced edge-based interpolation in the prior art. (See diagram for example.) Figure 6 As shown, candidate fill points are obtained in the other half of the field in the current field space by interpolation.

[0044] Motion adaptation refers to the fusion processing of static candidate fill points at the same position in the temporal direction, candidate fill points obtained by motion compensation, and candidate fill points obtained by enhanced edge-based interpolation. Figure 7 This is a schematic diagram illustrating a motion adaptive algorithm in one embodiment of the prior art. For example... Figure 7 As shown, some parameters are added during the fusion process, such as motion-static decision parameters obtained from motion detection, and other weight information.

[0045] After motion adaptation processing, there may be errors in judgment that could lead to streaking in the final image. Therefore, output image detection (CHECK) is required. If streaking is detected during image detection, some backtracking operations are needed, and the deinterlaced image data is finally output.

[0046] The deinterlacing device based on a shared register array disclosed herein will be described below through specific embodiments.

[0047] Figure 8A The diagram shown is a block diagram of a deinterlacing device based on a shared register array according to an embodiment of the present disclosure. Figure 8A As shown, the deinterlacing device 800 based on a shared register array includes a deinterlacing processing module 802, a shared register array 804, and a control module 806.

[0048] The deinterlacing processing module 802 includes multiple cascaded processing modules and is configured to sequentially perform multiple processes on the interlaced image field data to generate deinterlaced image frame data. In some embodiments, the deinterlacing processing module 802 may include any known module for performing deinterlaced image processing.

[0049] The shared register array 804 includes multiple cascaded register groups and is configured to store block information associated with the multiple processes in the multiple register groups corresponding to the multiple processing modules.

[0050] The control module 806 is configured to control the plurality of processing modules to perform the plurality of processes based on the block information stored in the corresponding register groups of the plurality of register groups, and to control the previous level register group of the plurality of register groups to update the stored block information to the next level register group.

[0051] Figure 8B The diagram shown is a structural schematic of a deinterlacing device based on a shared register array according to an embodiment of the present disclosure. Figure 8B As shown, in some embodiments, the deinterlacing processing module may include processing modules such as a motion detection module (MD), a motion estimation module (ME), a motion compensation module (MC), an enhanced edge-based interpolation module (EEDI), a motion adaptation module (MA), and an output detection module (CHECK). The motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module are configured to share block information associated with the plurality of processes to achieve deinterlacing processing of the image field data.

[0052] In addition, such as Figure 8B As shown, the shared register array includes multiple register groups TILE0, TILE1, TILE2, TILE3, and TILE4. These register groups are configured to store block information associated with multiple consecutive image field data.

[0053] Figure 9 This is a schematic diagram illustrating the data flow according to an embodiment of this disclosure. For example... Figure 9 As shown, in some embodiments, when the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module each set their own buffer BUF, the required buffer BUF capacity is very large. Therefore, this disclosure uses the shared register array to simultaneously provide each processing module with shared block information associated with multiple consecutive image field data, thereby effectively reducing data buffer capacity, reducing chip area, and improving data processing efficiency.

[0054] In some embodiments, the shared register array includes multiple registers (e.g., TILE0, TILE1, TILE2, TILE3, TILE4) configured to store multiple consecutive block information associated with image field data. In some embodiments, the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module each require all or part of the multiple consecutive block information associated with the image field data. For example, the motion estimation module may actually use information stored in TILE0, TILE1, TILE2, TILE3, TILE4.

[0055] The shared register array is composed of registers, characterized by its stable output until new data is written. Each bit has an input and an output, and the output can be directly sent to various modules, enabling high-bandwidth data output. For example, if the motion estimation module needs 16 × 6 × 8 bits = 768 bits of data per frame during calculation, it can obtain this directly from the shared register array, whereas the bandwidth obtained through MEM storage is very limited. For instance, a large SPRF1920×128 MEM with only one read / write port can read 128 bits of data per frame at its peak, and averages 64 bits of data per frame when read / write operations are fully utilized.

[0056] In some embodiments, the motion detection module, motion estimation module, motion compensation module, enhanced edge-based interpolation module, motion adaptation module, and output detection module simultaneously process each other on an image tile basis, acquiring the image tiles by scanning sequentially from top to bottom and from left to right. It should be noted that, depending on different application requirements, the size of the image tile can be several types, such as 16×6, 16×4, and 16×2. When selecting the image tile, the motion detection module, motion estimation module, motion compensation module, enhanced edge-based interpolation module, motion adaptation module, and output detection module select the required data from the shared register array through a data selector (MUX). The above processing modules can select different data selectors (MUX). For example, some modules select data using a counter (COUNT), while others select data using candidate motion vectors (mv). (For example, the motion estimation module uses the 3DRS algorithm, selecting 16×6 data multiple times from the shared register array based on the candidate motion vectors (mv) during the calculation process.)

[0057] In some embodiments, the control module is configured to generate a start signal for executing the current block processing, causing the subsequent processing module among the plurality of processing modules to perform processing corresponding to the current block processing based on the processing result received from the previous processing module and the block information retrieved from the corresponding register group, according to the start signal. For example, the control module may uniformly generate a start signal for each module to start the current image tile operation, named ctrl_xxx_start_p, where xxx is a code name for each module. The signal is a pulse signal, indicating that the required image tile data is ready and the operation task should be started. Simultaneously, the control module has a dedicated counter to determine the coordinates of each image tile in a frame. After receiving the pulse signal, each processing module starts its state machine, begins reading the corresponding block information from the shared register array, and completes its respective operation task within a specified time slice according to its own operational logic.

[0058] Each processing module stores its own calculation results for the current image tile and outputs them to the next-level processing module. When the next-level processing module receives the `ctrl_xxx_start_p` signal, it stores the calculation results provided by the previous-level module. Taking the motion detection module and the motion estimation module as examples, the motion detection module calculates 16×4 motion / static decision results for each image tile, and internally has 16×4 register storage units to store these results. When the motion estimation module receives the `ctrl_me_start_p` pulse signal, it stores these results within one clock cycle. For example, the motion estimation module provides the motion compensation module with the motion vector `mv` of the current image tile. The enhanced edge-based interpolation module provides the motion adaptation module with two 16×2 image interpolation results. The motion compensation module provides the motion adaptation module with two 16×2 motion compensation results. In some embodiments, the control module is configured to generate an update signal after each of the plurality of processing modules has completed its corresponding processing, such that the previous level register group in the plurality of register groups stores the stored block information to the next level register group according to the update signal.

[0059] In some embodiments, the deinterlacing apparatus based on a shared register array disclosed herein may further include a storage module. The storage module is configured to store multiple block information associated with multiple image field data, and to provide the multiple block information associated with the multiple image field data to the shared register array based on a DMA (Direct Memory Access) controller. In some embodiments, the storage module employs DDR. The DDR stores image field data obtained by interlacing scanning, and the image field data is provided to the shared register array and the input FIFOs of the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module via the DMA controller, so that each processing module can perform its own data processing. It should be noted that the data required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module comes from the shared register array, the input FIFOs, and the output data from the preceding module. The required data may differ for different modules, which will not be elaborated further here. The data in the input FIFO is directly used by the motion detection module, motion estimation module, motion compensation module, enhanced edge-based interpolation module, motion adaptation module, and detection module, and is not sent to the shared register array. The input FIFO serves to buffer data because there is a significant latency between issuing the data retrieval command and obtaining the data; buffering the data compensates for the performance loss caused by this latency. Furthermore, the deinterlaced image frame data obtained by the motion detection module, motion estimation module, motion compensation module, enhanced edge-based interpolation module, motion adaptation module, and detection module is then stored in the storage module via a DMA controller.

[0060] In some embodiments, the deinterlacing apparatus based on a shared register array disclosed herein may further include a cache module ORG LINEBUF. The cache module is configured to acquire multiple block information associated with the multiple image field data from the storage module based on a DMA controller, and to provide the multiple block information associated with the multiple image field data to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module, respectively, based on the DMA controller. By setting the cache module ORGLINEBUF, the required data can be quickly provided to the register array to accelerate the deinterlacing process, and additional data fetching can be avoided, reducing data fetching bandwidth.

[0061] In some embodiments, the control module is configured to update the shared register array once after a deinterlacing process is completed for an image block, such that block information in the previous register group is updated in the subsequent register group, and block information associated with newly read image field data is updated in the first register group.

[0062] Figure 10 The diagram shown illustrates a shared register array update according to an embodiment of this disclosure. Figure 10 As shown, the block information of TILE3 is updated to TILE4, the block information of TILE2 is updated to TILE3, the block information of TILE1 is updated to TILE2, and the block information of TILE0 is updated to TILE1. The new block information of TILE0 is read from the shared register array, the input FIFO, and the buffer module ORG LINE BUF.

[0063] In some embodiments, each of the motion detection module, motion estimation module, motion compensation module, enhanced edge-based interpolation module, motion adaptation module, and detection module issues a "ready" signal after completing the calculation of its current image tile. After all modules have completed the calculation of their current image tile, a unified update of the shared register array is performed to prepare for the calculation of the next image tile for each module. It should be noted that, to avoid large power consumption spikes caused by updating too much memory at once, the shared memory array update is divided into two-step operations. Tiles 2, 3, and 4 are updated first, while the other tiles are updated one step later, thereby halving the power consumption spike.

[0064] In some embodiments, the shared register array stores only the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module for the image patch.

[0065] Figure 11 The diagram shown is a storage schematic of a shared register array according to an embodiment of the present disclosure. Figure 11As shown, each small circle in the diagram represents a pixel. The row of registers containing the current frame (Cur) indicates that this register array stores the block information of the current frame (Cur), and the same applies to Nxt frames. Taking the motion estimation module as an example, the currently processed image block (tile) is TILE2. To achieve image block matching, it searches for matching image blocks in the shared register array, centered on TILE2 and expanding 28 units to the left and right. Other modules follow the same principle. Therefore, the shared register array described in this disclosure only stores the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module. The range of image frame data used by each processing module to complete the calculation of the current image block is different. To save area, only the union of the data needed by each processing module is stored; it is not necessary to store all the data. Figure 11 As shown, when TILE1 provides data to TIEL2, some useless data is discarded. For each TILE, the further to the right, the more data is discarded.

[0066] Figure 12 The diagram illustrates a data reading method for a shared register array according to an embodiment of the present disclosure. Figure 12 As shown, in some embodiments, the deinterlacing device based on a shared register array disclosed herein may further include a first data buffer DATA_IN_BUF0 and a second data buffer DATA_IN_BUF1. The first data buffer DATA_IN_BUF0 and the second data buffer DATA_IN_BUF1 are configured to provide multiple block information associated with the multiple image field data provided by the DMA controller to the shared register array via a ping-pong mechanism. There is a long latency from issuing a command to obtaining data. To compensate for the performance loss caused by this latency, this disclosure adopts a ping-pong data retrieval scheme. For example, during time period T0, DATA_IN_BUF0 is configured to receive block information provided by the DDR, and DATA_IN_BUF1 is configured to update the data in the shared register array. When DATA_IN_BUF0 is full of data, DATA_IN_BUF1 is also cleared. Entering time period T1, DATA_IN_BUF1 is configured to receive block information provided by the DDR, and DATA_IN_BUF0 is configured to update the data in the shared register array.

[0067] In some embodiments, when the DMA controller provides multiple block information associated with the multiple image field data to the shared register array, the multiple block information associated with the image field data is first read based on rows, and then the multiple block information associated with the image field data is read based on image blocks, wherein the image blocks are read in a left-to-right, top-to-bottom order.

[0068] Figure 13 This diagram illustrates the data read order of a shared register array according to an embodiment of the present disclosure. Figure 13 As shown, for each block of information, data is initially retrieved row by row, and then retrieved block by block. It should be noted that, to maintain compatibility with the DDR storage module, the data retrieval block size must be larger than the image tile size; for example, the data retrieval block might be 256×4, while the image tile is 16×4. When retrieving data row by row, the number of rows is related to the vertical expansion of the relevant module; for example, motion estimation requires vertical expansion.

[0069] In some embodiments, the deinterlacing apparatus based on a shared register array disclosed herein may further include a parameter detection module. The parameter detection module is configured to perform frame field detection, field order detection, drop-down detection, and caption detection on the current image field data to generate detection parameters, and to adjust the deinterlacing processing of the next image field data based on the detection parameters. It should be noted that the detection parameters are provided to the CPU, which then provides the detection parameters to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module, so that each module adjusts the processing parameters of the next image frame data in real time.

[0070] The above embodiments are merely illustrative of the principles and effects of this disclosure and are not intended to limit this disclosure. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this disclosure. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this disclosure should still be covered by the claims of this disclosure.

Claims

1. A deinterlacing device based on a shared register array, characterized in that, include: The deinterlacing processing module includes multiple cascaded processing modules and is configured to perform multiple processing steps on the interlaced image field data to generate deinterlaced image frame data. A shared register array, comprising multiple cascaded register groups, is configured to store block information associated with the multiple processes in the multiple register groups corresponding to the multiple processing modules. as well as The control module is configured to control the plurality of processing modules to perform the plurality of processes based on the block information stored in the corresponding register groups of the plurality of register groups, and to control the previous-level register group in the plurality of register groups to update the stored block information to the next-level register group. The deinterlacing module includes a motion detection module, a motion estimation module, a motion compensation module, an enhanced edge-based interpolation module, a motion adaptation module, and an output detection module. The motion detection module, motion estimation module, motion compensation module, enhanced edge-based interpolation module, motion adaptation module, and output detection module are configured to share block information associated with the multiple processes to achieve deinterlacing of the image field data. The control module is configured to control the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the detection module to simultaneously process each other on an image patch basis.

2. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The control module is configured to generate a start signal for executing the current block processing, such that the subsequent processing module among the plurality of processing modules performs processing corresponding to the current block processing based on the processing result received from the previous processing module and the block information retrieved from the corresponding register group, according to the start signal.

3. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The control module is configured to generate an update signal after each of the multiple processing modules has completed its corresponding processing, so that the previous level register group in the multiple register groups stores the stored block information to the next level register group according to the update signal.

4. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The multiple register groups are configured to store block information associated with multiple consecutive image field data.

5. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The control module is configured to update the shared register array once after a deinterlacing process is completed for an image block, such that the block information of the previous register group is updated in the subsequent register group, and the block information associated with the newly read image field data is updated in the first register group.

6. The deinterlacing device based on a shared register array according to claim 1, characterized in that, The shared register array stores only the block information required by the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module, and the output detection module for the image patch.

7. The deinterlacing device based on a shared register array according to claim 1, characterized in that, It also includes a storage module configured to store multiple block information associated with multiple image field data, and to provide the multiple block information associated with the multiple image field data to the shared register array based on the DMA controller.

8. The deinterlacing device based on a shared register array according to claim 7, characterized in that, It also includes a first data cache and a second data cache, which are configured to provide multiple block information associated with the multiple image field data provided by the DMA controller to the shared register array via a ping-pong mechanism.

9. The deinterlacing device based on a shared register array according to claim 7, characterized in that, It also includes a caching module, which is configured to acquire multiple block information associated with the multiple image field data in the storage module based on the DMA controller, and provide the multiple block information associated with the multiple image field data to the motion detection module, the motion estimation module, the motion compensation module, the enhanced edge-based interpolation module, the motion adaptation module and the detection module respectively based on the DMA controller.

10. The deinterlacing device based on a shared register array according to claim 7, characterized in that, When the DMA controller provides multiple block information associated with the multiple image field data to the shared register array, it first reads the multiple block information associated with the image field data based on rows, and then reads the multiple block information associated with the image field data based on image blocks. When reading the image blocks, the order is from left to right and from top to bottom.

11. The deinterlacing device based on a shared register array according to claim 1, characterized in that, It also includes a parameter detection module, which is configured to perform frame field detection, field order detection, drop-down detection, and subtitle detection on the current image field data to generate detection parameters, and to adjust the deinterlacing processing of the next image field data based on the detection parameters.

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