Discrete combination optimization control method of switchable series-parallel current limiting circuit based on IGBT and contactor

Abstract

The application discloses a discrete combination optimization control method of a switchable series-parallel current limiting circuit based on IGBT and contactors, and relates to the technical field of power electronic control and electrical testing.The control method comprises the following steps: S1, a real-time sensing step: collecting a target current limiting value of a system, a bus voltage, and real-time state data of each reconfigurable power module, wherein the real-time state data at least comprises a current value, a voltage value and a device temperature.The discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactors can automatically and accurately select a scheme meeting static and dynamic performance requirements from a large number of possible topologies by dynamically sensing real-time working conditions and constructing a discrete optimization model containing multiple targets, thereby solving the problems of limited adjustment range and insufficient precision of a traditional fixed topology circuit, and ensuring the response reliability and control accuracy of the system under wide-range working conditions.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of power electronic control and electrical testing, in particular to a discrete combination optimization control method of a switchable series-parallel current limiting circuit based on IGBT and contactor. BACKGROUND

[0002] With the rapid development of modern power systems and industrial automation fields, the performance requirements of circuit protection and current limiting devices are increasingly improved, especially in flexible HVDC transmission systems, new energy grid-connected, high-power variable frequency drive and other occasions, the rapid isolation and current limiting of short-circuit faults are crucial. At present, the current limiting device mostly adopts the combination of solid-state switching devices such as IGBT and mechanical contactors to balance fast response and high current carrying capacity. However, when facing different fault current levels and system operating states, the existing current limiting circuit often adopts a fixed series-parallel structure, lacks flexible and adjustable topology switching capability, resulting in limited application range, suboptimal response characteristics, and uneven device stress and intensified oscillation in high-frequency switching process. The authorized publication CN118198986A discloses a self-triggering series-parallel IGBT assembly suitable for DC circuit breakers, which simplifies the driving structure of multi-IGBT series-parallel by integrating a driving module, a buffer circuit and an oscillation suppression module, and improves the consistency of series voltage division and parallel current division. This scheme reduces the system complexity and cost to a certain extent, but it is still limited to fixed series-parallel configuration, cannot dynamically adjust the topology structure according to real-time operating conditions, and is difficult to achieve smooth switching and discrete optimal control between multiple modes during current limiting.

[0003] In addition, the existing combined current limiting device often relies on centralized or continuous control strategies, which are difficult to balance response speed, reliability and control accuracy, especially when multiple devices work cooperatively, control delay and logic conflicts are prone to occur, affecting the overall stability and fault recovery capability of the system. Therefore, how to design a current limiting circuit that can switch the series-parallel structure according to the system state in real time and achieve fast, reliable and current-sharing current limiting through a discrete combination optimization control method has become a technical problem to be solved in the field. SUMMARY

[0004] The present application aims to provide a discrete combination optimization control method of a switchable series-parallel current limiting circuit based on IGBT and contactor to solve the problems raised in the background art.

[0005] To solve the above technical problems, the application provides the following technical solutions: a discrete combination optimization control method of a switchable series-parallel current limiting circuit based on IGBT and contactors, the current limiting circuit comprising at least one reconfigurable power module, each reconfigurable power module being provided with IGBT, contactors and resistance elements, and realizing multiple topologies of internal series connection, parallel connection or series-parallel connection through state switching of the contactors, the control method comprising the following steps:

[0006] S1, a real-time sensing step: collecting target current limiting values of a system, bus voltages, and real-time state data of each reconfigurable power module, the real-time state data at least including current values, voltage values and device temperatures;

[0007] S2, a pre-computation step: generating constraint conditions based on the data collected in step S1, and through optimization computation on all effective state combinations of the contactors under the constraint conditions, screening at least one candidate topology scheme, the effective state combination referring to a contactor on-off combination that will not cause electrical connection conflicts;

[0008] S3, a dynamic pre-performance step: simulating a current establishment process of each candidate topology scheme screened in step S2 based on a circuit model, predicting dynamic response characteristics thereof, and performing secondary screening on the candidate topology schemes according to preset dynamic performance indexes, to determine a final execution topology scheme;

[0009] S4, an execution and verification step: controlling the contactors and the IGBTs to execute the final execution topology scheme determined in step S3, and simultaneously monitoring actual electrical waveforms, and comparing and verifying the actual electrical waveforms with corresponding simulated expected waveforms in the dynamic pre-performance step;

[0010] S5, a feedback updating step: according to actual operation data obtained through monitoring and verification in step S4, modifying model parameters used to generate the constraint conditions in step S2 or parameters of the circuit model in step S3, and using the modified parameters for the next control process.

[0011] Further, in the S1 real-time sensing step, generating the constraint conditions specifically comprises: calculating current thermal stress and voltage stress of each IGBT based on the real-time state data, to form an upper limit of current and an upper limit of voltage allowed to pass through each IGBT at the current time; and setting a maximum allowed response time and a maximum allowed current overshoot value according to system protection requirements; all the current upper limit, the voltage upper limit, the maximum allowed response time and the maximum allowed current overshoot value jointly constitute the constraint conditions.

[0012] Further, the S2 pre-computation step is specifically: taking the state vector of the contactor as the decision variable, constructing a discrete combinatorial optimization model with the goal of minimizing the current regulation error, and solving the model under the constraint condition to obtain at least one candidate topology scheme within the allowable range of the current regulation error; the current regulation error refers to the difference between the expected current generated by the candidate topology scheme under a given bus voltage and the target current limiting value.

[0013] Further, the discrete combinatorial optimization model is a multi-objective optimization model, and its objective function includes minimizing the current regulation error, minimizing the system on-state loss estimate value, and minimizing the number of contactors that need to be changed from the current topology to the target topology; a set of Pareto optimal solutions is obtained as the candidate topology scheme by solving the model through a multi-objective optimization algorithm.

[0014] Further, in the S3 dynamic pre-performance step, the predicted dynamic response characteristics at least include: simulating the current dynamic distribution process of each parallel branch under the candidate topology scheme to evaluate the dynamic current sharing performance; simulating the turn-off process of the IGBT to evaluate the dynamic voltage sharing performance; and verifying whether all contactors that need to act can complete mechanical switching within the maximum allowed response time under the current state.

[0015] Further, the S4 execution and verification step further includes: if the deviation between the actual electrical waveform and the simulated expected waveform exceeds a preset verification threshold, triggering a control failure warning signal.

[0016] Further, the control method further includes:

[0017] S6, hot standby switching step: after the S3 dynamic pre-performance step, one or more suboptimal topology schemes that pass the secondary screening but are not selected as the final execution topology scheme are reserved as hot standby schemes; when the control failure warning signal is triggered in the S4 execution and verification step, or when a device failure is detected by the real-time state data monitoring, the control system decides and switches to one of the hot standby schemes within a predetermined time to continue performing the current limiting operation.

[0018] Further, the specific configuration of the reconfigurable power module is: the module contains a plurality of IGBTs and a plurality of contactors, and through different on-off combinations of the contactors, the plurality of IGBTs and internal resistors can be configured into at least three standard topologies with different equivalent impedances, and the standard topologies include a single IGBT branch topology, a two-IGBT series branch topology, and a three-IGBT series branch topology.

[0019] Further, the specific way of correcting the model parameters in the S5 feedback updating step is: an association function between the electrical parameters of the device and the working temperature and the cumulative on-flow time is established, and the experience coefficients in the association function are calibrated online by using the actual operation data to realize adaptive updating of the model.

[0020] Further, the method is applied to a system for testing the electrical performance of a relay or a fuse, the target current limiting value is set according to the test specification of the device under test, and the current value collected in the real-time sensing step is the test current flowing through the device under test.

[0021] The application provides a discrete combination optimization control method of a switchable series-parallel current limiting circuit based on IGBT and contactor.

[0022] The discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactor can automatically and accurately select a scheme meeting the static and dynamic performance requirements from a large number of possible topologies by dynamically sensing real-time working conditions and constructing a discrete optimization model containing multiple targets, solving the problems of limited adjustment range and insufficient precision of a traditional fixed topology circuit; further, dynamic pre-rehearsal based on digital simulation and closed-loop verification of actual waveforms are introduced, so that dynamic risks are avoided in advance before physical execution, and control deviation is diagnosed immediately after execution, thereby ensuring the response reliability and control accuracy of the system under wide range of working conditions.

[0023] The discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactor converts a complex test current configuration process into an automatic optimization control process, and can automatically complete optimal circuit matching and high-precision output by only inputting a target value, greatly improving the test efficiency and consistency. At the same time, the modular hardware design combined with online learning and hot standby fault tolerance mechanism makes the system not only have good scalability to adapt to different test specifications, but also have long-term running stability and continuous working ability under unexpected faults, effectively reducing the test operation complexity and equipment maintenance risk. BRIEF DESCRIPTION OF DRAWINGS

[0024] Fig. 1 A flowchart of the discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactor of the application;

[0025] Fig. 2 A discrete combination optimization algorithm flowchart of the discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactor of the application;

[0026] Fig. 3The heat backup switching decision flowchart of the discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactors of the application. DETAILED DESCRIPTION

[0027] The technical solutions in the embodiments of the application will be clearly and completely described below with reference to the drawings in the embodiments of the application. Obviously, the described embodiments are only part of the embodiments of the application, rather than all the embodiments of the application. Based on the embodiments in the application, all other embodiments obtained by a person of ordinary skill in the art without creative work are within the protection scope of the application.

[0028] Please refer to Figs. 1 to 3 The application provides the technical solution of the discrete combination optimization control method of the switchable series-parallel current limiting circuit based on IGBT and contactors. The current limiting circuit comprises at least one reconfigurable power module. Each reconfigurable power module is provided with IGBT, contactors and resistance elements, and the internal series connection, parallel connection or series-parallel connection of multiple topologies is realized through the state switching of the contactors. The control method comprises the following steps:

[0029] S1, a real-time sensing step: collecting the target current limiting value of the system, the bus voltage, and the real-time state data of each reconfigurable power module, wherein the real-time state data at least comprises current value, voltage value and device temperature;

[0030] S2, a pre-computation step: generating constraint conditions based on the data collected in step S1. Under the constraint conditions, at least one candidate topology scheme is selected by performing optimization calculation on all effective state combinations of the contactors, wherein the effective state combination refers to the contactor on-off combination that will not cause electrical connection conflict;

[0031] S3, a dynamic pre-performance step: simulating the current establishment process of each candidate topology scheme selected in step S2 based on the circuit model, predicting the dynamic response characteristics thereof, and performing secondary selection on the candidate topology schemes according to the preset dynamic performance indicators to determine the final execution topology scheme;

[0032] S4, an execution and verification step: controlling the contactors and IGBT to execute the final execution topology scheme determined in step S3, and simultaneously monitoring the actual electrical waveform in real time, and comparing and verifying the actual electrical waveform with the corresponding simulated expected waveform in the dynamic pre-performance step;

[0033] S5, a feedback updating step: according to the actual operation data obtained by monitoring and verifying in step S4, the model parameters used to generate the constraint conditions in step S2 or the parameters of the circuit model in step S3 are corrected, and the corrected parameters are used for the next control process.

[0034] It needs to be further explained that the control method is implemented based on a modular reconfigurable power module hardware platform. A specific number of insulated gate bipolar transistors (IGBTs), contactors and low-inductance nickel-chromium resistors are integrated inside each reconfigurable power module. By precisely controlling the on-off state of these contactors, the connection relationship between the IGBTs and the resistors inside the module can be dynamically changed, thereby generating a plurality of preset topologies with different equivalent impedances at the level of a single module, such as implementing a single IGBT branch, a two-IGBT series branch or a three-IGBT series branch, etc. A plurality of such modules are further connected in parallel through a system-level bus to form an array with a large range of impedance discrete adjustment.

[0035] The implementation process of the control method begins with a real-time sensing step: the control system continuously receives the target current limiting value set by the upper computer or the operation interface and the real-time bus voltage signal, and simultaneously collects the output current, port voltage and real-time working temperature of key power devices such as IGBTs and resistors of each module through the current sensor, voltage sensor and temperature sensor integrated in each module. These data together constitute a complete portrait of the current state of the system.

[0036] Next is the pre-computation step: based on the collected real-time state data, the system first calculates the safe working zone of each IGBT at the current junction temperature, and generates the instantaneous current and voltage stress constraints of each switching device in combination with its voltage rating; at the same time, according to the safety specifications of the test or protection task, such as the maximum allowed fault clearing time, etc. Under this multiple constraint condition, the system takes the on-off state of all contactors as the Boolean decision variable, and constructs a discrete combinatorial optimization problem, the core objective function of which is to find a topology combination that can make the expected output current closest to the target current limiting value.

[0037] By logically excluding all invalid switching combinations that will lead to a short circuit or an expected open circuit in advance, the system quickly filters out one or more candidate topology schemes that meet the requirements in a large but limited valid solution space using an optimization algorithm.

[0038] Then comes the key dynamic pre-play step: for each candidate topology, the control system does not execute it immediately, but injects its corresponding circuit network parameters, including equivalent resistance and parasitic inductance, into an internal simplified circuit digital twin model. This model simulates the current establishment process, dynamic current distribution of each parallel branch and voltage stress distribution when the IGBT is turned off after applying a driving signal.

[0039] Through this numerical simulation, the current sharing effectiveness, electrical stress peak value, and the presence of harmful oscillations at the actual conduction instant are pre-evaluated, so that secondary screening is performed according to pre-set dynamic stability indicators to eliminate those schemes that have good static parameters but poor dynamic performance, and finally an optimal execution topology is determined.

[0040] Then, the execution and verification step is performed: the control system sends a synchronous on-off signal to the selected IGBT through the optical fiber trigger module, and drives the corresponding contactor coil to act, completing the physical reconstruction of the circuit topology. During the current establishment and duration, the high-speed data acquisition system synchronously records the actual voltage and current waveforms of the main circuit. This actual waveform is compared with the simulation expected waveform of the corresponding topology in the dynamic pre-play step in real time. If the deviation exceeds the safety threshold set based on the model confidence, an abnormality is immediately marked.

[0041] Finally, the feedback update step is performed: after each control process, the steady-state current value, dynamic waveform characteristics, device temperature rise, and other actual operation data are recorded and used to calibrate the key parameters in the loss model and digital twin model relied on by the optimization calculation, including parasitic parameters, contact resistance, etc. This continuous learning mechanism based on actual operation data enables the control model of the system to adapt to slow changes in hardware characteristics, such as contactor contact aging and resistance value temperature drift, thereby making more accurate decisions in subsequent control cycles.

[0042] This method deeply integrates discrete combinatorial optimization, real-time digital simulation verification, and closed-loop online learning into a fast control loop, realizing a fundamental transformation of the current limiting circuit from fixed structure open-loop control to topology self-adaptive reconstruction, decision-making process pre-verification, and intelligent closed-loop control with self-learning ability. It effectively solves the problems of narrow application range, uncontrollable response characteristics, and insufficient reliability under complex working conditions caused by the fixed topology, lack of dynamic adaptation and verification in traditional solutions.

[0043] In the S1 real-time sensing step, the constraint conditions include: calculating the current thermal stress and voltage stress of each IGBT based on real-time state data to form the upper limit of the current and voltage that each IGBT can pass at the current time; and setting the maximum allowed response time and the maximum allowed current overshoot value according to system protection requirements; all current upper limits, voltage upper limits, maximum allowed response times, and maximum allowed current overshoot values together constitute the constraint conditions.

[0044] It needs to be further explained that in the specific implementation of generating constraint conditions in the real-time sensing step, the system first processes the collected real-time state data of each IGBT. For thermal stress calculation, the control system estimates the junction temperature in real time according to the pre-stored IGBT thermal model and the real-time monitored heat sink temperature or shell temperature, combined with the historical current waveform of the IGBT in the current control cycle, through thermal network equivalent method or cumulative loss integral method, wherein the IGBT thermal model includes the thermal resistance from junction to shell, the thermal resistance from shell to heat sink and other parameters.

[0045] The real-time estimated junction temperature is compared with the maximum allowed junction temperature specified in the device safety data manual, and according to the pre-set derating curve or safety margin, the upper limit of the collector current allowed to pass continuously under the current thermal state of the IGBT is dynamically calculated. For voltage stress calculation, the system monitors the real-time voltage across the collector-emitter of the IGBT, and combines the voltage spike estimation model at the turn-off time, which considers the loop stray inductance and the characteristics of the buffer circuit, to estimate the maximum peak voltage it can withstand. Compare this peak voltage with the rated collector-emitter voltage of the IGBT and consider the necessary derating to determine the safe voltage upper limit under the current voltage stress.

[0046] At the same time, the system presets the action boundary that cannot be exceeded according to the protection logic of the target application scenario, which includes the maximum allowed response time allowed from the occurrence of the fault to the effective limitation of the current, and the maximum allowed current overshoot value set to avoid misoperation or damage to the measured device; wherein the protection logic includes short circuit protection and overload protection.

[0047] These current / voltage upper limits dynamically calculated by real-time physical state, together with the timing and accuracy boundaries determined by the system protection logic, form a set of time-varying, multi-dimensional constraint conditions, which are directly input to the subsequent pre-computation step to ensure that any candidate topology scheme searched by optimization is within the real-time safe working range of all power devices and meets the system-level protection performance requirements.

[0048] The method constraint conditions are not fixed values or conservative estimates based on the worst case, but are dynamically generated according to the actual working temperature of the device, the historical load and the real-time electrical stress, so that the system can fully tap the hardware potential under the premise of ensuring absolute safety, and realize more fine and active current limiting control, which cannot be realized by traditional methods using static safety margin.

[0049] The S2 pre-computation step specifically includes: taking the state vector of the contactor as a decision variable, constructing a discrete combinatorial optimization model with the objective of minimizing the current regulation error, and solving the model under the constraint condition to obtain at least one candidate topology scheme within the allowed range of the current regulation error; the current regulation error refers to the difference between the expected current of the candidate topology scheme under a given bus voltage and the target current limiting value.

[0050] It needs to be further explained that in the specific implementation of the pre-computation step, the system abstracts the on and off states of all contactors in each reconfigurable power module into a binary state vector, which uniquely defines the global topology structure of the entire current limiting circuit at a certain time. Taking this state vector as the core decision variable, the control system constructs a clear discrete combinatorial optimization model. The objective function of the model is set to minimize the current regulation error, that is, for any given state vector, a specific topology is obtained. First, the total equivalent resistance is calculated according to the equivalent resistance of all conducting branches in parallel under the topology, and then the expected output current is calculated through Ohm's law combined with the real-time collected bus voltage; finally, the absolute value of the difference between the expected current and the externally set target current limiting value is calculated.

[0051] The task of the system is to search for a state vector that can minimize the absolute value within the solution space defined by the dynamic constraint condition. The solving process does not traverse all theoretically possible state combinations, the number of which grows exponentially with the number of contactors, which is unrealistic, but rather logically excludes all invalid state vectors that would lead to power short circuit, load open circuit or violation of basic series and parallel electrical rules, thereby limiting the search range to a limited set of valid state combinations.

[0052] On this set, the system can use a discrete search method based on gradient information or a heuristic strategy for optimization. Once one or more state vectors are found, whose deviation of the expected current from the target value falls within the pre-set allowable error tolerance, the circuit topology corresponding to these vectors is output as a candidate topology scheme.

[0053] This method converts the complex and experience-dependent circuit topology selection problem into a mathematical optimization problem with a clearly defined objective function and constraint condition, and greatly reduces the search space by introducing the concept of valid state combinations, enabling the automatic and accurate selection of circuit configuration schemes that meet the static electrical performance requirements from a vast number of possibilities within the engineering achievable calculation time, replacing the outdated methods that rely on fixed collocation or manual estimation.

[0054] The discrete combinatorial optimization model is a multi-objective optimization model, and the objective function includes minimizing current regulation error, minimizing system on-state loss estimation value, and minimizing the number of contactors to be changed from the current topology to the target topology. A multi-objective optimization algorithm is used to solve the model to obtain a set of Pareto optimal solutions as candidate topology schemes.

[0055] It should be further explained that the discrete combinatorial optimization model is extended to a multi-objective optimization model, and the objective function is composed of three sub-targets that are related to each other and may conflict. The first sub-target is to minimize the current regulation error to ensure the current limiting accuracy. The second sub-target is to minimize the system on-state loss estimation value, which is obtained by summing the product of the on-state voltage drop of all IGBTs and resistive elements in the on-state under the candidate topology and the expected current. The calculation is corrected by referring to the on-state characteristic curve provided in the device data manual and the real-time collected device temperature, aiming to improve energy efficiency and reduce thermal stress.

[0056] The third sub-target is to minimize the number of contactors to be changed from the current topology to the target topology, i.e., the number of bits to be flipped in the state vector, which is directly related to the mechanical wear, action time and reliability of the switching process. A multi-objective optimization algorithm, such as a genetic algorithm based on fast non-dominated sorting, is used to solve the model.

[0057] When the genetic algorithm based on fast non-dominated sorting is used to solve the multi-objective discrete combinatorial optimization model, the core operating parameters of the algorithm can be adaptively set according to the number of reconfigurable power modules and the total number of contactors. The specific parameter value ranges are as follows: the population size is set to 30 to 50 individuals, each individual corresponds to an effective state vector of a set of contactors; the number of iterations is set to 50 to 80 generations to ensure that the algorithm converges to the Pareto optimal solution within an acceptable calculation time in engineering; the crossover operation adopts a simulated binary crossover strategy, and the crossover probability is controlled between 0.7 and 0.9 to ensure the effective transmission of good genes in the population; the mutation operation adopts a basic bit mutation strategy, and the mutation probability is controlled between 0.01 and 0.03 to maintain the diversity of the population and avoid the algorithm falling into local optimum. When the total number of contactors exceeds 10, the population size can be increased to 50 individuals, the number of iterations can be increased to 80 generations, the crossover probability can remain at 0.8, and the mutation probability can be increased to 0.03 to ensure the optimization coverage of the algorithm; when the total number of contactors is less than 5, the population size can be reduced to 30 individuals, and the number of iterations can be reduced to 50 generations to improve the operation efficiency of the algorithm.

[0058] The algorithm searches in parallel in the effective state combination space defined by the dynamic constraint conditions, and finally outputs a set of Pareto optimal solutions to form a candidate topology scheme set.

[0059] Each scheme in the set represents a compromise between different sub-goals, for example, scheme A can have the highest current accuracy but larger loss, while scheme B has lower loss but more contactors to switch.

[0060] This multi-objective comprehensive optimization breaks the limitation of traditional methods focusing on a single current accuracy index, and automatically explores and presents a variety of performance balanced feasible topologies through algorithms, so that the control decision can be made according to the real-time system priority, such as priority of accuracy in testing, priority of efficiency or device life in continuous operation, to flexibly select the most suitable execution scheme from the Pareto frontier, and realize more comprehensive and intelligent optimization of circuit performance.

[0061] In the S3 dynamic rehearsal step, the predicted dynamic response characteristics at least include: simulating the current dynamic distribution process of each parallel branch under the candidate topology scheme, and evaluating the dynamic current sharing performance; the dynamic current sharing performance refers to the degree of balance of the current distribution of each parallel IGBT branch in the current establishment and stable stage under the candidate topology scheme; simulating the turn-off process of IGBT, and evaluating the dynamic voltage sharing performance; the dynamic voltage sharing performance refers to the degree of balance of the voltage distribution of each device in the turn-off process of the series IGBT; and verifying whether all contactors that need to act can complete mechanical switching within the maximum allowed response time under the current state.

[0062] It needs to be further explained that in the specific implementation of the dynamic rehearsal step, the system starts an independent digital simulation process based on the circuit parameters for each candidate topology scheme through pre-computation. The simulation process first calls the pre-stored corresponding circuit network model according to the selected topology, and the model not only includes the ideal resistance value of each branch, but also takes into account the loop parasitic inductance and distributed capacitance parameters estimated based on the PCB layout and device packaging.

[0063] The specific equivalent topology of the circuit digital twin model adopts a modular RL series-parallel structure. For each reconfigurable power module, the equivalent topology is dynamically built according to different candidate topology schemes. A single IGBT branch is equivalent to an IGBT switch model in series with a branch resistance and a parasitic inductance. Two IGBT branches in series are equivalent to two IGBT switch models connected in series, followed by a branch resistance and a parasitic inductance. Three IGBT branches in series are equivalent in the same way. For a system-level topology with multiple modules in parallel, the equivalent topologies of the modules are connected in parallel through a bus equivalent resistance and a parasitic inductance, while the distributed capacitance at the connection points of the modules and the bus is also taken into account. The parasitic parameters in the model are obtained by industry conventional empirical estimation methods. The parasitic inductance of the PCB trace is estimated according to the length, width, copper thickness, and reference ground plane spacing of the trace. For reference, the trace inductance empirical estimation rules in IPC-2221 standard can be used, that is, the longer the trace length and the narrower the width, the larger the parasitic inductance value. The parasitic inductance and distributed capacitance of the device package are taken from the typical values of the packaging parasitic parameters provided in the device data manual. The contact resistance of the contactor contact is corrected according to the ratio of the rated current to the actual current-carrying current. The closer the current-carrying current is to the rated current, the closer the contact resistance is to the minimum value in the manual. When simulating the current establishment and turn-off process, the IGBT switch model uses a simplified switching transient model, which only retains core transient parameters such as turn-on delay, turn-off delay, current rise slope, and voltage drop slope. The parameter values are taken from the typical values of the switching characteristics in the device manual and are corrected according to the real-time junction temperature.

[0064] The core task of the simulation is to simulate the transient process of current establishment.

[0065] To evaluate the dynamic current sharing performance, the simulation calculates the difference in the current rise waveform in each parallel IGBT branch after applying the drive pulse, analyzes the degree of uneven current distribution caused by device parameter dispersion and circuit asymmetry, and predicts the maximum transient current deviation that may occur. To evaluate the dynamic voltage sharing performance, the simulation simulates the transient voltage distribution process of the series-connected IGBTs caused by inconsistent turn-off times and parasitic parameter resonance after the turn-off command is issued, and predicts the maximum turn-off voltage spike each IGBT will withstand.

[0066] At the same time, the system verifies whether the estimated total time required from issuing the switching command to the stable positioning of all contacts is shorter than the maximum allowed response time preset by the system, based on the pre-stored average mechanical action time and its dispersion statistics of each type of contactor, combined with the number and position of the contactors to be switched.

[0067] The dynamic preview step uses digital simulation means to preview and quantitatively evaluate the dynamic behavior of the candidate scheme before performing the physical action, identifies and screens the dynamic current sharing, voltage sharing and timing coordination risks that may be exposed only after the circuit is actually turned on, thereby fundamentally avoiding the field oscillation, over-stress or response timeout failures that may be caused by selecting the topology only according to the static resistance parameters, and realizing the decision mode upgrade from static parameter matching to dynamic behavior verification.

[0068] The execution and verification step further includes: if the deviation of the actual electrical waveform from the simulated expected waveform exceeds the preset verification threshold, a control failure warning signal is triggered.

[0069] It needs to be further explained that in the specific implementation of the execution and verification step, the control system starts a high-speed data acquisition and comparison thread at the same time as the contactor and IGBT complete the final execution of the topology scheme switching. The thread synchronously captures the actual voltage and current waveforms of the key nodes in the main circuit through a high-precision, high-bandwidth analog-to-digital converter.

[0070] At the same time, the simulated expected waveform data generated in the dynamic preview step for the current execution scheme is called to the memory as a comparison reference, wherein the simulated expected waveform data includes the current rise curve, the steady-state value and the key harmonic characteristics. The comparison process is not a simple steady-state value comparison, but after the actual waveform and the expected waveform are time-domain aligned within a preset time window, the error norm between the two is calculated, such as the root mean square error or the peak absolute difference.

[0071] The verification threshold preset by the system is not a fixed value, but is dynamically calculated according to the confidence of the digital twin model under the current working condition, the measurement accuracy of the sensor and the margin required for safe operation of the system.

[0072] The specific determination logic of the dynamic verification threshold needs to be determined in combination with the confidence of the digital twin model, the sensor measurement accuracy and the system safety margin. The model confidence is determined according to the deviation statistical value of the simulation waveform and the measured waveform in the historical control cycle. The root mean square error of the waveform of the last 50 effective control cycles is calculated. The smaller the error is, the higher the model confidence is. The confidence coefficient is in the range of 0.8 to 1.0. The sensor measurement accuracy is converted into a specific error range according to the factory calibration accuracy level of the current and voltage sensors. For example, the measurement error coefficient of a 0.5-level current sensor is 0.5%, and the measurement error coefficient of a 0.2-level voltage sensor is 0.2%. The system safety margin is set according to the test requirements of the target application scene. When applied to the electrical performance test of a relay, the safety margin coefficient is set to 5%. When applied to the electrical performance test of a fuse, the safety margin coefficient is set to 3%. The comprehensive value of the dynamic verification threshold is a weighted combination of the three. The weight of the model confidence coefficient is 0.4, the weight of the sensor measurement error coefficient is 0.3, and the weight of the system safety margin coefficient is 0.3. In actual determination, if the model confidence is higher than 0.9, the weight of the model confidence coefficient can be appropriately increased to 0.5 and the weight of the sensor measurement error coefficient can be reduced to 0.2. If the sensor is in a high noise working condition, the weight of the sensor measurement error coefficient can be increased to 0.4 and the weight of the model confidence coefficient can be reduced to 0.3, so as to ensure that the threshold can adapt to different operating conditions and accurately determine the waveform deviation.

[0073] For example, when the model confidence is low or the sensor noise is large, the threshold is relaxed accordingly. When the calculated error norm exceeds the dynamic verification threshold, the system immediately triggers a digital control failure warning signal.

[0074] The signal is set as an internal state flag and can be uploaded to the upper monitoring system through the communication interface or triggered locally. This step builds a real-time health diagnosis link based on dynamic waveform comparison, converting open-loop execution into closed-loop verification with immediate feedback. This not only captures control deviations caused by model mismatch, device parameter drift or unexpected interference, but also provides a quantitative evaluation method for the consistency of control instructions and actual physical responses at the execution level, providing higher level reliability and state awareness for the system from execution to verification, and from exception to early warning.

[0075] The control method further comprises:

[0076] S6, hot standby switching step: after the S3 dynamic rehearsal step, one or more suboptimal topology schemes that pass the secondary screening but are not selected as the final execution topology scheme are reserved as hot standby schemes; when the control failure warning signal is triggered in the S4 execution and verification step, or the real-time state data detects a device failure, the control system decides and switches to one of the hot standby schemes within a predetermined time to continue executing the current limiting operation.

[0077] It needs to be further explained that in the specific implementation of the hot standby switching step, after completing the dynamic rehearsal and secondary screening, the system not only determines the final execution topology scheme, but also stores one or more suboptimal topology schemes and their complete contactor driving sequences, expected electrical parameters and simulation waveform characteristics in the non-volatile memory immediately after the evaluation indicators, which are marked as hot standby schemes. These hot standby schemes, like the final scheme, have passed the screening of static constraints and dynamic rehearsal, and have the basic conditions for immediate operation. When the control failure warning signal is triggered in the execution and verification step, such as waveform deviation exceeding the limit, or the real-time state data monitoring thread independently detects explicit faults such as IGBT drive error, contactor contact state feedback anomaly or device temperature rapid rise, the system immediately interrupts the regular process and starts a high-priority fault evaluation and switching decision routine.

[0078] The routine first classifies and locates the abnormal event, determines whether it affects the safe operation of the current topology and the scope of the impact. Subsequently, it traverses all pre-stored hot standby schemes, combines the current real-time bus voltage and the availability status of each branch, for example, if the fault location is the damage of a certain module, it automatically excludes all hot standby schemes that rely on that module, from the remaining feasible schemes, selects a scheme with the smallest expected current error and the shortest switching path under the current working condition, and the least number of contactors that need to be changed as the target switching scheme.

[0079] The entire decision-making process must be completed within a very short time window to ensure that the current limiting function is not interrupted. After the decision is made, the system sends the new switching instruction sequence to the related contactor driving unit and IGBT driver through the high-speed communication bus, almost synchronously, to replace the failed original scheme. This hot standby switching mechanism upgrades the traditional static and fixed hardware redundancy to a logical topology redundancy based on multi-objective optimization results, dynamically generated and real-time evaluated.

[0080] The system not only prepares spare parts, but also prepares backup strategies that have been fully rehearsed and verified, and can intelligently select the most suitable backup strategy to perform seamless switching according to the real-time characteristics of the fault, thereby realizing the leap from passive redundancy to active fault tolerance, and enhancing the system's continuous operation capability and reliability in the event of unexpected failures at the device or control level.

[0081] The specific configuration of the reconfigurable power module is that the module contains multiple IGBTs and multiple contactors, which can be configured into at least three standard topologies with different equivalent impedances by different on-off combinations of the contactors, including a single IGBT branch topology, a two-IGBT series branch topology and a three-IGBT series branch topology.

[0082] It is further explained that in the specific hardware implementation of the reconfigurable power module, each module serves as a basic unit for building the entire switchable current limiting circuit, and contains a plurality of IGBTs and a plurality of contactors pre-planned inside, which are electrically interconnected through copper bars on the printed circuit board and power traces to form a certain internal network.

[0083] The layout and connection relationship of the contactors are specially designed, so that by programmatically controlling the on-off combination of the contactors, the IGBTs in the module and the fixed resistance elements can be reconfigured into several predefined standard topologies with different equivalent impedances.

[0084] Specifically, at least three standard topologies include: first, a single IGBT branch topology, that is, only one IGBT is connected in series with the associated resistance and then connected to the main circuit, at this time the other IGBTs are disconnected by the contactors; second, a two-IGBT series branch topology, that is, two IGBTs and their attached resistors are connected in series to form a branch by closing certain contactors; third, a three-IGBT series branch topology, that is, three IGBTs are connected in series to form a branch with higher voltage resistance and impedance.

[0085] The key to realizing these topology switches is that the contactor network is arranged between the collector, emitter of the IGBT and the connection nodes of the resistance, and by selectively bridging or isolating these nodes, the current path and the connection relationship of the elements are changed. For example, by the coordinated action of a group of contactors, the originally parallel IGBT branches can be converted into series branches, and vice versa. This hardware configuration is not simply a stack of multiple switching devices, but through an integrated and programmable contactor matrix, a single hardware module has the ability to generate multiple discrete impedance values, providing a physical basis for system-level discrete combination optimization.

[0086] Compared with traditional fixed series-parallel or parallel-only expansion modules, this design realizes topology variability at the module level, so that the final system can cover a wider impedance adjustment range with fewer module quantities and more flexible configuration methods.

[0087] In the S5 feedback updating step, the specific way to correct the model parameters is to establish a correlation function between the electrical parameters of the device and the working temperature and the cumulative current flow time, and to calibrate the empirical coefficients in the correlation function using actual operation data to realize adaptive updating of the model.

[0088] It needs to be further explained that in the specific implementation of the feedback updating step, the system realizes the adaptive correction of the model parameters by constructing and maintaining a dynamic device electrical parameter-working condition correlation model. Specifically, for IGBT, the on-state saturation voltage drop and switching loss parameters are modeled as functions of junction temperature and instantaneous current, which contain several empirical coefficients initialized by data manual typical values; for metal film or nickel-chromium resistance, the resistance value is modeled as a function of resistance body temperature, containing an initial resistance value and a temperature coefficient.

[0089] For the correlation function of device electrical parameters and working temperature, cumulative current flow time, the specific form is differentiated according to the type of device, wherein the on-state saturation voltage drop of IGBT adopts a piecewise linear correlation function, which takes the real-time junction temperature of IGBT and the cumulative current flow time as input variables, and divides the junction temperature interval into normal temperature segment (-20℃ to 50℃), medium temperature segment (50℃ to 100℃), and high temperature segment (100℃ to 150℃), each segment has independent correlation coefficients for the change rate of on-state saturation voltage drop with junction temperature and the attenuation coefficient with cumulative current flow time; the resistance value of the resistance element adopts a linear temperature correlation function, which has a single slope linear relationship between the resistance value and the resistance body temperature, and superimposes a small resistance value drift coefficient caused by cumulative current flow time. The initial empirical coefficients of the above correlation functions are preferentially taken from the typical values provided in the device factory data manual. For the coefficients without manual typical values, they are obtained through pre-factory calibration test, that is, by collecting the actual electrical parameters of the device at different temperatures and current flow times, the initial coefficients are fitted. The recursive least squares method is used for online calibration, the actual running data collected in each control cycle are used as calibration samples, a sliding data window with a length of 20 to 30 control cycles is set, only the latest effective data in the window are used to incrementally correct the empirical coefficients of the correlation function, and the earlier data are given lower weights in the correction process to ensure that the coefficients can be dynamically updated following the aging and temperature drift characteristics of the device.

[0090] The online calibration process is to use the actual steady-state running data captured in the execution and verification steps, such as average current, bus voltage, calculated equivalent total resistance under a specific topology, and synchronous monitoring of device temperature, to deduce the true values of these empirical coefficients. For example, in the case of known total current and each branch topology, combined with the measured device case temperature or heat sink temperature, the actual on-state resistance characteristics of IGBT at a specific working point can be more accurately calibrated through iterative calculation. The calibration algorithm uses parameter estimation techniques such as recursive least squares method to incrementally update the empirical coefficients in the model.

[0091] The data packet generated by each successful control cycle, i.e. the cycle without triggering a serious alarm and with reliable data, is used in this process. The calibrated new coefficients will be immediately updated in the loss estimation model in the pre-computation step and in the circuit simulation model parameter library in the dynamic pre-play step.

[0092] This method makes the control system no longer rely on the fixed initial typical value of the device parameters, but can continuously learn and track the characteristic drift of each specific device individual due to aging, temperature and use history in actual operation, so that the optimization and simulation based model always approximates the real behavior of the hardware, thereby improving the robustness of current control accuracy, loss prediction accuracy and dynamic simulation credibility in long-term operation, and realizing self-optimization and maintenance of control performance.

[0093] The method is applied to a system for testing the electrical performance of a relay or a fuse, and the target current limit value is set according to the test specification of the device under test. The current value collected in the real-time sensing step is the test current flowing through the device under test.

[0094] It should be further pointed out that in the implementation of the control method applied to the relay or fuse electrical performance test system, the target current limit value is automatically set and issued by the test system host computer according to the specification book of the device under test or the test parameters input by the operator. The specification book includes rated breaking current and time-current characteristic curve, and the test parameters include verification current value and duration.

[0095] The key current value collected in the real-time sensing step is the test current measured by the precision current transformer or Rogowski coil connected in series in the loop of the device under test. This current signal directly reflects the real load of the device under test under test conditions.

[0096] The entire control process is closely related to the test requirements: in the pre-computation step, the maximum allowed response time and other constraints are directly derived from the requirements of the test standard for short-circuit current establishment speed or full breaking time; in the dynamic pre-play step, the simulation model will pay special attention to the quality of the current rise rate and steady-state flat waveform to meet the specification for test waveform consistency.

[0097] The execution and verification step not only ensures the accuracy of the current value, but also verifies the stability of the test current within the set flow time through monitoring the waveform. The feedback update step uses the data accumulated in repeated tests to continuously optimize the model to improve the consistency and comparability of test results.

[0098] It not only solves the problem of traditional test equipment adjustment and the dependence on manual experience, but also effectively avoids the distortion of test results or abnormal damage to devices caused by poor transient characteristics of the test circuit, such as oscillation and overshoot, through dynamic pre-play and closed-loop verification.

[0099] By fusing reconfigurable hardware modules with intelligent closed-loop control procedures, the performance of the current limiting circuit is comprehensively upgraded. In terms of control capability, the method can automatically filter out schemes that meet static and dynamic performance requirements from a vast number of possible topologies by dynamically sensing real-time working conditions and constructing a discrete optimization model containing multiple objectives, solving the problem of limited adjustment range and insufficient precision of traditional fixed topology circuits. Further, dynamic pre-rehearsal based on digital simulation and closed-loop verification of actual waveforms are introduced to avoid dynamic risks in advance before physical execution and diagnose control deviations immediately after execution, thereby ensuring the response reliability and control accuracy of the system under a wide range of working conditions.

[0100] The complex test current configuration process is converted into an automatic optimization control procedure, which can automatically complete optimal circuit matching and high-precision output by only inputting target values, greatly improving test efficiency and consistency. At the same time, the modular hardware design combined with online learning and hot standby fault tolerance mechanism makes the system not only have good scalability to adapt to different test specifications, but also obtain long-term running stability and continuous working ability under unexpected failures, effectively reducing test operation complexity and equipment maintenance risk.

[0101] It should be noted that, in this text, relational terms such as first and second are used only to distinguish one entity or action from another, and do not necessarily require or imply that there is any such actual relationship or order between these entities or actions. Moreover, the terms "include", "contain" or any other variant thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or equipment including the element.

[0102] Although embodiments of the present application have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made thereto without departing from the principles and spirit of the present application, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A discrete combination optimization control method for a switchable series-parallel current limiting circuit based on IGBT and contactor, the current limiting circuit comprising at least one reconfigurable power module, each of the reconfigurable power modules being provided with an IGBT, a contactor and a resistance element, and realizing multiple topologies of internal series connection, parallel connection or series-parallel connection through state switching of the contactor, characterized in that, The control method comprises the following steps: ​ S1, a real-time sensing step: collecting target current limiting values of a system, bus voltages, and real-time state data of the reconfigurable power module, the real-time state data at least including current values, voltage values, and device temperatures; S2, a pre-computation step: generating constraint conditions based on the data collected in step S1, and filtering at least one candidate topology scheme by optimizing computation on all valid state combinations of the contactors under the constraint conditions, the valid state combinations referring to contactor on-off combinations that will not cause electrical connection conflicts; S3, a dynamic pre-performance step: simulating current establishment processes of each of the candidate topology schemes filtered in step S2 based on a circuit model, predicting dynamic response characteristics thereof, and performing secondary filtering on the candidate topology schemes according to preset dynamic performance indexes to determine a final execution topology scheme; S4, an execution and verification step: controlling the contactors and the IGBTs to execute the final execution topology scheme determined in step S3, and simultaneously monitoring actual electrical waveforms in real time, and comparing and verifying the actual electrical waveforms with corresponding simulated expected waveforms in the dynamic pre-performance step; S5, a feedback updating step: modifying model parameters used to generate the constraint conditions in step S2 or parameters of the circuit model in step S3 according to actual operation data obtained through monitoring and verification in step S4, and using the modified parameters for the next control process; The S2 pre-computation step specifically comprises: taking a state vector of the contactors as a decision variable, constructing a discrete combinatorial optimization model with current regulation error as a target, and solving the model under the constraint conditions to obtain at least one candidate topology scheme with the current regulation error within an allowable range; the current regulation error refers to a difference between an expected current generated by the candidate topology scheme under a given bus voltage and the target current limiting value.

2. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuit according to claim 1, characterized in that: In the S1 real-time sensing step, generating the constraint conditions specifically comprises: calculating current thermal stress and voltage stress of each IGBT based on the real-time state data to form an upper limit of current and an upper limit of voltage allowed to pass through each IGBT at the current time; and setting an allowable response time and an allowable current overshoot value according to system protection requirements; all the current upper limit, the voltage upper limit, the allowable response time, and the allowable current overshoot value jointly constitute the constraint conditions.

3. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuit according to claim 1, characterized in that: The discrete combinatorial optimization model is a multi-objective optimization model, and its objective function simultaneously includes the current regulation error, a system on-state loss estimated value, and a number of contactors required to be changed from a current topology to a target topology; a multi-objective optimization algorithm is used to solve the model to obtain a group of Pareto optimal solutions as the candidate topology schemes.

4. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuit according to claim 1, characterized in that: In the S3 dynamic pre-performance step, the prediction of the dynamic response characteristics at least includes: simulating a current dynamic distribution process of each parallel branch under the candidate topology scheme to evaluate dynamic current sharing performance; simulating an IGBT turn-off process to evaluate dynamic voltage sharing performance; and verifying whether all contactors required to act can complete mechanical switching within an allowable response time under the current state.

5. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuit according to claim 1, characterized in that: The S4 execution and verification step further comprises: if the deviation between the actual electrical waveform and the simulated expected waveform exceeds a preset verification threshold, triggering a control failure warning signal.

6. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuit according to claim 5, characterized in that: The control method further comprises: S6, a hot standby switching step: after the S3 dynamic rehearsal step, one or more suboptimal topology schemes that pass the secondary screening but are not selected as the final execution topology scheme are reserved as hot standby schemes; when the control failure warning signal is triggered in the S4 execution and verification step, or a device failure is monitored in the real-time state data, the control system decides and switches to one of the hot standby schemes within a predetermined time to continue executing the current limiting operation.

7. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuitry according to claim 1, characterized by: The specific configuration of the reconfigurable power module is: the module contains a plurality of IGBTs and a plurality of contactors, and the plurality of IGBTs and internal resistors are configured into at least three standard topologies with different equivalent impedances through different on-off combinations of the contactors, the standard topologies including a single IGBT branch topology, a two-IGBT series branch topology, and a three-IGBT series branch topology.

8. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuitry according to claim 1, characterized by: In the S5 feedback updating step, the specific way of correcting the model parameters is: establishing a correlation function between the electrical parameters of the device and the working temperature and the cumulative current flowing time, and using the actual operation data to online calibrate the empirical coefficients in the correlation function.

9. The discrete combination optimization control method of IGBT and contactor based switchable series-parallel current limiting circuit according to claim 8, characterized in that: The method is applied to a system for testing the electrical performance of a relay or a fuse, the target current limiting value is set according to the test specification of the device under test, and the current value collected in the real-time sensing step is the test current flowing through the device under test.

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