A low leakage Schottky diode and its fabrication method

Abstract

This invention relates to the field of diode fabrication technology, specifically disclosing a low-leakage Schottky diode and its fabrication method. The diode includes a substrate; a first N-type GaN layer disposed on the substrate; the first N-type GaN layer including a planar layer and a boss structure disposed on the planar layer; an N-type buried layer disposed on the first N-type GaN layer; a second N-type GaN layer disposed on the boss structure; and a JTE region disposed on a portion of the upper surface of the second N-type GaN layer, the sidewalls of the second N-type GaN layer, the sidewalls of the boss structure, and a portion of the upper surface of the planar layer. The JTE region is a P-type GaN layer, formed by Mg ion implantation activation, and is not in contact with the Schottky electrode, the front ohmic electrode, or the back ohmic electrode. This invention uses Mg-JTE termination instead of a metal P-type termination layer, thus eliminating the shielding effect, electric field reflection and distortion, and high-frequency parasitic capacitance or inductive interference of metal at high frequencies.

Description

Technical Field

[0001] This invention relates to the field of diode fabrication technology, specifically to a low-leakage Schottky diode and its fabrication method. Background Technology

[0002] A Schottky diode is a metal-semiconductor junction diode, also known as a hot-carrier diode, low-voltage diode, or Schottky barrier diode. A Schottky diode is formed by a junction of a semiconductor and a metal. Schottky diodes offer fast switching action and low forward voltage drop. In a PN junction diode, the p-type and n-type diodes are connected to form a PN junction, while in a Schottky diode, metals such as platinum or aluminum are used instead of the p-type semiconductor. Compared to PN junction diodes, the most significant characteristics of a Schottky diode are its low forward voltage drop and short reverse recovery time. Furthermore, Schottky diodes have low turn-on voltage and low charge storage effect, making them extremely suitable for high-frequency operation. However, high-frequency operation introduces changes in environmental parameters, such as temperature and field effects caused by high frequencies. Schottky diodes are highly sensitive to these environmental parameters, and therefore, they are prone to developing special problems in high-frequency operating environments. Therefore, improving the stability of Schottky diodes is the technical problem that this invention aims to solve. Summary of the Invention

[0003] The purpose of this invention is to provide a low-leakage Schottky diode and its fabrication method to solve the problems mentioned in the background art.

[0004] To achieve the above objectives, the present invention provides the following technical solution:

[0005] A low-leakage Schottky diode and its fabrication method, comprising:

[0006] Substrate;

[0007] A first N-type GaN layer is disposed on the substrate; the first N-type GaN layer includes a planar layer and a boss structure disposed on the planar layer;

[0008] An N-type buried layer is disposed on the first N-type GaN layer; the N-type buried layer is partially positioned below the boss structure;

[0009] A second N-type GaN layer is disposed on the boss structure;

[0010] JTE regions are disposed on a portion of the upper surface of the second N-type GaN layer, the sidewall of the second N-type GaN layer, the sidewall of the boss structure, and a portion of the upper surface of the planar layer; the JTE regions are P-type GaN layers, formed by Mg ion implantation activation, and do not contact the Schottky electrode, the front ohmic electrode, or the back ohmic electrode.

[0011] A Schottky electrode is disposed on the remaining upper surface of the second N-type GaN layer, the Schottky electrode comprising a first contact layer and a first metal layer;

[0012] A front ohmic electrode is disposed on the remaining upper surface of the planar layer, the front ohmic electrode comprising a second contact layer and a second metal layer;

[0013] A back ohmic electrode is disposed on the back side of the substrate;

[0014] A composite passivation layer deposited at the Schottky edge and above the JTE.

[0015] As a further aspect of the present invention: the substrate is an Al2O3 substrate with a thickness of 430μm-650μm and a surface roughness not exceeding 0.5nm; the planar layer has a thickness of 2.0μm-2.5μm, and the doped ions are Si with a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 The boss height is 0.6μm-0.8μm; the doping type is consistent with the planar layer, and the concentration is not less than 1×10⁻⁶. 19 cm -3 The thickness of the N-type buried layer is 0.15 μm-0.3 μm, and the doping ion is Si with a doping concentration of 5 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 The thickness of the second N-type GaN layer is 4.5 μm-5.0 μm; the dopant ion is Si, and the doping concentration is 1×10⁻⁶. 16 cm -3 -5×10 17 cm -3 The back ohmic electrode is made of a Ti, Ni, and Au composite layer with thicknesses of 20 nm, 50 nm, and 200 nm, respectively, and its contact resistance after annealing does not exceed 1 × 10⁻⁶. -5 Ω·cm 2 .

[0016] As a further aspect of the present invention: the equivalent doping concentration of Mg after activation is 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 The lateral width of the JTE region is 35μm-45μm.

[0017] As a further aspect of the present invention: the first contact layer is made of Ni with a thickness of 80nm-100nm; the first metal layer is made of Au with a thickness of 500nm-800nm; the Schottky electrode contact interface barrier height is not less than 1.05eV; the second contact layer is a Ti, Al, and Ni composite layer with thicknesses of 20nm, 120nm, and 40nm, respectively; the second metal layer is made of Al with a thickness of 800nm; and the specific contact resistance after annealing does not exceed 5×10⁻⁶. -6 Ω·cm 2 .

[0018] As a further aspect of the present invention: the gap between the JTE region and the Schottky electrode is 6μm-8μm; the gap between the JTE region and the front ohmic electrode is 6μm-8μm.

[0019] As a further aspect of the present invention: the composite passivation layer comprises a bottom layer and a top layer, wherein the equivalent dielectric constant of the composite passivation layer does not exceed 6.5, and the interface state density does not exceed 5 × 10⁻⁶. 11 cm -2 ·eV -1 The passivation layer does not cover the central region of the Schottky contact, but only covers the edge range of 5μm-10μm.

[0020] The present invention also provides a method for fabricating a low-leakage Schottky diode, the method comprising:

[0021] A first N-type GaN layer, an N-type buried layer, and a second N-type GaN layer were sequentially epitaxially grown on a substrate. The first N-type GaN layer was grown using MOCVD at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The N-type buried layer was grown at the same temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The second N-type GaN layer was grown using MOCVD at a temperature of 1040℃, a pressure of 120 Torr, a V / III ratio of 3500, with SiH4 as the dopant source but at a lower flow rate than that used in the first N-type GaN layer, and a concentration range of 1 × 10⁻⁶. 16 -5×10 17 cm -3 SiH4 is used as a doping source to control the concentration, and the target of control is the concentration of Si.

[0022] The first and second N-type GaN layers were etched using ICP-RIE dry etching. The etching gases included Cl2, BCl3, and Ar, with flow rates of 15 sccm, 5 sccm, and 10 sccm, respectively. The RF power was 120 W, the ICP power was 600 W, and the etching rate was 300-450 nm / min. The resulting bosses had a height of 0.6 μm-0.8 μm and a sidewall tilt angle of 88°-90°.

[0023] A SiO2 hard mask was used as the template to cover the area outside the JTE region for Mg ion implantation; the implantation energy was 150 keV and the dose was 1.5 × 10⁻⁶. 14 cm -2 and 5×10 13 cm -2 It adopts a two-window horizontal gradient design, with the edge windows extending outward by 35μm-45μm;

[0024] High-temperature annealing activates Mg ions and N-type buried layers; annealing parameters: temperature 1250℃, time 30min, pressure atmospheric pressure, protective gas nitrogen with a flow rate of 5L / min, heating rate 25℃ / min, cooling rate 15℃ / min.

[0025] The SiO2 hard mask was removed using the HF wet method, and the electrode was deposited by electron beam evaporation. The removal parameters were: HF solution concentration of 5% and immersion time of 60s.

[0026] TiN, Ni, and Au were deposited sequentially to form a contact layer, followed by annealing to form a stable contact layer. The annealing parameters were: temperature 400℃, annealing time 30s, protective gas nitrogen with a flow rate of 5L / min. The thickness of TiN was 10nm, the thickness of Ni was 80nm-100nm, and the thickness of Au was 500nm-800nm.

[0027] Ti, Al and Ni are evaporated, then Al is covered and annealed to form a low-resistance ohmic contact. The annealing parameters are: temperature 500℃, annealing time: 30s, protective gas is nitrogen, flow rate is 5L / min.

[0028] Evaporation of Ti, Ni, and Au followed by annealing yields a Schottky diode.

[0029] As a further aspect of the present invention, the preparation method further includes:

[0030] The device edge is formed by single ICP dry etching at an angle of 30°-40°, and the etching depth penetrates the second N-type GaN layer to the sidewall of the boss.

[0031] Compared with the prior art, the beneficial effects of the present invention are as follows: The present invention uses a single epitaxial layer to complete the first N-type GaN layer, the N-type buried layer and the second N-type GaN layer, which serve as the planar layer, the buried layer and the drift layer, respectively. The three layers are doped to form a clear band gradient, so that the depletion spread under reverse bias is stably controlled within the drift layer, avoiding the junction temperature fluctuation that causes a significant reduction in the main barrier. In addition, under high reverse temperature, hot carriers are preferentially pumped laterally to the depletion region of the buried layer instead of penetrating the main Ni / Au Schottky interface. During high-frequency surges, Joule heating is rapidly bypassed and sinks, avoiding the local hot spot temperature from exceeding the Ni / Au melting criticality. This can break the positive feedback loop of high-temperature TE leakage exponent increase and self-heating, so that the leakage growth under high frequency / high temperature is limited to less than two orders of magnitude.

[0032] This invention uses Mg-JTE terminals instead of metal P-type terminal layers, thereby eliminating the shielding effect of metal at high frequencies (affecting barrier uniformity), electric field reflection and distortion (causing premature edge breakdown), and high-frequency parasitic capacitance / inductance interference (leading to signal reflection and switching instability) from the source.

[0033] The present invention employs a selective composite passivation layer that covers only the Schottky edge region, forming a "local interface defect freezing and surface electric field buffer layer", which can make the interface state density sufficiently small, thereby suppressing surface state-assisted conductivity.

[0034] This invention uses TiN and Ni to form an ultrathin NiSi composite barrier after annealing, forming a thermally stable, uniform barrier with low interface defects, no cracking, and no high-frequency shielding interference MS junction. This ensures minimal barrier height drift under high-frequency or high-temperature conditions, stable interface band structure, and no triggering of tunneling or TFE field emission leakage current. Attached Figure Description

[0035] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention.

[0036] Figure 1 This is a schematic diagram of a low-leakage Schottky diode.

[0037] Figure 2 This is the first sub-flowchart of the method for fabricating a low-leakage Schottky diode.

[0038] Figure 3 This is the second sub-flowchart of the method for fabricating a low-leakage Schottky diode.

[0039] In the figure: 1-substrate, 2-first N-type GaN layer, 3-boob structure, 4-second N-type GaN layer, 5-Schottky electrode, 6-front ohmic electrode. Detailed Implementation

[0040] To make the technical problems, solutions, and beneficial effects of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0041] Example 1

[0042] like Figure 1 As shown, the technical solution of the present invention provides a low leakage Schottky diode, specifically comprising:

[0043] Substrate 1;

[0044] A first N-type GaN layer 2 is disposed on the substrate 1; the first N-type GaN layer includes a planar layer and a boss structure 3 disposed on the planar layer;

[0045] The first N-type GaN layer 2 is an N-type buried layer; the N-type buried layer portion is located below the boss structure 3;

[0046] A second N-type GaN layer 4 is disposed on the boss structure 3;

[0047] The substrate 1 is an Al2O3 substrate with a thickness of 430 μm and a surface roughness not exceeding 0.5 nm; the planar layer has a thickness of 2.0 μm, is doped with Si ions, and has a doping concentration of 1 × 10⁻⁶. 19 cm -3 The boss height is 0.6 μm; the doping type is consistent with the planar layer, and the concentration is not less than 1 × 10⁻⁶. 19 cm -3 The thickness of the N-type buried layer is 0.15 μm, and the doping ion is Si with a doping concentration of 5 × 10⁻⁶. 18 cm -3 The second N-type GaN layer 4 has a thickness of 4.5 μm; the dopant ions are Si, and the doping concentration is 1 × 10⁻⁶. 16 cm -3 The back ohmic electrode is made of a Ti, Ni, and Au composite layer with thicknesses of 20 nm, 50 nm, and 200 nm, respectively, and its contact resistance after annealing does not exceed 1 × 10⁻⁶. -5 Ω·cm 2 .

[0048] JTE regions are disposed on a portion of the upper surface of the second N-type GaN layer, the sidewall of the second N-type GaN layer, the sidewall of the boss structure 3, and the upper surface of the planar layer. The JTE regions are P-type GaN layers formed by Mg ion implantation activation and are not in contact with the Schottky electrode 5, the front ohmic electrode 6, or the back ohmic electrode.

[0049] A Schottky electrode 5 is disposed on the remaining upper surface of the second N-type GaN layer 4, the Schottky electrode 5 comprising a first contact layer and a first metal layer;

[0050] A front ohmic electrode 6 is disposed on the remaining upper surface of the planar layer, the front ohmic electrode 6 comprising a second contact layer and a second metal layer;

[0051] The first contact layer is made of Ni with a thickness of 80 nm; the first metal layer is made of Au with a thickness of 500 nm; the Schottky electrode contact interface barrier height is not less than 1.05 eV; the second contact layer is a composite layer of Ti, Al, and Ni with thicknesses of 20 nm, 120 nm, and 40 nm, respectively; the second metal layer is made of Al with a thickness of 800 nm; and the specific contact resistance after annealing does not exceed 5 × 10⁻⁶. -6 Ω·cm 2 .

[0052] A back ohmic electrode is disposed on the back side of the substrate 1;

[0053] A composite passivation layer deposited at the Schottky edge and above the JTE.

[0054] The composite passivation layer comprises a bottom layer and a top layer. The equivalent dielectric constant of the composite passivation layer does not exceed 6.5, and the interface state density does not exceed 5 × 10⁻⁶. 11 cm -2 ·eV -1 The passivation layer does not cover the central region of the Schottky contact, but only covers the edge range of 5μm-10μm.

[0055] like Figure 2 and Figure 3 As shown, the present invention also provides a method for fabricating a low-leakage Schottky diode, the method comprising:

[0056] Step S1: Epitaxially grow a first N-type GaN layer 2, an N-type buried layer, and a second N-type GaN layer 4 sequentially on substrate 1;

[0057] The first N-type GaN layer 2 is grown using MOCVD at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The N-type buried layer is grown at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The second N-type GaN layer 4 is grown using MOCVD at a temperature of 1040℃, a pressure of 120 Torr, and a V / III ratio of 3500. The dopant source is also SiH4, but the flow rate is lower than that used during the growth of the first N-type GaN layer 2, and the concentration range is 1 × 10⁻⁶. 16SiH4 is used as a doping source to control the concentration, and the target of control is the concentration of Si.

[0058] Step S2: The first N-type GaN layer 2 and the second N-type GaN layer 4 are etched using ICP-RIE dry etching.

[0059] The etching gases include Cl2, BCl3 and Ar, with flow rates of 15 sccm, 5 sccm and 10 sccm respectively, RF power of 120W, ICP power of 600W, and a rate of 300nm / min. The height of the formed boss is 0.6μm, and the sidewall inclination angle is 90° straight wall.

[0060] Step S3: Using a SiO2 hard mask as a template to cover the area outside the JTE region, Mg ion implantation is performed;

[0061] The implantation energy during Mg ion implantation was 150 keV, and the dose was 1.5 × 10⁻⁶. 14 cm -2 and 5×10 13 cm -2 It adopts a two-window horizontal gradient design, with the edge windows extending outward by 35μm-45μm;

[0062] Step S4: High-temperature annealing to activate Mg ions and N-type buried layer; Annealing parameters: temperature is 1250℃, time is 30min, pressure is atmospheric pressure, protective gas is nitrogen, flow rate is 5L / min, heating rate is 25℃ / min, cooling rate is 15℃ / min.

[0063] Step S5: Remove the SiO2 hard mask using the HF wet method, and deposit the electrode using electron beam evaporation; the removal parameters are: HF solution concentration of 5% and immersion time of 60s;

[0064] Step S6: Sequentially deposit TiN, Ni and Au to form a contact, then anneal to form a stable contact layer; the annealing parameters are: temperature 400℃, annealing time: 30s, protective gas is nitrogen, flow rate is 5L / min; wherein, the thickness of TiN is 10nm, the thickness of Ni is 80nm, and the thickness of Au is 500nm.

[0065] Step S7: Evaporate Ti, Al and Ni, then cover with Al and anneal to form a low-resistance ohmic contact; Annealing parameters are: temperature 500℃, annealing time: 30s, protective gas is nitrogen, flow rate is 5L / min;

[0066] Step S8: Evaporate Ti, Ni and Au, and anneal to form a Schottky diode.

[0067] Regarding the diodes fabricated using the above method, the core processes include an N-type buried layer, a non-contact JTE region, a composite passivation layer, and an ultrathin composite barrier of TiN and NiSi, as detailed below:

[0068] N-type buried layers can form locally highly doped regions (discontinuous metal layers) through epitaxy without introducing metal shielding interference. Their working principle is that under reverse bias, a lateral electric field and depletion region expansion exist at the edge of the main junction. The buried layer, acting as a locally high electron concentration layer, establishes a low-resistance current bypass in advance, guiding edge leakage current and carriers under reverse bias towards the center, suppressing edge local barrier reduction and tunneling triggering. Furthermore, at high temperatures (150℃), the Ni / Au barrier height decreases with temperature, leading to an increase in TE current. However, the buried layer provides a lower bandgap rise channel, and the reverse current preferentially depletes and expands laterally in the buried layer region rather than directly penetrating the main Schottky interface, thus breaking the positive feedback loop of "hot, leakage, and even hotter," improving junction temperature stability. Based on this, for surge current, the IFSM1A (package-level) corresponds to an internal instantaneous current density of up to 10-1. 2 -10 3 A / cm 2 The buried layer can experience a sudden surge in conductivity during a surge (electron concentration 5×10⁻⁶). 18 -1×10 19 cm -3 This allows for rapid current sinking, preventing the main Ni / Au layer from being melted by Joule heating.

[0069] The composite passivation layer is deposited only in the Schottky edge region, with no passivation layer covering the central region of the main junction, in order to avoid increasing the junction capacitance. The principle behind this is that ALD-Al2O3 is deposited at a low temperature of 350℃, which can reduce the interface state density to 10. 11 cm -2 ·eV -1 Al2O3, with its high dielectric constant and high bandgap, can reduce the peak electric field on the GaN surface and delay premature breakdown. At high temperatures, Al2O3 acts as an interfacial thermal passivation layer, which can reduce the thermal activation contribution of interfacial traps and limit the high-temperature Ir growth to within two orders of magnitude.

[0070] For the TiN and NiSi ultrathin composite barrier, TiN serves as a thermally stable transition layer, and Ni forms a NiSi composite Schottky barrier after annealing. Its working principle is that the effective work function of the NiSi / TiN composite contact is higher than that of pure Ni, which makes the barrier height stable at ≥1.05eV, meeting the requirements for high-temperature TE leakage suppression. TiN serves as a diffusion control layer, which suppresses Ni agglomeration and uneven interfacial diffusion at high temperatures, ensuring that the barrier height deviation does not exceed 0.05eV and improving the local tunneling path. TiN has high-temperature chemical stability and a low diffusion coefficient, which prevents the barrier layer from becoming unstable, cracking, or forming deep diffusion during annealing at 1250℃.

[0071] Example 2

[0072] Unlike Example 1, the substrate 1 is an Al2O3 substrate with a thickness of 650 μm and a surface roughness of no more than 0.5 nm; the planar layer has a thickness of 2.5 μm, and the doped ions are Si with a doping concentration of 5 × 10⁻⁶. 19 cm -3 The boss height is 0.8 μm; the doping type is consistent with the planar layer, and the concentration is not less than 1 × 10⁻⁶. 19 cm -3 The N-type buried layer has a thickness of 0.3 μm, is doped with Si ions, and has a doping concentration of 1 × 10⁻⁶. 19 cm -3 The second N-type GaN layer 4 has a thickness of 5.0 μm; the dopant ions are Si, and the doping concentration is 5 × 10⁻⁶. 17 cm -3 The back ohmic electrode is made of a Ti, Ni, and Au composite layer with thicknesses of 20 nm, 50 nm, and 200 nm, respectively, and its contact resistance after annealing does not exceed 1 × 10⁻⁻⁻⁶. 5 Ω·cm²;

[0073] The first contact layer is made of Ni with a thickness of 100 nm; the first metal layer is made of Au with a thickness of 500 nm-800 nm; the Schottky electrode contact interface barrier height is not less than 1.05 eV; the second contact layer is a composite layer of Ti, Al, and Ni with thicknesses of 20 nm, 120 nm, and 40 nm, respectively; the second metal layer is made of Al with a thickness of 800 nm; the specific contact resistance after annealing does not exceed 5 × 10⁻⁶. -6 Ω·cm².

[0074] The gap between the JTE region and the Schottky electrode 5 is 8 μm; the gap between the JTE region and the front ohmic electrode 6 is 8 μm.

[0075] Example 3

[0076] Unlike Example 1, the equivalent doping concentration of Mg after activation is 1×10⁻⁶. 18cm -3 The lateral width of the JTE region is 35 μm; the gap between the JTE region and the Schottky electrode 5 is 6 μm; the gap between the JTE region and the front ohmic electrode 6 is 6 μm.

[0077] The non-contact JTE region is isolated from all electrodes by 6μm-8μm, which avoids electric field interference introduced by the metal. Its working principle is that after Mg activation, an equivalent 1×10 18 The P-type region, under reverse bias, forms a laterally extended depletion region with the N⁻ drift layer, delaying vertical breakdown, making the edge of the depletion layer smooth and continuous, avoiding electric field concentration, and ensuring that the terminal does not contact the electrode. This allows the Schottky interface barrier to be determined only by the central Ni / Au / TiN, while the edge carriers are captured by the JTE depletion region, reducing the injection of edge hot carriers into the metal-semiconductor interface and improving barrier uniformity.

[0078] Example 4

[0079] Unlike Example 1, the preparation method further includes:

[0080] The device edge is formed by single ICP dry etching at an angle of 40°, and the etching depth penetrates the second N-type GaN layer 4 to the sidewall of the boss.

[0081] As a preferred embodiment of the technical solution of the present invention, by using a 30°-40° oblique angle, the electric field can be transformed from the vertical direction to the horizontal dispersion, and the peak value of the terminal electric field is reduced to 2×10. 6 V / cm (far lower than 3-5×10⁻⁵ for straight-walled structures) 6 Peak value of V / cm), suppressing premature breakdown and improving reverse withstand voltage reliability.

[0082] In addition, it is worth mentioning that in the technical solution of the present invention, the N-type buried layer and the JTE region are treated by a single annealing process. The single annealing can simultaneously realize the Mg activation process to form the P-JTE terminal, which can realize the damage repair and activation of the N-type buried layer, and can also realize the annealing repair of Schottky interface defects.

[0083] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A low-leakage Schottky diode, characterized in that, The diode includes: Substrate; A first N-type GaN layer is disposed on the substrate; the first N-type GaN layer includes a planar layer and a boss structure disposed on the planar layer; An N-type buried layer is disposed on the first N-type GaN layer; the N-type buried layer is partially positioned above the boss structure; A second N-type GaN layer is disposed on the boss structure; JTE regions are disposed on a portion of the upper surface of the second N-type GaN layer, the sidewall of the second N-type GaN layer, the sidewall of the boss structure, and a portion of the upper surface of the planar layer; the JTE regions are P-type GaN layers, formed by Mg ion implantation activation, and do not contact the Schottky electrode, the front ohmic electrode, or the back ohmic electrode. A Schottky electrode is disposed on the remaining upper surface of the second N-type GaN layer, the Schottky electrode comprising a first contact layer and a first metal layer; A front ohmic electrode is disposed on the remaining upper surface of the planar layer, the front ohmic electrode comprising a second contact layer and a second metal layer; A back ohmic electrode is disposed on the back side of the substrate; A composite passivation layer deposited at the Schottky edge and above the JTE.

2. The low leakage current Schottky diode according to claim 1, characterized in that, The substrate is an Al2O3 substrate with a thickness of 430μm-650μm and a surface roughness not exceeding 0.5nm; the planar layer has a thickness of 2.0μm-2.5μm, and is doped with Si ions at a doping concentration of 1×10⁻⁶. 19 cm -3 -5×10 19 cm -3 The boss height is 0.6μm-0.8μm; the doping type is consistent with the planar layer, and the concentration is not less than 1×10⁻⁶. 19 cm -3 The thickness of the N-type buried layer is 0.15 μm-0.3 μm, and the doping ion is Si with a doping concentration of 5 × 10⁻⁶. 18 cm -3 -1×10 19 cm -3 The thickness of the second N-type GaN layer is 4.5 μm-5.0 μm; the dopant ion is Si, and the doping concentration is 1×10⁻⁶. 16 cm -3 -5×10 17 cm -3 The back ohmic electrode is made of a Ti, Ni, and Au composite layer with thicknesses of 20 nm, 50 nm, and 200 nm, respectively, and its contact resistance after annealing does not exceed 1 × 10⁻⁻⁻⁶. 5 Ω·cm².

3. The low leakage current Schottky diode according to claim 1, characterized in that, The equivalent doping concentration of Mg after activation is 1×10¹ 8 cm -3 -5×10¹ 8 cm -3 The lateral width of the JTE region is 35μm-45μm.

4. The low leakage current Schottky diode according to claim 1, characterized in that, The first contact layer is made of Ni with a thickness of 80nm-100nm; the first metal layer is made of Au with a thickness of 500nm-800nm; the Schottky electrode contact interface barrier height is not less than 1.05eV; the second contact layer is a composite layer of Ti, Al, and Ni with thicknesses of 20nm, 120nm, and 40nm, respectively; the second metal layer is made of Al with a thickness of 800nm; the specific contact resistance after annealing does not exceed 5×10⁻⁶. -6 Ω·cm².

5. The low leakage current Schottky diode according to claim 1, characterized in that, The gap between the JTE region and the Schottky electrode is 6μm-8μm; the gap between the JTE region and the front ohmic electrode is 6μm-8μm.

6. The low leakage current Schottky diode according to claim 1, characterized in that, The composite passivation layer comprises a bottom layer and a top layer. The equivalent dielectric constant of the composite passivation layer does not exceed 6.5, and the interface state density does not exceed 5 × 10⁻⁶. 11 cm -2 ·eV -1 The passivation layer does not cover the central region of the Schottky contact, but only covers the edge range of 5μm-10μm.

7. A method for fabricating a low-leakage Schottky diode as described in any one of claims 1 to 6, characterized in that, The preparation method includes: A first N-type GaN layer, an N-type buried layer, and a second N-type GaN layer were sequentially epitaxially grown on a substrate. The first N-type GaN layer was grown using MOCVD at a temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The N-type buried layer was grown at the same temperature of 1050℃, a pressure of 150 Torr, a V / III ratio of 3000, and a growth rate of 1 μm / h, with SiH4 introduced as the dopant source to control the concentration. The second N-type GaN layer was grown using MOCVD at a temperature of 1040℃, a pressure of 120 Torr, a V / III ratio of 3500, with SiH4 as the dopant source but at a lower flow rate than that used in the first N-type GaN layer, and a concentration range of 1 × 10⁻⁶. 16 -5×10 17 cm -3 SiH4 is used as a doping source to control the concentration, and the target of control is the concentration of Si. The first and second N-type GaN layers were etched using ICP-RIE dry etching. The etching gases included Cl2, BCl3, and Ar, with flow rates of 15 sccm, 5 sccm, and 10 sccm, respectively. The RF power was 120 W, the ICP power was 600 W, and the etching rate was 300-450 nm / min. The resulting bosses had a height of 0.6 μm-0.8 μm and a sidewall tilt angle of 88°-90°. A SiO2 hard mask was used as the template to cover the area outside the JTE region for Mg ion implantation; the implantation energy was 150 keV and the dose was 1.5 × 10⁻⁶. 14 cm -2 and 5×10 13 cm -2 It adopts a two-window horizontal gradient design, with the edge windows extending outward by 35μm-45μm; High-temperature annealing activates Mg ions and N-type buried layers; annealing parameters: temperature 1250℃, time 30min, pressure atmospheric pressure, protective gas nitrogen with a flow rate of 5L / min, heating rate 25℃ / min, cooling rate 15℃ / min. The SiO2 hard mask was removed using the HF wet method, and the electrode was deposited by electron beam evaporation. The removal parameters were: HF solution concentration of 5% and immersion time of 60s. TiN, Ni, and Au were deposited sequentially to form a contact layer, followed by annealing to form a stable contact layer. The annealing parameters were: temperature 400℃, annealing time 30s, protective gas nitrogen with a flow rate of 5L / min. The thickness of TiN was 10nm, the thickness of Ni was 80nm-100nm, and the thickness of Au was 500nm-800nm. Ti, Al and Ni are evaporated, then Al is covered and annealed to form a low-resistance ohmic contact. The annealing parameters are: temperature 500℃, annealing time: 30s, protective gas is nitrogen, flow rate is 5L / min. Evaporation of Ti, Ni, and Au followed by annealing yields a Schottky diode.

8. The method for fabricating a low-leakage Schottky diode according to claim 7, characterized in that, The preparation method further includes: The device edge is formed by single ICP dry etching at an angle of 30°-40°, and the etching depth penetrates the second N-type GaN layer to the sidewall of the boss.

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