PHEMT devices and methods of making the same

Abstract

This invention discloses a PHEMT device, comprising: a GaAs substrate; an AlGaAs lower barrier layer disposed on the GaAs substrate; an InGaAs channel layer stacked on the AlGaAs lower barrier layer; a perovskite reinforcement layer stacked on the InGaAs channel layer; an AlGaAs upper barrier layer stacked on the perovskite reinforcement layer; and a GaAs ohmic contact layer stacked on the AlGaAs upper barrier layer. The PHEMT device and its fabrication method of this invention have at least one of the following advantages: 1. The perovskite reinforcement layer and the InGaAs channel layer form an alternating band structure, generating a band shift, thereby producing a built-in electric field and strengthening electron confinement; 2. The perovskite reinforcement layer can reduce the interface dislocation density and improve the two-dimensional electron gas mobility of the channel; 3. The defect passivation effect of the perovskite reinforcement layer can reduce the interface state density and suppress carrier scattering; 4. The perovskite reinforcement layer can suppress deep-level defects in AlGaAs, enabling the device to maintain performance at 200°C.

Description

Technical Field

[0001] This invention belongs to the field of compound semiconductor device technology, specifically, it relates to a GaAs-based PHEMT device that enhances the two-dimensional electron gas performance through perovskite material and its preparation method. Background Technology

[0002] PHEMT (Pseudomodulated high electron mobility transistor), also known as Pseudomodulated doped heterojunction field-effect transistor (PMODFET), is an improved structure of the traditional high electron mobility transistor (HEMT). Through heterojunction design optimization, this device solves the problem of temperature-dependent fluctuations in the two-dimensional electron gas concentration caused by "DX center" traps in HEMTs, thus improving stability and high-frequency performance.

[0003] Traditional GaAs-based PHEMTs rely on InGaAs / AlGaAs heterostructures to form a two-dimensional electron gas (2DEG), but their mobility is limited by interface scattering and impurity doping, typically ranging from 6000 to 8500 cm⁻¹. 2 / V·s。 Although the channel can be optimized by increasing the In composition, the following problems still exist: 1. Interface defects lead to carrier scattering, reducing mobility; 2. The polarization effect is limited, making it difficult to increase the 2DEG concentration; 3. Poor high-temperature stability limits the device's operating conditions. Summary of the Invention

[0004] To address at least one of the aforementioned technical problems in the prior art, embodiments of the present invention provide a GaAs-based PHEMT device with enhanced two-dimensional electron gas properties through perovskite materials and a method for its fabrication.

[0005] A PHEMT device provided according to one aspect of an embodiment of the present invention includes: a GaAs substrate; an AlGaAs lower barrier layer disposed on the GaAs substrate; an InGaAs channel layer stacked on the AlGaAs lower barrier layer; a perovskite reinforcement layer stacked on the InGaAs channel layer; an AlGaAs upper barrier layer stacked on the perovskite reinforcement layer; and a GaAs ohmic contact layer stacked on the AlGaAs upper barrier layer.

[0006] In one example of the PHEMT device provided above, the PHEMT device further includes a GaAs buffer layer disposed between the GaAs substrate and the AlGaAs lower barrier layer.

[0007] In one example of the PHEMT device provided above, the material of the perovskite reinforcement layer is SrHfO3 or BaSnO3.

[0008] In one example of the PHEMT device provided above, the In composition in the InGaAs channel layer is 0.30-0.42.

[0009] A method for fabricating a PHEMT device according to one aspect of an embodiment of the present invention includes: providing a GaAs substrate; forming an AlGaAs lower barrier layer on the GaAs substrate; forming an InGaAs channel layer stacked on the AlGaAs lower barrier layer; forming a perovskite reinforcement layer stacked on the InGaAs channel layer; forming an AlGaAs upper barrier layer stacked on the perovskite reinforcement layer; and forming a GaAs ohmic contact layer stacked on the AlGaAs upper barrier layer.

[0010] In one example of the method for fabricating a PHEMT device provided above, before forming an AlGaAs lower barrier layer on the GaAs substrate, the method further includes: forming a GaAs buffer layer stacked on the GaAs substrate.

[0011] In one example of the method for fabricating a PHEMT device provided above, the fabrication of an AlGaAs lower barrier layer on the GaAs substrate includes: fabricating an AlGaAs lower barrier layer stacked on the GaAs buffer layer.

[0012] In one example of the fabrication method of the PHEMT device provided above, the material of the perovskite reinforcement layer is SrHfO3 or BaSnO3.

[0013] In one example of the fabrication method of the PHEMT device provided above, the In composition in the InGaAs channel layer is 0.30-0.42.

[0014] In one example of the fabrication method of the PHEMT device provided above, after fabricating the GaAs ohmic contact layer stacked on the AlGaAs barrier layer, the fabrication method further includes: performing thermal annealing on each of the formed layers.

[0015] Beneficial effects: Compared with the prior art, the PHEMT device and its fabrication method according to embodiments of the present invention have at least one of the following advantages:

[0016] 1. The perovskite reinforcement layer and the InGaAs channel layer form an alternating band structure, which generates a band shift, thereby creating a built-in electric field and strengthening electron confinement.

[0017] 2. The perovskite reinforcement layer can reduce the interface dislocation density and improve the two-dimensional electron gas mobility of the channel.

[0018] 3. The defect passivation effect of the perovskite reinforcement layer can reduce the interface state density and suppress carrier scattering;

[0019] 4. The perovskite reinforcement layer can suppress deep-level defects in AlGaAs, enabling the device to maintain its performance at 200°C. Attached Figure Description

[0020] The above and other aspects, features, and advantages of embodiments of the present invention will become clearer from the following description taken in conjunction with the accompanying drawings, in which:

[0021] Figure 1 This is a schematic diagram of the structure of a PHEMT device according to an embodiment of the present invention;

[0022] Figure 2 This is a flowchart of a method for fabricating a PHEMT device according to an embodiment of the present invention;

[0023] Figure 3 This is a comparison chart of the 2DEG mobility of a PHEMT device according to an embodiment of the present invention and a conventional PHEMT device. Detailed Implementation

[0024] Hereinafter, specific embodiments of the present invention will be described in detail with reference to the accompanying drawings. However, the present invention can be implemented in many different forms, and should not be construed as limited to the specific embodiments set forth herein. Rather, these embodiments are provided to explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the various embodiments of the invention and various modifications suitable for particular intended applications.

[0025] As used herein, the term "comprising" and its variations are open terms meaning "including but not limited to". The terms "based on", "according to", etc., mean "at least partially based on" or "at least partially based on". The terms "embodiment", "an example", "an embodiment", and "an embodiment" mean "at least one embodiment". The terms "first", "second", etc., may refer to different or the same objects. Other definitions, whether explicit or implicit, may be included below. Unless explicitly indicated by the context, the definition of a term remains consistent throughout the specification.

[0026] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related are omitted.

[0027] Figure 1 This is a schematic diagram of the structure of a PHEMT device according to an embodiment of the present invention.

[0028] Reference Figure 1 According to an embodiment of the present invention, the PHEMT device comprises, from bottom to top: a GaAs substrate 100; a GaAs buffer layer 110 stacked on the GaAs substrate 100; an AlGaAs lower barrier layer 120 stacked on the GaAs buffer layer 110; an InGaAs channel layer 130 stacked on the AlGaAs lower barrier layer 120; a perovskite reinforcement layer 140 stacked on the InGaAs channel layer 130; an AlGaAs upper barrier layer 150 stacked on the perovskite reinforcement layer 140; and a GaAs ohmic contact layer 160 stacked on the AlGaAs upper barrier layer 150.

[0029] GaAs substrate 100 is a semi-insulating GaAs substrate with a thickness of 500 μm.

[0030] The GaAs buffer layer 110 is unintentionally doped and has a thickness of 300-500 nm. In this embodiment, the GaAs buffer layer 110 is disposed between the GaAs substrate 100 and the subsequent epitaxial layer. It alleviates lattice mismatch stress through homogeneous epitaxy, absorbs defects such as native dislocations and microcracks in the GaAs substrate 100, and prevents them from extending into the subsequent epitaxial layer (especially the InGaAs channel layer 130). Simultaneously, the GaAs buffer layer 110 optimizes surface flatness, providing a foundation for high-quality growth of the subsequent epitaxial layer, thereby suppressing the interference of GaAs substrate 100 defects on the device's electrical performance and improving channel electron mobility and stability. In another embodiment of the invention, the GaAs buffer layer 110 may be absent, but this is not the preferred option.

[0031] The Al composition in the AlGaAs lower barrier layer 120 is 0.2-0.3, and its thickness is 200-500 nm.

[0032] The InGaAs channel layer 130 has an In composition of 0.3-0.4 and a thickness of 10-15 nm. Furthermore, the InGaAs channel layer 130 is pseudo-matched.

[0033] The perovskite reinforcement layer 140 is made of SrHfO3 or BaSnO3 and has a thickness of 2-5 nm. In this embodiment, the perovskite reinforcement layer 140 (i.e., abrupt heterojunction) is formed by MOCVD growth. Therefore, by utilizing the ferroelectric polarization effect of the perovskite reinforcement layer 140, positive charge accumulation is induced at the interface, thereby increasing the 2DEG concentration.

[0034] The Al composition of the AlGaAs barrier layer 150 is 0.2-0.3%, and its thickness is 30-50 nm. Furthermore, the AlGaAs barrier layer 150 is Si δ-doped with a doping concentration of 1 × 10⁻⁶. 12 –3×10 12 cm -3.

[0035] The Si doping concentration in the GaAs ohmic contact layer 160 is 1×10⁻⁶. 19 cm -3 Its thickness is 100-200nm.

[0036] In the PHEMT device according to an embodiment of the present invention, the perovskite reinforcement layer 140 and the InGaAs channel layer 130 form a type II band alignment, thereby generating a built-in electric field and thus enhancing electron confinement.

[0037] Furthermore, the perovskite reinforcement layer 140 alleviates the lattice mismatch stress between InGaAs and AlGaAs through lattice buffering, reducing dislocation nucleation caused by stress concentration. Secondly, the defect passivation function of the perovskite reinforcement layer 140 can absorb dislocation outcrops or microcracks at the interface, preventing dislocations from extending into the channel layer. Finally, the stable chemical bonds formed between the perovskite reinforcement layer 140 and the upper and lower layers can optimize the atomic arrangement at the interface, suppressing dislocation movement and multiplication. Therefore, the perovskite reinforcement layer 140 can reduce the dislocation density at the interface and improve the two-dimensional electron gas mobility in the channel.

[0038] Furthermore, since the interface between the InGaAs channel layer 130 and the perovskite reinforcement layer 140 is a critical region for carrier transport, defects at the interface can form interface states. These interface states trap carriers, preventing them from transporting freely, increasing nonradiative recombination, and thus reducing the device's current gain and output power. The high lattice matching and strong coordination ability of the perovskite material in the perovskite reinforcement layer 140 effectively passivates these defects. This passivation significantly reduces the interface state density, decreasing carrier trapping and recombination, and increasing the effective carrier concentration. In addition, during carrier transport in the InGaAs channel layer 130, defect states act as scattering centers, altering the carrier's direction and energy, leading to a decrease in carrier mobility. The perovskite's defect passivation reduces the number of defects at the interface and in the bulk phase, thereby reducing the number of scattering centers. This reduction in defects lengthens the mean free path of carriers, increasing mobility. Higher mobility means that charge carriers can pass through the InGaAs channel layer 130 more quickly, reducing propagation delay and improving the switching speed and high-frequency performance of the device.

[0039] Furthermore, the polar functional groups of the perovskite reinforcement layer 140 interact with the uncoordinated Ga on the AlGaAs surface. 3+ / Al 3+ Forming coordination bonds or hydrogen bonds fills defect sites, reduces deep-level trap density, and decreases carrier trapping. Furthermore, the perovskite reinforcement layer 140 (whose composition can be tuned) achieves lattice matching with AlGaAs, alleviating interfacial stress and suppressing Al2O3 at high temperatures. 3+ with Ga 3+ Phase separation and defect proliferation. The high thermal decomposition temperature of perovskite prevents water and oxygen erosion, and its low ion mobility inhibits Al2O3 degradation. 3+ The perovskite reinforcement layer 140 inhibits the generation and proliferation of deep-level defects in AlGaAs, maintains the stability of the heterojunction interface, and ensures efficient carrier transport at high temperatures. This, in turn, maintains key performance parameters such as device current gain and output power, enabling stable operation at 200°C.

[0040] The following describes in detail the fabrication method of the PHEMT device according to an embodiment of the present invention. Figure 2 This is a flowchart of a method for fabricating a PHEMT device according to an embodiment of the present invention.

[0041] PHEMT devices according to embodiments of the present invention are fabricated using an MOCVD apparatus. See also... Figure 1 and Figure 2 In fabrication step S210, a GaAs substrate 100 is provided.

[0042] Specifically, the reaction chamber of the MOCVD equipment is heated to 600°C and the reaction chamber pressure is 50 mbar to perform thermal cleaning (600°C, 10 minutes) on the GaAs substrate 100 to remove the surface oxides of the GaAs substrate 100.

[0043] In step S220, a GaAs buffer layer 110 is formed and stacked on the GaAs substrate 100. It should be noted that, as described above, when the GaAs buffer layer 110 is not present, step S220 is also absent.

[0044] Specifically, a GaAs buffer layer 110 with a thickness of, for example, 350 nm is grown at 580°C.

[0045] In step S230, an AlGaAs lower barrier layer 120 is formed and stacked on the GaAs buffer layer 110. It should be noted that when step S220 is not present, the AlGaAs lower barrier layer 120 is directly formed and stacked on the GaAs substrate 100.

[0046] In step S240, an InGaAs channel layer 130 is formed on the AlGaAs lower barrier layer 120.

[0047] Specifically, the reaction chamber temperature is lowered to 500°C to grow, for example, a 300 nm thick InGaAs channel layer 130, the material being In... 0.38 Ga 0.62 As.

[0048] In step S250, a perovskite reinforcement layer 140 is formed on the InGaAs channel layer 130.

[0049] Specifically, the reaction chamber temperature was lowered to 400°C, and Sr and Hf were introduced to grow a 5 nm thick SrHfO3 layer (growth rate of 0.01 nm / s) in an As atmosphere to form a perovskite reinforcement layer 140.

[0050] In step S260, an AlGaAs upper barrier layer 150 is fabricated on the perovskite reinforcement layer 140. Specifically, a 50 nm thick AlGaAs upper barrier layer 150 is grown. 0.25 Ga 0.75 An As layer is used as a barrier layer on AlGaAs 150.

[0051] In step S270, a GaAs ohmic contact layer 160 is fabricated on the AlGaAs upper barrier layer 150. Specifically, a GaAs ohmic contact layer 160 with a thickness of 150 nm is grown.

[0052] In step S280, each layer formed is subjected to thermal annealing.

[0053] Specifically, annealing at 600°C for 1 minute in nitrogen optimizes the interface properties. Therefore, step S280 is a preferred method for optimizing interface properties. In another embodiment of the invention, step S280 may be omitted.

[0054] The following describes in detail the fabrication process of a PHEMT device using a conventional structure, which can serve as a comparative example of a PHEMT device according to an embodiment of the present invention.

[0055] In the comparative examples, the fabrication method of the traditional PHEMT device includes:

[0056] Step S1, Substrate treatment: The MOCVD reaction chamber is heated to 600°C and the reaction chamber pressure is 50mbar. The GaAs substrate is thermally cleaned (600°C, 10 minutes) to remove surface oxides.

[0057] Step S2, Buffer layer growth: A 350 nm GaAs buffer layer is grown at 580°C;

[0058] Step S3: Growing Al on the GaAs buffer layer 0.25 Ga 0.75 As the lower barrier layer;

[0059] In step S4, the reaction chamber temperature is reduced to 500℃ to grow 300nm In atoms. 0.38 Ga 0.62 As channel layer;

[0060] Step S5: Cool to 400°C and grow 50nm Al. 0.25 Ga 0.75 As barrier layer (Si δ doped).

[0061] Step S6: Grow a 150nm GaAs cap layer;

[0062] Step S7, post-annealing: Anneal at 600°C for 1 minute in nitrogen to optimize interface properties.

[0063] Figure 3 This is a comparison chart of the 2DEG mobility of a PHEMT device according to an embodiment of the present invention and a conventional PHEMT device (comparative example).

[0064] Reference Figure 3 Traditional PHEMT devices rely on InGaAs / AlGaAs heterojunctions to form a two-dimensional electron gas, but their mobility is limited by interface scattering and impurity doping, typically ranging from 6000 to 8500 cm⁻¹ at room temperature. 2 / V·s; The PHEMT device according to embodiments of the present invention enhances the 2DEG confinement capability by modulating the band structure through the polarization field of the perovskite layer, achieving a high-mobility, high-stability two-dimensional electron gas channel. The 2DEG mobility reaches 10,000–12,000 cm⁻¹ at room temperature. 2 / V·s, and the perovskite polarization field increases the 2DEG concentration to greater than or equal to 2×10⁻⁶. 12 cm -2 .

[0065] In summary, the PHEMT device and its fabrication method according to embodiments of the present invention have at least one of the following advantages:

[0066] 1. The perovskite reinforcement layer and the InGaAs channel layer form an alternating band structure, which generates a band shift, thereby creating a built-in electric field and strengthening electron confinement.

[0067] 2. The perovskite reinforcement layer can reduce the interface dislocation density and improve the two-dimensional electron gas mobility of the channel.

[0068] 3. The defect passivation effect of the perovskite reinforcement layer can reduce the interface state density and suppress carrier scattering;

[0069] 4. The perovskite reinforcement layer can suppress deep-level defects in AlGaAs, enabling the device to maintain its performance at 200°C.

[0070] The optional embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the embodiments of the present invention are not limited to the specific details in the above embodiments. Within the scope of the technical concept of the embodiments of the present invention, various simple modifications can be made to the technical solutions of the embodiments of the present invention, and these simple modifications all fall within the protection scope of the embodiments of the present invention.

Claims

1. A PHEMT device, characterized in that, include: GaAs substrate; An AlGaAs lower barrier layer is disposed on the GaAs substrate; An InGaAs channel layer is stacked on the AlGaAs lower barrier layer; A perovskite reinforcement layer is stacked on the InGaAs channel layer; An AlGaAs barrier layer is stacked on the perovskite reinforcement layer; GaAs ohmic contact layer, stacked on the AlGaAs upper barrier layer; The perovskite reinforcement layer is made of SrHfO3 or BaSnO3, and the In composition in the InGaAs channel layer is 0.30-0.

42.

2. The PHEMT device according to claim 1, characterized in that, Also includes: A GaAs buffer layer is disposed between the GaAs substrate and the AlGaAs lower barrier layer.

3. A method for fabricating a PHEMT device, characterized in that, The manufacturing method includes: Provide a GaAs substrate; An AlGaAs lower barrier layer is formed on the GaAs substrate. An InGaAs channel layer is fabricated on the AlGaAs lower barrier layer; A perovskite reinforcement layer is fabricated and stacked on the InGaAs channel layer; An AlGaAs barrier layer is fabricated on the perovskite reinforcement layer; A GaAs ohmic contact layer is fabricated on the AlGaAs barrier layer; The perovskite reinforcement layer is made of SrHfO3 or BaSnO3, and the In composition in the InGaAs channel layer is 0.30-0.

42.

4. The manufacturing method according to claim 3, characterized in that, Before forming an AlGaAs lower barrier layer on the GaAs substrate, the fabrication method further includes: forming a GaAs buffer layer stacked on the GaAs substrate.

5. The manufacturing method according to claim 4, characterized in that, The step of forming an AlGaAs lower barrier layer on the GaAs substrate includes: forming an AlGaAs lower barrier layer stacked on the GaAs buffer layer.

6. The manufacturing method according to any one of claims 3-5, characterized in that, After fabricating the GaAs ohmic contact layer stacked on the AlGaAs barrier layer, the fabrication method further includes: performing thermal annealing on each of the formed layers.

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