A clock throttling management method based on double register configuration

Abstract

The application provides a clock current-limiting management method based on a double register configuration, and the implementation steps include: defining a clock as a periodic pulse, and numbering the periodic pulse in a "0, 1,..., N-1" cycle; configuring an [N-1:0] bit current-limiting parameter register, each bit corresponding to a numbered pulse, and storing a "pass / cut" rule; configuring a start register to realize the shutdown of a current-limiting mechanism and the start of a new parameter taking effect; and generating a clock gating sequence by using two registers to output, so as to control the on-off of the clock pulse, thereby realizing periodic and non-periodic regulation. The application can accurately adjust power consumption and data rate through dynamic management of the clock pulse, has high regulation accuracy, does not affect other modules, occupies few resources in a large-scale ASIC, is simple to operate, and has wide application prospects.

Description

Technical Field

[0001] This invention relates to the field of clock circuit control, and more particularly to a clock current limiting management method based on a dual-register configuration. Background Technology

[0002] With the rapid iteration of SOC (System-on-a-Chip) and ASIC (Application-Specific Integrated Circuit) technologies, the integration of chip functions continues to improve, and its scale is growing exponentially. This is accompanied by a significant increase in chip power consumption. For every order of magnitude increase in chip size, power consumption often needs to increase simultaneously to maintain the stable operation of each module. This not only poses a severe challenge to the battery life of devices (especially mobile terminals and IoT devices), but also increases the complexity and cost of hardware design due to the increased heat dissipation requirements. This has become a core bottleneck restricting the development of SOC and ASIC chips towards miniaturization and low power consumption.

[0003] To alleviate power consumption pressure, traditional solutions in the industry often use frequency division and reduction to adjust the clock frequency, that is, to reduce switching losses and dynamic power consumption by reducing the clock rate of specific functional modules. However, this approach has several unavoidable problems in practical applications: First, each time the frequency is adjusted, a fixed reset-de-reset process must be performed on the target module—first, the module is reset to its initial state to avoid data corruption caused by frequency switching, and then the reset and working parameters are loaded again after the adjustment is completed. This process interrupts the normal operation of the module, which can easily lead to data loss or service delays in scenarios with high real-time requirements (such as industrial control and high-definition data transmission). Second, frequency adjustment relies on PLLs (phase-locked loops) to generate the target frequency. However, the number of PLLs in the chip is limited by area, cost, and power supply resources, and can usually only cover the core high frequency or commonly used frequency, which cannot meet the differentiated needs of all functional modules. For example, some low-speed peripherals require low-frequency clocks below 1MHz, while high-performance computing units require GHz-level high-frequency clocks. The limited number of PLLs cannot cover all frequency points in all scenarios. During the design, it is necessary to repeatedly coordinate the working modes of different modules (such as time-division multiplexing of PLLs and sacrificing the performance of some modules), which greatly reduces the flexibility of system design.

[0004] More importantly, increasing the number of PLLs in pursuit of frequency adjustment flexibility will directly lead to a simultaneous expansion of the scale of supporting hardware such as frequency divider circuits and clock control logic within the chip. Each additional PLL requires the design of a corresponding frequency divider, clock switching switch, and signal buffer unit. This not only occupies more chip area but also introduces new power sources and signal interference risks, creating a contradictory situation of "increasing power consumption for the sake of reducing power consumption," which runs counter to the goal of low power consumption design.

[0005] Meanwhile, data flow management of SOCASIC chips faces another challenge: the data flow rates of various functional modules differ significantly under different operating modes (such as standby mode, light load mode, and heavy load mode). For example, in standby mode, only a small number of control signals need to be transmitted, and the rate can be as low as Kbps; while under heavy load (such as video encoding / decoding and big data processing), the data flow rate needs to be increased to Gbps to meet bandwidth requirements. Throughout the data path, the rate matching between upstream and downstream modules (such as sensor-processor-memory) directly determines the bus bandwidth utilization: if the upstream rate is higher than the downstream rate, data will accumulate on the bus, causing buffer overflow; if the upstream rate is lower than the downstream rate, bus resources will be idle, reducing data processing efficiency.

[0006] Current solutions often balance speed by configuring module operating modes in software (such as adjusting data interface bit width and enabling caching). However, due to limitations in software response latency and inherent hardware characteristics, the adjustment precision and real-time performance are difficult to meet requirements. In fact, clock speed is the fundamental factor affecting data flow rate—every step of data transmission and processing relies on clock synchronization, and the clock speed directly determines the amount of data that a module can process per unit time. Therefore, precise and dynamic control of the clock speed is the most effective means to achieve flexible adaptation of data flow rate and balance bus bandwidth requirements.

[0007] In summary, the inherent defects of traditional frequency division and reduction schemes, along with the practical need for data flow rate regulation, have jointly driven the industry to seek a more efficient and flexible clock control technology to solve the power consumption and speed management challenges of SOCASIC chips. Summary of the Invention

[0008] This invention reads the output signals of two registers through hardware circuitry, generates a gating sequence synchronized with the clock, and then controls the passage or cut-off of clock pulses according to the sequence, ultimately achieving the goal of dynamically adjusting power consumption and data rate without affecting the operation of other modules.

[0009] This invention provides a clock current limiting management method based on a dual-register configuration, characterized by comprising: The periodic clock pulses are numbered cyclically as 0, 1, 2, ..., N-1, 0, 1, 2..., where N is the total number of pulses contained in one clock sequence period and N is a positive integer greater than or equal to 1. Configure a current limiting parameter register with a bit width of [N-1:0], so that each bit of the current limiting parameter register corresponds one-to-one with each clock pulse in a single clock sequence period, and the level state of the bit determines the output state of the corresponding clock pulse; Write the current limiting parameters into the current limiting parameter register; Configure the startup register to enable or disable the clock current limiting control mechanism; A gating sequence is generated using the current limiting parameter register and the start register; The output clock is controlled to pass through or be cut off by a gating sequence; The startup register is configured to perform the following operations: When the disable enable bit is 1, the clock current limiting control mechanism is disabled, and the original clock pulse passes through without restriction; or When the enable bit is 1, the current limiting parameters take effect and the clock current limiting control mechanism is activated. Both the disable enable bit and the enable enable bit are specific bits; The generation of the clock gating sequence through the current limiting parameter register and the start register includes: Synchronously read the current value of the current limiting parameter register and the current state of the start register; When the start enable bit is 1, if the register bit corresponding to the current pulse number in the current limiting parameter register is 1, a high-level signal is generated; if the corresponding register bit is 0, a low-level signal is generated, and a gating sequence is generated in the order of pulse numbers. When the enable bit is 1, a full high-level gating sequence is generated to ensure that all pulses pass through normally; The control of the output clock through the gating sequence to pass or cut off includes: When the gate sequence signal is high, the clock buffer is turned on, and the original clock pulse is output to the subsequent module normally. When the gate sequence signal is low, the clock buffer is turned off, the output remains low, and the corresponding clock pulse is blocked.

[0010] In one embodiment of the present invention, the gating sequence is configured for periodic or aperiodic regulation: When the bit signals in the current limiting parameter register are set at power-of-2 intervals, the gating sequence will periodically allow a specific proportion of pulses to pass through; or When the bit signals in the current limiting parameter register have no fixed interval, the gating sequence will allow any number of pulses to pass through.

[0011] The present invention also provides a clock current limiting circuit based on the above method, comprising: The current limiting parameter register is configured to store the current limiting parameters of the clock current limiting control mechanism; The startup register is configured to control the start / stop state of the clock current limiting mechanism; A clock-gated sequence generation circuit, configured to generate clock-gated sequences; and A clock gating unit is configured to control the passage or interruption of the output clock according to a clock gating sequence.

[0012] The present invention has the following beneficial effects: (1) The current limiting parameter register is designed with a bit width of "[N-1:0]" (N is preferred to be a power of 2, such as N=32) to achieve a precise association of "each bit corresponds to a numbered clock pulse". The pulse "cut-off / pass-through" rule can be flexibly set by configuring the bit level state (0 / 1).

[0013] (2) The startup register has dual functions of "disabling the current limiting mechanism" and "starting the new parameter to take effect", and avoids functional conflicts through hardware mutual exclusion logic. On the one hand, when temporary bypass current limiting control is required (such as when the chip needs to run at full speed under heavy load), the startup register can be used to quickly disable the mechanism to ensure that the original clock is output without delay; on the other hand, after the new current limiting parameter is written, it needs to be triggered to take effect through the startup register to avoid abnormal clock fluctuations during the parameter update process.

[0014] (3) By implementing clock pulse management through hardware, the power consumption and data throughput rate of the corresponding functional modules in the SOCASIC chip can be dynamically adjusted. This can not only cope with the power consumption surge caused by the increase in chip size, but also match the data flow rate changes under different working modes, balance the bandwidth requirements of the front and rear bus of the data path, and effectively solve the limitations of the traditional frequency division and reduction method. Attached Figure Description

[0015] Figure 1 A flowchart of a clock current limiting management method based on dual register configuration in one embodiment of the present invention is shown; Figure 2 A waveform diagram of a periodically adjusted clock is shown in one embodiment of the present invention; and Figure 3 The diagram shows a non-periodic adjustable clock waveform according to an embodiment of the present invention. Detailed Implementation

[0016] In the following description, the invention is described with reference to various embodiments. However, those skilled in the art will recognize that the embodiments may be practiced without one or more specific details or with other alternatives and / or additional methods, materials, or components. In other instances, well-known structures, materials, or operations are not shown or described in detail so as not to obscure the inventive points of the invention. Similarly, for illustrative purposes, specific quantities, materials, and configurations are set forth to provide a comprehensive understanding of embodiments of the invention. However, the invention is not limited to these specific details.

[0017] In this invention, the various embodiments are merely intended to illustrate the solutions of the invention and should not be construed as limiting.

[0018] In this specification, references to "an embodiment" or "this embodiment" mean that a particular feature, structure, or characteristic described in connection with that embodiment is included in at least one embodiment of the invention. The phrase "in one embodiment" appearing throughout this specification does not necessarily refer to the same embodiment in all instances.

[0019] Furthermore, the numbering of the steps in the methods of the present invention does not limit the execution order of the method steps. Unless otherwise specified, the method steps may be executed in different orders.

[0020] The present invention will be further described below with reference to the accompanying drawings and specific embodiments.

[0021] Figure 1 A flowchart of a clock current limiting management method based on dual register configuration in one embodiment of the present invention is shown.

[0022] like Figure 1 As shown, in one embodiment of the present invention, the clock current limiting management method based on dual register configuration includes the following steps: The S100 clock pulse basic definition and numbering rules set clearly define the clock as a series of periodically repeating pulse signals. Its periodicity is the core characteristic that ensures the synchronous operation of each module of the SOC. All subsequent current limiting control revolves around "whether the pulse passes through".

[0023] Each clock pulse is assigned a unique number in a cyclical order of "0, 1, 2, ..., N-1, 0, 1, 2...", where N is the maximum range of pulse numbers (i.e., the total number of pulses contained in one control cycle). N can be any positive integer greater than or equal to 1. The value of N is optimized according to computer language conventions: N is preferentially chosen to be a power of 2 (such as 16, 32, 64, etc.). In this embodiment, N=32 (i.e., 2^36, 3^36, 3^4, 3^36 ... 5 Taking this as an example, this value can simplify the subsequent design of register bit width, parameter calculation logic and hardware circuit implementation, and reduce circuit complexity and operation latency.

[0024] The S200 current limiting parameter register is configured to store the rules for "which pulses are allowed to pass," and is the core basis for current limiting control. Based on the N value set in step S100, configure a current limiting parameter register with a width of [N-1:0]. For example, when N=32, the register width is 31:0, a total of 32 bits, ensuring that each bit of the register corresponds one-to-one with a pulse number, thereby achieving precise management of "one bit controlling one pulse". Each bit of the register is explicitly bound to a clock pulse with the same number, such as Bit0 corresponding to pulse 0, Bit1 corresponding to pulse 1, ... Bit31 corresponding to pulse 31. The level state (0 or 1) of the bit directly determines the output state of the corresponding numbered pulse. Write current limiting parameters to this register through the SOC's control interface (such as AXI or APB bus). The parameter value needs to be set according to the actual power consumption or data rate requirements. For example, if you need to reduce power consumption by 50%, you can set it to allow only 16 pulses to pass through, corresponding to register 16 bits being 1 and 16 bits being 0.

[0025] The S300 startup register is configured to control the start / stop status and parameter update timing of the current limiting mechanism. Two core functions must be assigned to the startup register, and the triggering conditions for these functions must be clearly defined: When the clock current limiting control mechanism is disabled, and the enable bit is 1 (i.e., a specific bit is set to 1), the clock current limiting mechanism stops working, and the clock pulse is output normally without restriction, which is equivalent to a free-running clock.

[0026] To enable the new current limiting parameters and start the current limiting function, when the current limiting rules need to be updated, first write the new parameters to the current limiting parameter register, and then trigger the loading of the new parameters and start the current limiting mechanism through the specific trigger conditions of the start register, such as when the start enable bit is 1, to ensure that the clock does not run out during the parameter update process.

[0027] The number of register bits needs to be determined based on the number of functions and triggering logic. For example, a 2-bit register can cover core scenarios such as closing, starting new parameters, and maintaining the current state. At the same time, state latching logic needs to be designed, such as by using a D flip-flop, to avoid external signal interference causing erroneous changes in the register state and to ensure the stability of the current limiting mechanism.

[0028] The S400 generates a clock gating sequence and synchronously reads the current value of the current limiting parameter register (pulse passing rules) and the current state of the start register (mechanism start / stop instructions). These two signals are the only input basis for generating the gating sequence. It is necessary to ensure the synchronization of signal reading to avoid mismatch between rules and instructions due to delay.

[0029] The input signals of the two registers are processed by combinational logic circuits or sequential logic circuits: when the enable bit is 1, if the register bit corresponding to the current pulse number in the current limiting parameter register is 1, a high-level signal is generated; if the corresponding register bit is 0, a low-level signal is generated, and the pulses are arranged in order to form a gating sequence. When the disable bit is 1, a gating sequence of all high levels is generated to ensure that all pulses pass normally.

[0030] The period of the gating sequence is consistent with the N value in step S100. For example, when N=32, the gating sequence repeats once every 32 pulse cycles to ensure that the current limiting rule is executed stably in each control cycle.

[0031] To avoid the generation of abnormally narrow pulses due to the phase difference between the gating sequence and the clock pulse causing the pulse edge to be out of sync with the control signal edge, a synchronization circuit is needed to align the phase of the gating sequence and the clock signal. This ensures that the gating action is accurately applied to the effective edge of the pulse and avoids timing violations in subsequent modules.

[0032] The S500 clock output control uses a clock gating unit to control the clock pulse via a gating sequence. The input to the clock gating unit is the original clock pulse and the gating sequence generated in step S400. When the gating sequence outputs "allow," the original clock pulse is output normally; when the gating sequence outputs "cut off," the clock gating unit blocks the original pulse and outputs a low level.

[0033] The clock current limiting mechanism of this invention includes periodic regulation and non-periodic regulation: Figure 2 The diagram shows a periodically adjusted clock waveform according to an embodiment of the present invention.

[0034] In one embodiment of the present invention, such as Figure 2 As shown, when the bit states of the current limiting parameter register are set at power-of-2 intervals, such as only Bit0, Bit2, Bit4... being set to 1, frequency control of frequency*1 / 2ⁿ is achieved. That is, when n=1, 1 / 2 pulses pass through, and the frequency drops to 1 / 2 of the original frequency; when n=3, 1 / 8 pulses pass through, and the frequency drops to 1 / 8 of the original frequency.

[0035] Figure 3 The diagram shows a non-periodic adjustable clock waveform according to an embodiment of the present invention.

[0036] like Figure 3 As shown, when the bit states of the current limiting parameter register are not set at fixed intervals, such as only Bit0, Bit1, Bit2, and Bit31 being set to 1, flexible frequency control of frequency*(1~32) / 32 can be achieved. For example, when 4 pulses are allowed to pass through, the frequency is 4 / 32=1 / 8 of the original frequency; when 31 pulses are allowed to pass through, the frequency is 31 / 32 of the original frequency.

[0037] In extreme scenarios where all pulses are cut off, it is necessary to determine the working state of the downstream modules at this time, such as complete power failure, low-power standby, or sleep state that maintains register data, to avoid data loss or functional abnormality caused by clock interruption.

[0038] In one embodiment of the present invention, a clock current limiting circuit based on the above method is further included, comprising: The current limiting parameter register is configured to store the current limiting parameters of the clock current limiting control mechanism; The startup register is configured to control the start / stop state of the clock current limiting mechanism; A clock-gated sequence generation circuit, configured to generate clock-gated sequences; and A clock gating unit is configured to control the output of clock pulses according to a clock gating sequence.

[0039] The table below shows the relationship between current limiting parameters and power control rate in this embodiment: Although various embodiments of the invention have been described above, it should be understood that they are presented by way of example only and not as limitations. It will be apparent to those skilled in the art that various combinations, modifications, and alterations can be made without departing from the spirit and scope of the invention. Therefore, the breadth and scope of the invention disclosed herein should not be limited by the exemplary embodiments disclosed above, but should be defined solely by the appended claims and their equivalents.

Claims

1. A clock current limiting management method based on dual-register configuration, characterized in that, include: The periodic clock pulses are numbered cyclically as 0, 1, 2, ..., N-1, 0, 1, 2..., where N is the total number of pulses contained in one clock sequence period and N is a positive integer greater than or equal to 1. Configure a current limiting parameter register with a bit width of [N-1:0], so that each bit of the current limiting parameter register corresponds one-to-one with each clock pulse in a single clock sequence period, and the level state of the bit determines the output state of the corresponding clock pulse; Write the current limiting parameters into the current limiting parameter register; Configure the startup register to enable or disable the clock current limiting control mechanism; A gating sequence is generated using the current limiting parameter register and the start register; The output clock is controlled to pass through or be cut off by a gating sequence; The startup register is configured to perform the following operations: When the disable enable bit is 1, the clock current limiting control mechanism is disabled, and the original clock pulse passes through without restriction; or When the enable bit is 1, the current limiting parameters take effect and the clock current limiting control mechanism is activated. Both the disable enable bit and the enable enable bit are specific bits; The generation of the clock gating sequence through the current limiting parameter register and the start register includes: Synchronously read the current value of the current limiting parameter register and the current state of the start register; When the start enable bit is 1, if the register bit corresponding to the current pulse number in the current limiting parameter register is 1, a high-level signal is generated; if the corresponding register bit is 0, a low-level signal is generated, and a gating sequence is generated in the order of pulse numbers. When the enable bit is 1, a full high-level gating sequence is generated to ensure that all pulses pass through normally; The control of the output clock through the gating sequence to pass or cut off includes: When the gate sequence signal is high, the clock buffer is turned on, and the original clock pulse is output to the subsequent module normally. When the gate sequence signal is low, the clock buffer is turned off, the output remains low, and the corresponding clock pulse is blocked.

2. The method according to claim 1, characterized in that, The gating sequence is configured for periodic or aperiodic regulation: When the bit signals in the current limiting parameter register are set at power-of-2 intervals, the gating sequence will periodically allow a specific proportion of pulses to pass through; or When the bit signals in the current limiting parameter register have no fixed interval, the gating sequence will allow any number of pulses to pass through.

3. A clock current limiting circuit based on the method of any one of claims 1-2, characterized in that, include: The current limiting parameter register is configured to store the current limiting parameters of the clock current limiting control mechanism; The startup register is configured to control the start / stop state of the clock current limiting mechanism; A clock-gated sequence generation circuit, configured to generate clock-gated sequences; as well as A clock gating unit is configured to control the passage or interruption of the output clock according to a clock gating sequence.

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