Method, apparatus, electronic device and storage medium for adjusting power consumption

Abstract

This disclosure provides a method, apparatus, electronic device, and storage medium for adjusting power consumption, relating to the field of chips. The main technical features include: obtaining the computing frequencies corresponding to a master chip and a slave chip respectively; determining the frequency deviation value between the master chip and the slave chip; when the frequency deviation value is greater than a preset target frequency deviation value, determining the power consumption adjustment amount corresponding to the master chip and the slave chip respectively based on the frequency deviation value; determining the target power consumption corresponding to the master chip and the slave chip respectively based on the power consumption adjustment amount; adjusting the power consumption of the master chip and the slave chip to the target power consumption corresponding to the master chip and the slave chip respectively, so that the frequency deviation between the master chip and the slave chip is controlled within the preset target frequency deviation value, improving the synergy of parallel computing between the master and slave chips, and improving the overall system performance.

Description

Technical Field

[0001] This disclosure relates to the field of chips, and more particularly to a method, apparatus, electronic device, and storage medium for adjusting power consumption. Background Technology

[0002] As computing clusters demand higher computing density and system integration, high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) computing cards with a single-card dual-chip architecture have been widely used. They integrate two computing chips on a single card, reducing server slot usage and improving the system integration of computing clusters.

[0003] However, in a single-card dual-core architecture, the two computing chips share a power supply, and there are process deviations in the chip manufacturing process. In a dual-chip parallel computing scenario, even under the same power consumption conditions, the computing frequencies of the two chips will still differ, resulting in poor synchronization of dual-chip task processing. The chip with the higher computing frequency has to wait for the low-frequency chip after completing its own task, causing the computing unit of the high-frequency chip to be idle, which limits the overall computing performance of the system. Summary of the Invention

[0004] This disclosure provides a method, apparatus, electronic device, and storage medium for adjusting power consumption. Its main purpose is to solve the problems of poor synchronization, idle computing units, and limited system performance caused by frequency differences during parallel computing in a single-card dual-chip architecture in the prior art.

[0005] According to a first aspect of this disclosure, a method for adjusting power consumption is provided, comprising:

[0006] Obtain the computing frequencies corresponding to the master chip and the slave chip respectively, and determine the frequency deviation value between the master chip and the slave chip;

[0007] If the frequency deviation value is greater than the preset target frequency deviation value, the power consumption adjustment amount corresponding to the main chip and the slave chip is determined based on the frequency deviation value.

[0008] The target power consumption of the master chip and the slave chip is determined based on the power consumption adjustment amount corresponding to the master chip and the slave chip respectively.

[0009] The power consumption of the master chip and the slave chip is adjusted to the target power consumption corresponding to the master chip and the slave chip, respectively.

[0010] In some embodiments, determining the power consumption adjustment amounts corresponding to the master chip and the slave chip respectively based on the frequency deviation value includes:

[0011] The basic adjustment range is determined based on the magnitude of the frequency deviation value; wherein the frequency deviation value is positively correlated with the basic adjustment range.

[0012] The compensation adjustment amount is determined based on the accumulated historical frequency deviation value;

[0013] The correction adjustment amount is determined by predicting the deviation trend based on the rate of change of the frequency deviation value.

[0014] The power consumption adjustment amounts corresponding to the master chip and the slave chip are obtained based on the basic adjustment range, the compensation adjustment amount, and the correction adjustment amount; wherein the power consumption adjustment amounts corresponding to the master chip and the slave chip have the same value and opposite adjustment directions.

[0015] In some embodiments, obtaining the computing frequencies corresponding to the master chip and the slave chip respectively, and determining the frequency deviation value between the master chip and the slave chip, includes:

[0016] The clock module collects the respective computing frequencies of the master chip and the slave chip.

[0017] The absolute value of the difference between the calculated frequencies corresponding to the master chip and the slave chip is calculated to obtain the frequency deviation value.

[0018] In some embodiments, after obtaining the computing frequencies corresponding to the master chip and the slave chip respectively, and determining the frequency deviation value between the master chip and the slave chip, the method further includes:

[0019] The power consumption of the main chip and the slave chip is collected by a power consumption monitor.

[0020] In some embodiments, determining the target power consumption corresponding to the master chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the master chip and the slave chip respectively includes:

[0021] The power consumption of the master chip and the slave chip are added together with their respective power consumption adjustment amounts to obtain the target power consumption of the master chip and the slave chip respectively.

[0022] In some embodiments, adjusting the power consumption of the master chip and the slave chip to the target power consumption corresponding to each of the master chip and the slave chip includes:

[0023] The master chip and the slave chip adjust their respective power consumption to their respective target power consumption by adjusting their respective operating voltage and computing frequency.

[0024] According to a second aspect of this disclosure, an apparatus for adjusting power consumption is provided, comprising:

[0025] The first determining unit is used to obtain the calculation frequencies corresponding to the main chip and the slave chip respectively, and to determine the frequency deviation value between the main chip and the slave chip;

[0026] The second determining unit is used to determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value when the frequency deviation value is greater than the preset target frequency deviation value.

[0027] The third determining unit is used to determine the target power consumption corresponding to the main chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the main chip and the slave chip respectively;

[0028] An adjustment unit is used to adjust the power consumption of the main chip and the slave chip to the target power consumption corresponding to the main chip and the slave chip, respectively.

[0029] In some embodiments, the second determining unit includes:

[0030] The first determining module is used to determine the basic adjustment range based on the magnitude of the frequency deviation value; wherein the frequency deviation value is positively correlated with the basic adjustment range;

[0031] The second determining module is used to determine the compensation adjustment amount based on the accumulated historical frequency deviation value;

[0032] The third determining module is used to predict the deviation trend based on the rate of change of the frequency deviation value and determine the correction adjustment amount.

[0033] The fourth determining module is used to obtain the power consumption adjustment amount corresponding to the master chip and the slave chip respectively based on the basic adjustment range, the compensation adjustment amount and the correction adjustment amount; wherein the power consumption adjustment amount corresponding to the master chip and the slave chip respectively has the same value and the adjustment direction is opposite.

[0034] In some embodiments, the first determining unit includes:

[0035] The acquisition module is used to acquire the computing frequencies of the main chip and the slave chip respectively through the clock module;

[0036] The fifth determining module is used to calculate the absolute value of the difference between the calculated frequencies corresponding to the main chip and the slave chip, and obtain the frequency deviation value.

[0037] In some embodiments, the apparatus further includes:

[0038] The acquisition unit is used to acquire the calculation frequencies corresponding to the master chip and the slave chip respectively after the first determining unit acquires the frequency deviation value between the master chip and the slave chip, and then acquires the power consumption corresponding to the master chip and the slave chip respectively through the power consumption monitor.

[0039] In some embodiments, the third determining unit is further configured to add the power consumption corresponding to the master chip and the slave chip respectively to their respective power consumption adjustment amounts to obtain the target power consumption corresponding to the master chip and the slave chip respectively.

[0040] In some embodiments, the adjustment unit is further configured to adjust the power consumption of the master chip and the slave chip to their respective target power consumption by adjusting their respective operating voltages and computing frequencies.

[0041] According to a third aspect of this disclosure, an electronic device is provided, comprising:

[0042] At least one processor; and

[0043] A memory communicatively connected to the at least one processor; wherein,

[0044] The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method described in the first aspect above.

[0045] According to a fourth aspect of this disclosure, a non-transitory computer-readable storage medium is provided storing computer instructions, wherein the computer instructions are configured to cause the computer to perform the method described in the first aspect above.

[0046] According to a fifth aspect of this disclosure, a computer program product is provided, comprising a computer program that, when executed by a processor, implements the method described in the first aspect above.

[0047] In summary, compared with related technologies, the solution disclosed herein can determine the frequency deviation between the master chip and the slave chip by obtaining their respective computing frequencies; if the frequency deviation is greater than a preset target frequency deviation, the power consumption adjustment amount corresponding to the master chip and the slave chip is determined based on the frequency deviation; then, the target power consumption corresponding to the master chip and the slave chip is determined based on the power consumption adjustment amount corresponding to the master chip and the slave chip; finally, the power consumption of the master chip and the slave chip is adjusted to their respective target power consumption, so that the frequency deviation between the master chip and the slave chip is controlled within the preset target frequency deviation value, thereby improving the synergy of parallel computing between the master and slave chips and improving the overall system performance.

[0048] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of this application, nor is it intended to limit the scope of this application. Other features of this application will become readily apparent from the following description. Attached Figure Description

[0049] The accompanying drawings are provided to better understand this solution and do not constitute a limitation of this disclosure. Wherein:

[0050] Figure 1 This is a flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure;

[0051] Figure 2 This is a flowchart illustrating another method for adjusting power consumption provided in an embodiment of this disclosure;

[0052] Figure 3 This is a flowchart illustrating another method for adjusting power consumption provided in an embodiment of this disclosure;

[0053] Figure 4 This is a flowchart illustrating another method for adjusting power consumption provided in an embodiment of this disclosure;

[0054] Figure 5 This is a flowchart illustrating another method for adjusting power consumption provided in an embodiment of this disclosure;

[0055] Figure 6 This is a flowchart illustrating another method for adjusting power consumption provided in an embodiment of this disclosure;

[0056] Figure 7 This is a schematic diagram of the structure of a power consumption adjustment device provided in an embodiment of the present disclosure;

[0057] Figure 8 A schematic diagram of another device for adjusting power consumption provided in an embodiment of this disclosure;

[0058] Figure 9 This is a schematic block diagram of an example electronic device provided in an embodiment of this disclosure. Detailed Implementation

[0059] The exemplary embodiments of this disclosure are described below with reference to the accompanying drawings, including various details of the embodiments to aid understanding, and should be considered merely exemplary. Therefore, those skilled in the art will recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of this disclosure. Similarly, for clarity and brevity, descriptions of well-known functions and structures are omitted in the following description.

[0060] The following description, with reference to the accompanying drawings, outlines a method, apparatus, electronic device, and storage medium for adjusting power consumption according to embodiments of the present disclosure.

[0061] Figure 1 This is a flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure.

[0062] like Figure 1 As shown, the method includes steps 101-104.

[0063] Step 101: Obtain the calculation frequency corresponding to the master chip and the slave chip respectively, and determine the frequency deviation value between the master chip and the slave chip.

[0064] In some embodiments, the computing units of the master chip and slave chip in a single-card dual-core architecture are first determined. The computing frequencies of the master chip's computing unit and the slave chip's computing unit are then collected using a frequency acquisition component associated with the computing unit (including but not limited to a clock module built into the chip). After acquisition, the absolute value of the difference between the master chip's computing frequency and the slave chip's computing frequency is calculated; this absolute value is the frequency deviation between the master chip and the slave chip. It should be noted that the embodiments of this disclosure are also applicable to single-card multi-core architectures, and the number of slave chips is not limited.

[0065] The above method can accurately obtain the calculation frequency of the master chip and the slave chip, and obtain the frequency deviation value reflecting the performance difference between the two by calculating the absolute value of the difference, providing basic data support for subsequent judgment on whether power consumption adjustment is needed.

[0066] Step 102: If the frequency deviation value is greater than the preset target frequency deviation value, determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value.

[0067] In some embodiments, a target frequency deviation value is preset according to the actual application scenario. The preset target frequency deviation value can be a fixed value or a preset value range. The specific preset value of the target frequency deviation value is not limited in the embodiments of this disclosure.

[0068] The frequency deviation value obtained in step 101 is compared with the preset target frequency deviation value. If the frequency deviation value is greater than the preset target frequency deviation value, the power consumption adjustment amount corresponding to the master chip and the slave chip is determined based on the magnitude of the frequency deviation value by means of a proportional-integral-derivative (PID) controller, including but not limited to.

[0069] Using the above method, the power consumption adjustment amount can be determined based on the magnitude of the frequency deviation, providing accurate adjustment parameters for subsequent determination of the target power consumption.

[0070] Step 103: Determine the target power consumption of the master chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the master chip and the slave chip respectively.

[0071] In some embodiments, the current power consumption of the main chip and the current power consumption of the slave chip are obtained, and the current power consumption of the main chip is added to the power consumption adjustment amount corresponding to the main chip to obtain the target power consumption of the main chip; at the same time, the current power consumption of the slave chip is added to the power consumption adjustment amount corresponding to the slave chip to obtain the target power consumption of the slave chip.

[0072] Using the above method, the target power consumption that the master chip and slave chip need to achieve can be calculated based on their current power consumption and their respective power consumption adjustment amounts, providing a target basis for subsequent power consumption adjustments.

[0073] Step 104: Adjust the power consumption of the main chip and the slave chip to the target power consumption corresponding to the main chip and the slave chip respectively.

[0074] In some embodiments, the master chip and slave chip, based on their respective target power consumption, adjust their operating voltage and computing frequency to gradually approach and reach the target power consumption. Specifically, the chip's power consumption is related to its operating voltage and computing frequency. When it is necessary to increase power consumption to reach the target power consumption, the operating voltage can be appropriately increased while simultaneously increasing the computing frequency; conversely, when it is necessary to decrease power consumption to reach the target power consumption, the operating voltage can be appropriately decreased while simultaneously decreasing the computing frequency. Adjusting only the computing frequency without adjusting the operating voltage will lead to abnormal chip operation or failure to reach the target power consumption: when it is necessary to increase the computing frequency to improve power consumption, if the operating voltage is not increased accordingly, the chip will experience calculation errors, data verification failures, or even operational interruptions due to insufficient power supply, making it unable to stably maintain a high-frequency state; when it is necessary to decrease the computing frequency to reduce power consumption, if the operating voltage is not decreased accordingly, although the chip can maintain low-frequency operation, excessively high voltage will lead to an increase in ineffective power consumption (power consumption is proportional to the square of the voltage), making it impossible for the actual power consumption to be reduced to the target power consumption, and the excess power consumption will be converted into heat, affecting the chip's lifespan and system stability.

[0075] By using the above method, the power consumption of the master chip and the slave chip can be adjusted to their respective target power consumption, thereby reducing the frequency deviation between them and ensuring the synergy of parallel computing between the two chips.

[0076] In summary, the power consumption adjustment method provided in this disclosure can determine the frequency deviation between the master chip and the slave chip by obtaining their respective computing frequencies; if the frequency deviation is greater than a preset target frequency deviation, the power consumption adjustment amount corresponding to the master chip and the slave chip is determined based on the frequency deviation; then, the target power consumption corresponding to the master chip and the slave chip is determined based on the power consumption adjustment amount; finally, the power consumption of the master chip and the slave chip is adjusted to their respective target power consumption, so that the frequency deviation between the master chip and the slave chip is controlled within the preset target frequency deviation value, thereby improving the synergy of parallel computing between the master and slave chips and improving the overall system performance.

[0077] Figure 2 A flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 102. Figure 2 This may include the following steps:

[0078] Step 201: Determine the basic adjustment range based on the magnitude of the frequency deviation value; wherein the frequency deviation value is positively correlated with the basic adjustment range.

[0079] In some embodiments, a correspondence between frequency deviation values ​​and basic adjustment amplitude is pre-established. This correspondence can be determined through chip factory test data, and may take the form of, but is not limited to, a correspondence table or a fitting formula. For example, a pre-defined correspondence table records: when the frequency deviation value is 0.1 GHz, the basic adjustment amplitude is 2 W; when the frequency deviation value is 0.15 GHz, the basic adjustment amplitude is 3.5 W; when the frequency deviation value is 0.2 GHz, the basic adjustment amplitude is 5 W. The larger the frequency deviation value, the larger the basic adjustment amplitude, and the frequency deviation value and the basic adjustment amplitude are positively correlated. The frequency deviation value obtained in step 101 can be used to determine the basic adjustment amplitude in the current scenario by querying the correspondence table or substituting it into the fitting formula. The above is only an illustrative example and is not a limitation on the specific values ​​of the frequency deviation value and the basic adjustment amplitude.

[0080] Step 202: Determine the compensation adjustment amount based on the accumulated historical frequency deviation value.

[0081] In some embodiments, the historical frequency deviation value refers to the frequency deviation value calculated by all steps 101 within a preset number of times (such as the first 5 times, the first 10 times, etc.) before the current adjustment period, or the frequency deviation value calculated by all steps 101 within a preset time window (such as the first 10 seconds, the first 30 seconds, etc.) before the current adjustment period. Specifically, the acquisition of the historical frequency deviation value is not limited in the embodiments of this disclosure.

[0082] These historical frequency deviation values ​​are accumulated using methods including, but not limited to, summation and weighted summation. For example, if the first three historical frequency deviation values ​​are 0.19 GHz, 0.18 GHz, and 0.17 GHz, the accumulated value obtained by summation is 0.54 GHz; if the weights of the first three deviation values ​​are 0.3, 0.3, and 0.4 respectively, the accumulated value obtained by weighted summation is... The above is merely an illustrative example and not a limitation on the specific calculation method for historical frequency deviation values.

[0083] The compensation adjustment amount is determined according to the preset correspondence rule between the cumulative historical frequency deviation value and the compensation adjustment amount to eliminate the static error caused by the long-term small frequency deviation. For example, the rule is: when the cumulative historical frequency deviation value is greater than 0.5 GHz, the compensation adjustment amount is +0.5W; when the cumulative historical frequency deviation value is between 0.4 and 0.5 GHz, the compensation adjustment amount is +0.3W; when the cumulative historical frequency deviation value is less than 0.4 GHz, the compensation adjustment amount is +0.1W. The above is only an example and is not a limitation on the specific correspondence rule between the cumulative historical frequency deviation value and the compensation adjustment amount.

[0084] Step 203: Determine the correction adjustment amount based on the rate of change of the frequency deviation value to predict the deviation trend.

[0085] In some embodiments, the frequency deviation value of the current adjustment period and the frequency deviation value of the previous adjustment period are obtained, the difference between the two is calculated, and then divided by the time interval between the two adjustment periods to obtain the rate of change of the frequency deviation value. The deviation trend is predicted based on the rate of change, and a correction adjustment amount is determined based on the predicted deviation trend. The correction adjustment amount not only needs to reflect the adjustment direction through positive and negative values, but also needs to reflect the adjustment strength through the magnitude of the absolute value, and the magnitude of the absolute value needs to be related to the absolute value of the rate of change. Specifically, the larger the absolute value of the rate of change (the more drastic the deviation change), the larger the absolute value of the correction adjustment amount; the smaller the absolute value of the rate of change (the more gradual the deviation change), the smaller the absolute value of the correction adjustment amount. At the same time, the absolute value of the correction adjustment amount must not exceed a preset maximum threshold (e.g., ...). To avoid system oscillations due to excessively large correction magnitudes, the following measures can be taken: For example, if the rate of change is +20MHz / adjustment period (the deviation increases rapidly), the basic adjustment magnitude determined in step 201 may be significantly insufficient, and the correction adjustment amount can be set to +3W (positive value with a large absolute value) to enhance the adjustment strength; if the rate of change is +5MHz / adjustment period (the deviation increases slowly), the correction adjustment amount can be set to +1W (positive value with a small absolute value); if the rate of change is -15MHz / adjustment period (the deviation decreases rapidly), the basic adjustment magnitude determined in step 201 may be excessive, and the correction adjustment amount can be set to -2.5W (negative value with a large absolute value) to suppress over-adjustment; if the rate of change is -3MHz / adjustment period (the deviation decreases slowly), the correction adjustment amount can be set to -0.5W (negative value with a small absolute value); if the rate of change is close to 0 (the deviation is stable), the correction adjustment amount is set to 0. These are merely illustrative examples and not limitations on specific correction adjustment amounts.

[0086] Step 204: Obtain the power consumption adjustment amounts corresponding to the master chip and the slave chip respectively based on the basic adjustment range, the compensation adjustment amount, and the correction adjustment amount; wherein the power consumption adjustment amounts corresponding to the master chip and the slave chip have the same value and opposite adjustment directions.

[0087] In some embodiments, a preset comprehensive calculation method is used to process the basic adjustment range, compensation adjustment amount, and correction adjustment amount. The comprehensive calculation method includes, but is not limited to, direct addition of the three, weighted addition, etc. The direction of the power consumption adjustment amount is determined according to the frequency of the master chip and the slave chip: if the current calculation frequency of the master chip is higher than that of the slave chip, the power consumption adjustment amount of the master chip is set to a negative value (reducing power consumption to reduce frequency), and the power consumption adjustment amount of the slave chip is set to a positive value (increasing power consumption to increase frequency); if the current calculation frequency of the master chip is lower than that of the slave chip, the power consumption adjustment amount of the master chip is set to a positive value, and the power consumption adjustment amount of the slave chip is set to a negative value, while the values ​​remain the same.

[0088] By combining the current frequency deviation value, the cumulative historical frequency deviation value, and the changing trend of the frequency deviation value, the power consumption adjustment amount can be determined from multiple dimensions. This ensures that the adjustment force is adapted to the current frequency deviation, eliminates static errors, and avoids adjustment oscillations. At the same time, by using constraints with the same value and opposite adjustment directions, the total power consumption of the master chip and slave chip is kept stable.

[0089] Figure 3 A flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure is further shown. Based on Figure 1 The illustrated embodiment further explains step 101. Figure 3 This may include the following steps:

[0090] Step 301: Collect the calculation frequency of the main chip and the slave chip respectively through the clock module.

[0091] In some embodiments, both the master chip and the slave chip are configured with independent clock modules. These clock modules include, but are not limited to, a phase-locked loop (PLL) clock module built into the chip, or an external crystal oscillator clock module bound to the chip's computing unit. Their core function is to provide a stable clock signal to the computing unit, and the computing frequency of the computing unit is consistent with the frequency of this clock signal. During data acquisition, the clock module monitors and outputs the frequency value corresponding to the current operating rhythm of the computing unit through signal interaction interfaces with the master chip's computing unit and the slave chip's computing unit; that is, the respective computing frequencies of the master chip and the slave chip.

[0092] Step 302: Calculate the absolute value of the difference between the calculated frequencies corresponding to the main chip and the slave chip respectively, and obtain the frequency deviation value.

[0093] In some embodiments, the calculation frequencies of the master chip and the slave chip, acquired in step 301, are obtained. Then, a difference calculation is performed on the two calculation frequencies. Finally, the absolute value of the difference is taken, which is the frequency deviation between the master chip and the slave chip. Taking the absolute value aims to focus only on the magnitude of the difference between the calculation frequencies of the master chip and the slave chip, without needing to distinguish which one has a higher calculation frequency, ensuring that the frequency deviation objectively reflects the degree of performance difference between the two chips.

[0094] Using the above method, the signal monitoring function of the clock module can be relied upon to obtain the calculation frequency of the master chip and the slave chip. Then, by performing absolute value calculation of the difference, the influence of positive and negative signs on the difference judgment can be eliminated, and an objective and reliable frequency deviation value can be obtained.

[0095] Figure 4 A flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure is further shown, such as... Figure 4 As shown, the method includes steps 401-405.

[0096] Step 401: Obtain the calculation frequency corresponding to the master chip and the slave chip respectively, and determine the frequency deviation value between the master chip and the slave chip.

[0097] Step 402: Collect the power consumption of the main chip and the slave chip respectively using a power consumption monitor.

[0098] In some embodiments, both the master chip and the slave chip are equipped with independent power consumption monitors. These monitors may include, but are not limited to, a power sampling module built into the chip or an external power detection device connected in series with the chip's power supply circuit. Their core function is to collect the actual power consumption consumed by the master chip's computing unit and the slave chip's computing unit during operation in real time. During the data collection process, the power consumption monitor detects the real-time current and voltage of the master chip's power supply circuit and, based on the calculation logic of power consumption = voltage × current, obtains the current power consumption of the master chip. Similarly, it detects the real-time current and voltage of the slave chip's power supply circuit to obtain the current power consumption of the slave chip. The data collection timing is synchronized with the frequency calculation timing in step 401 to ensure that the collected power consumption data of the master chip and slave chip correspond to the concurrent frequency calculation data, avoiding the impact of data timing misalignment on subsequent adjustment logic.

[0099] Step 403: If the frequency deviation value is greater than the preset target frequency deviation value, determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value.

[0100] Step 404: Determine the target power consumption of the master chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the master chip and the slave chip respectively.

[0101] Step 405: Adjust the power consumption of the main chip and the slave chip to the target power consumption corresponding to the main chip and the slave chip respectively.

[0102] For explanations of steps 401, 403 to 405, please refer to [link / reference needed]. Figure 1 The detailed description of the relevant steps will not be repeated here in the embodiments disclosed herein.

[0103] By using the above methods, it can be ensured that the calculated target power consumption matches the actual operating state of the chip, guaranteeing the accuracy and effectiveness of power consumption adjustment and providing a reliable data basis for adjusting power consumption to reduce frequency deviation.

[0104] Figure 5 A flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure is further shown, such as... Figure 5 As shown, the method includes steps 501-504.

[0105] Step 501: Obtain the calculation frequency corresponding to the master chip and the slave chip respectively, and determine the frequency deviation value between the master chip and the slave chip.

[0106] Step 502: If the frequency deviation value is greater than the preset target frequency deviation value, determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value.

[0107] Step 503: Add the power consumption and power consumption adjustment amount corresponding to the main chip and the slave chip respectively to obtain the target power consumption corresponding to the main chip and the slave chip respectively.

[0108] In some embodiments, based on step 502, the power consumption adjustment amounts corresponding to the main chip and the slave chip are determined, and the power consumption of the main chip and the slave chip is collected by a power consumption monitor. Specifically, the power consumption of the main chip and its corresponding power consumption adjustment amount are obtained and added together; the result is the target power consumption of the main chip. Similarly, the power consumption of the slave chip and its corresponding power consumption adjustment amount are obtained and added together; the result is the target power consumption of the slave chip. The sign of the power consumption adjustment amount indicates the adjustment direction: a positive value means the target power consumption needs to be increased from the current power consumption; a negative value means the target power consumption needs to be decreased from the current power consumption, ensuring that the sum of the current power consumption and the target power consumption are equal.

[0109] Step 504: Adjust the power consumption of the main chip and the slave chip to the target power consumption corresponding to the main chip and the slave chip respectively.

[0110] For explanations of steps 501, 502, and 504, please refer to [link / reference needed]. Figure 1 The detailed description of the relevant steps will not be repeated here in the embodiments disclosed herein.

[0111] The above methods clarify the specific targets for power consumption adjustment and prevent the total power consumption from exceeding the rated upper limit.

[0112] Figure 6 A flowchart illustrating a method for adjusting power consumption provided in an embodiment of this disclosure is further shown, such as... Figure 6 As shown, the method includes steps 601-604.

[0113] Step 601: Obtain the calculation frequency corresponding to the master chip and the slave chip respectively, and determine the frequency deviation value between the master chip and the slave chip.

[0114] Step 602: If the frequency deviation value is greater than the preset target frequency deviation value, determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value.

[0115] Step 603: Determine the target power consumption of the master chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the master chip and the slave chip respectively.

[0116] For explanations of steps 601 to 603, please refer to [link / reference needed]. Figure 1The detailed description of the relevant steps will not be repeated here in the embodiments disclosed herein.

[0117] Step 604: The main chip and the slave chip adjust their respective power consumption to their respective target power consumption by adjusting their respective operating voltage and computing frequency.

[0118] In some embodiments, both the master chip and the slave chip have independent voltage regulation modules and frequency regulation modules. The voltage regulation module is used to adjust the chip's operating voltage, and the frequency regulation module is used to adjust the chip's computing frequency. During the adjustment process, the master chip, based on its corresponding target power consumption, first determines the target operating voltage and target computing frequency required to achieve the target power consumption. The voltage regulation module adjusts the supply voltage according to the target operating voltage, and the frequency regulation module simultaneously adjusts the clock signal frequency according to the target computing frequency, so that the actual power consumption of the master chip gradually approaches the target power consumption. Similarly, the slave chip also determines the target operating voltage and target computing frequency based on its corresponding target power consumption, and then performs adjustments through its own voltage regulation module and frequency regulation module.

[0119] The above method reduces the frequency deviation between the two chips, thus ensuring the synergy of parallel computing between the two chips.

[0120] Corresponding to the above-described method for adjusting power consumption, the present invention also proposes a device for adjusting power consumption. Since the device embodiments of the present invention correspond to the above-described method embodiments, details not disclosed in the device embodiments can be referred to the above-described method embodiments, and will not be repeated here.

[0121] Figure 7 This is a schematic diagram of a device for adjusting power consumption provided in an embodiment of the present disclosure, as shown below. Figure 7 As shown, the device includes:

[0122] The first determining unit 71 is used to obtain the calculation frequency corresponding to the main chip and the slave chip respectively, and to determine the frequency deviation value between the main chip and the slave chip;

[0123] The second determining unit 72 is used to determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value when the frequency deviation value is greater than the preset target frequency deviation value.

[0124] The third determining unit 73 is used to determine the target power consumption corresponding to the main chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the main chip and the slave chip respectively;

[0125] The adjustment unit 74 is used to adjust the power consumption of the main chip and the slave chip to the target power consumption corresponding to the main chip and the slave chip respectively.

[0126] This device can determine the frequency deviation between the master chip and the slave chip by acquiring their respective computing frequencies. If the frequency deviation exceeds a preset target frequency deviation, it determines the power consumption adjustment amount for each chip based on the frequency deviation. Then, it determines the target power consumption for each chip based on the power consumption adjustment amount. Finally, it adjusts the power consumption of each chip to their respective target power consumption, keeping the frequency deviation within the preset target frequency deviation value, thereby improving the synergy of parallel computing between the master and slave chips and enhancing the overall system performance.

[0127] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8 As shown, the second determining unit 72 includes:

[0128] The first determining module 721 is used to determine the basic adjustment range based on the magnitude of the frequency deviation value; wherein the frequency deviation value is positively correlated with the basic adjustment range;

[0129] The second determining module 722 is used to determine the compensation adjustment amount based on the accumulated historical frequency deviation value;

[0130] The third determining module 723 is used to predict the deviation trend based on the rate of change of the frequency deviation value and determine the correction adjustment amount.

[0131] The fourth determining module 724 is used to obtain the power consumption adjustment amounts corresponding to the master chip and the slave chip respectively based on the basic adjustment range, the compensation adjustment amount and the correction adjustment amount; wherein the power consumption adjustment amounts corresponding to the master chip and the slave chip have the same value and opposite adjustment directions.

[0132] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8 As shown, the first determining unit 71 includes:

[0133] The acquisition module 711 is used to acquire the respective computing frequencies of the main chip and the slave chip through the clock module.

[0134] The fifth determining module 712 is used to calculate the absolute value of the difference between the calculated frequencies corresponding to the main chip and the slave chip respectively, so as to obtain the frequency deviation value.

[0135] Furthermore, in one possible implementation of the embodiments of this disclosure, such as Figure 8 As shown, the device further includes:

[0136] The acquisition unit 75 is used to acquire the power consumption of the main chip and the slave chip respectively through a power consumption monitor after the first determining unit 71 acquires the calculation frequency corresponding to the main chip and the slave chip respectively and determines the frequency deviation value between the main chip and the slave chip.

[0137] Furthermore, in one possible implementation of this disclosure, the third determining unit 73 is further configured to add the power consumption corresponding to the main chip and the slave chip respectively to their respective power consumption adjustment amounts to obtain the target power consumption corresponding to the main chip and the slave chip respectively.

[0138] Furthermore, in one possible implementation of this disclosure, the adjustment unit 74 is also used to adjust the power consumption of the main chip and the slave chip to their respective target power consumption by adjusting their respective operating voltages and calculation frequencies.

[0139] It should be noted that the foregoing explanation of the method embodiments also applies to the apparatus of the embodiments of this disclosure, and the principle is the same. Therefore, the embodiments of this disclosure are not limited thereto.

[0140] According to embodiments of this disclosure, this disclosure also provides an electronic device, a readable storage medium, and a computer program product.

[0141] Figure 9 A schematic block diagram of an example electronic device 900 that can be used to implement embodiments of the present disclosure is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device may also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0142] like Figure 9As shown, the electronic device 900 includes a computing unit 901, which can perform various appropriate actions and processes based on a computer program stored in ROM (Read-Only Memory) 902 or a computer program loaded from storage unit 908 into RAM (Random Access Memory) 903. The RAM 903 can also store various programs and data required for the operation of the electronic device 900. The computing unit 901, ROM 902, and RAM 903 are interconnected via bus 904. An I / O (Input / Output) interface 905 is also connected to bus 904.

[0143] Multiple components in electronic device 900 are connected to I / O interface 905, including: input unit 906, such as keyboard, mouse, etc.; output unit 907, such as various types of displays, speakers, etc.; storage unit 908, such as disk, optical disk, etc.; and communication unit 909, such as network card, modem, wireless transceiver, etc. Communication unit 909 allows electronic device 900 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0144] The computing unit 901 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 901 include, but are not limited to, CPUs (Central Processing Units), GPUs (Graphics Processing Units), various special-purpose AI (Artificial Intelligence) computing chips, various computing units running machine learning model algorithms, DSPs (Digital Signal Processors), and any suitable processor, controller, microcontroller, etc. The computing unit 901 performs the various methods and processes described above, such as methods for adjusting power consumption. For example, in some embodiments, the methods for adjusting power consumption may be implemented as computer software programs tangibly contained in a machine-readable medium, such as storage unit 908. In some embodiments, part or all of the computer program may be loaded and / or installed on the electronic device 900 via ROM 902 and / or communication unit 909. When the computer program is loaded into RAM 903 and executed by the computing unit 901, one or more steps of the methods described above may be performed. Alternatively, in other embodiments, the computing unit 901 may be configured to perform the aforementioned power consumption adjustment method by any other suitable means (e.g., by means of firmware).

[0145] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, FPGAs (Field Programmable Gate Arrays), ASICs (Application-Specific Integrated Circuits), ASSPs (Application-Specific Standard Products), SOCs (System-on-Chips), CPLDs (Complex Programmable Logic Devices), computer hardware, firmware, software, and / or combinations thereof. These various implementations may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0146] The program code used to implement the methods of this disclosure may be written in any combination of one or more programming languages. This program code may be provided to a processor or controller of a general-purpose computer, special-purpose computer, or other programmable data processing apparatus, such that when executed by the processor or controller, the program code causes the functions / operations specified in the flowcharts and / or block diagrams to be implemented. The program code may be executed entirely on a machine, partially on a machine, as a standalone software package partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0147] In the context of this disclosure, a machine-readable medium can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can be, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, RAM, ROM, EPROM (Electrically Programmable Read-Only Memory) or flash memory, optical fiber, CD-ROM (Compact Disc Read-Only Memory), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0148] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (Cathode-Ray Tube) or LCD (Liquid Crystal Display) monitor); and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the computer. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0149] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include LANs (Local Area Networks), WANs (Wide Area Networks), the Internet, and blockchain networks.

[0150] Computer systems can include clients and servers. Clients and servers are generally geographically separated and typically interact via communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. A server can be a cloud server, also known as a cloud computing server or cloud host, a hosting product within the cloud computing service system that addresses the shortcomings of traditional physical hosts and VPS (Virtual Private Server) services, such as high management difficulty and weak business scalability. Servers can also be servers for distributed systems or servers incorporating blockchain technology.

[0151] It's important to note that artificial intelligence (AI) is the study of enabling computers to simulate certain human thought processes and intelligent behaviors (such as learning, reasoning, thinking, and planning). It encompasses both hardware and software technologies. AI hardware technologies generally include sensors, dedicated AI chips, cloud computing, distributed storage, and big data processing. AI software technologies primarily include computer vision, speech recognition, natural language processing, machine learning / deep learning, big data processing, and knowledge graph technologies.

[0152] It should be understood that the various forms of processes shown above can be used to rearrange, add, or delete steps. For example, the steps described in this disclosure can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution disclosed in this disclosure can be achieved, and this is not limited herein.

[0153] The specific embodiments described above do not constitute a limitation on the scope of protection of this disclosure. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this disclosure should be included within the scope of protection of this disclosure.

Claims

1. A method for adjusting power consumption, characterized in that, The method is applied to scenarios where the master chip and slave chip share the same power supply, including: Obtain the computing frequencies corresponding to the master chip and the slave chip respectively, and determine the frequency deviation value between the master chip and the slave chip; If the frequency deviation value is greater than the preset target frequency deviation value, the power consumption adjustment amount corresponding to the main chip and the slave chip is determined based on the frequency deviation value. The target power consumption of the master chip and the slave chip is determined based on the power consumption adjustment amount corresponding to the master chip and the slave chip respectively. The power consumption of the main chip and the slave chip is adjusted to the target power consumption corresponding to the main chip and the slave chip respectively, so that the frequency deviation between the main chip and the slave chip is controlled within the preset target frequency deviation value; The step of determining the power consumption adjustment amounts corresponding to the master chip and the slave chip respectively based on the frequency deviation value includes: The basic adjustment range is determined based on the magnitude of the frequency deviation value; wherein the frequency deviation value is positively correlated with the basic adjustment range. The compensation adjustment amount is determined based on the accumulated historical frequency deviation value; The correction adjustment amount is determined by predicting the deviation trend based on the rate of change of the frequency deviation value. The power consumption adjustment amounts corresponding to the master chip and the slave chip are obtained based on the basic adjustment range, the compensation adjustment amount, and the correction adjustment amount; wherein the power consumption adjustment amounts corresponding to the master chip and the slave chip have the same value and opposite adjustment directions.

2. The method according to claim 1, characterized in that, The step of obtaining the respective computing frequencies of the master chip and the slave chip, and determining the frequency deviation value between the master chip and the slave chip, includes: The clock module collects the respective computing frequencies of the master chip and the slave chip. The absolute value of the difference between the calculated frequencies corresponding to the master chip and the slave chip is calculated to obtain the frequency deviation value.

3. The method according to claim 1, characterized in that, After obtaining the respective computing frequencies of the master chip and the slave chip, and determining the frequency deviation value between the master chip and the slave chip, the method further includes: The power consumption of the main chip and the slave chip is collected by a power consumption monitor.

4. The method according to claim 3, characterized in that, The step of determining the target power consumption corresponding to the master chip and the slave chip based on the power consumption adjustment amounts corresponding to the master chip and the slave chip respectively includes: The power consumption of the master chip and the slave chip are added together with their respective power consumption adjustment amounts to obtain the target power consumption of the master chip and the slave chip respectively.

5. The method according to claim 4, characterized in that, Adjusting the power consumption of the main chip and the slave chip to their respective target power consumption includes: The master chip and the slave chip adjust their respective power consumption to their respective target power consumption by adjusting their respective operating voltage and computing frequency.

6. A device for adjusting power consumption, characterized in that, The device is used in scenarios where the master chip and slave chip share the same power supply, including: The first determining unit is used to obtain the calculation frequencies corresponding to the main chip and the slave chip respectively, and to determine the frequency deviation value between the main chip and the slave chip; The second determining unit is used to determine the power consumption adjustment amount corresponding to the main chip and the slave chip respectively based on the frequency deviation value when the frequency deviation value is greater than the preset target frequency deviation value. The third determining unit is used to determine the target power consumption corresponding to the main chip and the slave chip respectively based on the power consumption adjustment amount corresponding to the main chip and the slave chip respectively; The adjustment unit is used to adjust the power consumption of the main chip and the slave chip to the target power consumption corresponding to the main chip and the slave chip respectively, so that the frequency deviation between the main chip and the slave chip is controlled within the preset target frequency deviation value; The step of determining the power consumption adjustment amounts corresponding to the master chip and the slave chip respectively based on the frequency deviation value includes: The basic adjustment range is determined based on the magnitude of the frequency deviation value; wherein the frequency deviation value is positively correlated with the basic adjustment range. The compensation adjustment amount is determined based on the accumulated historical frequency deviation value; The correction adjustment amount is determined by predicting the deviation trend based on the rate of change of the frequency deviation value. The power consumption adjustment amounts corresponding to the master chip and the slave chip are obtained based on the basic adjustment range, the compensation adjustment amount, and the correction adjustment amount; wherein the power consumption adjustment amounts corresponding to the master chip and the slave chip have the same value and opposite adjustment directions.

7. An electronic device, characterized in that, include: At least one processor; as well as A memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-5.

8. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause the computer to perform the method according to any one of claims 1-5.

9. A computer program product, characterized in that, Includes a computer program that, when executed by a processor, implements the method as described in any one of claims 1-5.

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