A hidden PUF device based on a memristor array and method of operation thereof

Abstract

The application belongs to the technical field of hardware security and microelectronic circuit, and specifically discloses a hidden PUF device based on a memristor array and an operation method thereof. In the first aspect, the application keeps all the memristor array in a high resistance state as a hidden state, and activates part of the units for a short time under the challenge, so as to realize a "hidden / activatable" working mode, effectively reduce static power consumption, and significantly improve the resistance to side channel detection and physical analysis. In the second aspect, the application uses the SET voltage threshold of the memristor as an entropy source, so that the selected units produce different switching results in a probabilistic manner under a fixed write pulse, thereby forming a high randomness response derived from the microstructure difference of the device, and improving the unpredictability and the anti-modeling attack capability. In the third aspect, the application introduces a digital readout structure composed of a reference current source and a current comparator, so as to realize a stable and low-power logic response without complex analog circuits.

Description

Technical Field

[0001] This application belongs to the field of hardware security and microelectronic circuit technology, and more specifically, relates to a hidden PUF device based on a memristor array and its operation method. Background Technology

[0002] With the rapid development of technologies such as the Internet of Things, artificial intelligence, and edge computing, information terminals and embedded devices are widely deployed in various application scenarios, leading to an increasing demand for hardware-level security protection. Traditional security mechanisms based on digital keys or storage encryption are vulnerable to copying, cracking, or tampering, making them difficult to effectively counter physical layer attacks.

[0003] Physically Unclonable Functions (PUFs) are security mechanisms that generate unique response characteristics based on the microscopic physical differences of devices. They are widely used in chip authentication, key generation, and anti-counterfeiting verification. Traditional PUFs are mostly implemented based on CMOS process circuit structures, such as delayed PUFs and voltage fluctuation PUFs. However, their randomness is limited by process variations and they are easily affected by environmental changes and side-channel attacks, resulting in low security and reconfigurability.

[0004] While existing memristor array-based plug-in functions (PUFs) possess high randomness and density, their security remains vulnerable. Because the conductivity and resistance distribution of a memristor array can be indirectly or directly measured using various physical detection methods (such as microscopic imaging, electrical probes, and side-channel analysis), attackers can reconstruct the internal physical distribution characteristics of the array, thereby inferring or replicating the PUF's response, leading to its compromise. Bin Gao et al. proposed a hidden PUF in their paper (Concealable physically unclonable function chip with a memristor array). The main idea is to apply a RESET voltage to the memristor in the read state, causing it to transition to a high-resistance state, and then measure its read current. This current is compared with a reference current to obtain a 1 or 0 response bit. In the hidden state, a SET voltage is applied to the memristor, causing it to transition to a low-resistance state. However, this approach has drawbacks: in the hidden state, all memristors are in a low-resistance state, resulting in high overall static power consumption. It requires error correction techniques such as multiple voting to reduce the bit error rate, further increasing overall power consumption and hindering the practical application of low-power secure terminals.

[0005] Therefore, there is an urgent need for a memristor PUF device that can achieve effective concealment while reducing static power consumption and avoiding reliance on high-overhead error correction methods, so as to further improve its security and practicality. Summary of the Invention

[0006] To address the shortcomings of existing technologies, the purpose of this application is to provide a hidden PUF device based on a memristor array and its operation method, aiming to solve the problems of insufficient security, high static power consumption in the hidden state, and increased energy consumption due to reliance on multiple voting technology in existing PUF devices.

[0007] To achieve the above objectives, in a first aspect, this application provides a hidden PUF device based on a memristor array, including a processing module, a memristor array, a reference current source, and a current comparator; wherein, The memristor array is composed of multiple independently addressable memristor cells. The initial state of each memristor cell is a high-resistance state, and the SET voltage threshold of each memristor cell is different in the high-resistance state. The reference current source is used to provide a stable reference current signal; The number of current comparators is equal to the number of columns in the memristor array. One end of each comparator is connected to the output terminal of the corresponding column of the memristor array, and the other end is connected to the reference current source. It is used to compare the magnitude of the column output current with the reference current signal and output logic level "1" or "0" to the processing module. The processing module is used to receive external challenge signals, apply challenge signals to the memristor array, cause some memristor units to change from a high-resistance state to a low-resistance state with a certain probability, obtain the output logic level of the current comparator, splice the logic signals to obtain the PUF response sequence, and then control the memristor array to return to the high-resistance state.

[0008] Preferably, the memristor unit adopts a 1T1R structure formed by a gating transistor and a memristor connected in series. The control terminal of the gating transistor is connected to the processing module to conduct when selected and turn off when not selected, thereby realizing unit-level addressing and current path control.

[0009] Preferably, the reference current source is configured to be greater than the high-resistivity current of the memristor and less than the low-resistivity current.

[0010] Preferably, the challenge signal is the median of the distribution of the memristor SET voltage threshold in the memristor array under the high impedance state of the memristor.

[0011] Preferably, the current comparator maps units with a conduction current greater than the reference current signal to logic "1", and units with a conduction current less than the reference current signal to logic "0".

[0012] Preferably, the processing module splices the output bits of each unit in the spatial order of the memristor array to generate a complete PUF response sequence. The length of the PUF response sequence is adaptively adjusted according to the number of selected memristor units and is not limited by a fixed number of bits.

[0013] Preferably, the processing module restores all memristor cells in the memristor array to a high-resistivity state by applying a RESET voltage to the memristor array.

[0014] Preferably, the processing module is further configured to generate challenge-response pairs during the registration and authentication phases respectively, thereby achieving unique identity authentication of the device.

[0015] Preferably, the concealable PUF device is integrated with an external security processor, encryption module and / or communication interface to build a security chip or trusted hardware system.

[0016] To achieve the above objectives, in a second aspect, this application provides a method for operating the hidden PUF device based on a memristor array as described in the first aspect, comprising: Excitation phase: Receive external challenge signals and apply challenge signals to the memristor array, causing some memristor cells to change from a high-resistivity state to a low-resistivity state with a certain probability; Reading phase: Obtain the output logic level of the current comparator, concatenate the logic signals to obtain the PUF response sequence; Hidden phase: Control the memristor array to return to a high-resistivity state.

[0017] It is understandable that the beneficial effects of the second aspect mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0018] Overall, the technical solutions conceived in this application have the following beneficial effects compared with the prior art: This application provides a hidden PUF device based on a memristor array, comprising: a memristor array composed of multiple independently addressable memristor cells, wherein the initial state of each memristor cell is a high-resistivity state, and the SET voltage threshold of each memristor cell differs in the high-resistivity state; a reference current source for providing a stable reference current signal; a number of current comparators equal to the number of columns of the memristor array, each comparator having one end connected to the output terminal of the corresponding column of the memristor array and the other end connected to the reference current source, for comparing the magnitude of the column output current with the reference current signal, and outputting a logic level "1" or "0" to a processing module; and a processing module for receiving an external challenge signal, applying the challenge signal to the memristor array to cause some memristor cells to change from a high-resistivity state to a low-resistivity state with a certain probability, obtaining the output logic level of the current comparators, splicing the logic signals to obtain the PUF response sequence, and then controlling the memristor array to return to a high-resistivity state. Firstly, this application achieves a "hidden / activated" operating mode by keeping the entire memristor array in a high-resistivity state as a hidden state and briefly activating some cells under challenge conditions. This effectively reduces static power consumption and significantly improves resistance to side-channel probing and physical analysis. Secondly, this application utilizes the memristor SET voltage threshold as an entropy source, causing selected cells to generate different switching results probabilistically under a fixed write pulse. This results in a highly random response derived from differences in the device's microstructure, improving unpredictability and resistance to modeling attacks. Thirdly, this application introduces a digital readout structure composed of a reference current source and a current comparator, achieving a stable, low-power logic response without complex analog circuitry. Therefore, this application achieves significant improvements over existing technologies in terms of randomness, concealment, side-channel protection, and energy efficiency. Attached Figure Description

[0019] Figure 1 This is a schematic diagram of a hidden PUF device based on a memristor array provided in an embodiment of this application.

[0020] Figure 2 This is a flowchart of the operation method of the hidden PUF device based on memristor array provided in the embodiments of this application. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0022] like Figure 1 As shown, this application provides a hidden PUF device based on a memristor array, including a processing module, a memristor array, a reference current source, and a current comparator; wherein, The memristor array is composed of multiple independently addressable memristor cells. The initial state of each memristor cell is a high-resistance state, and the SET voltage threshold of each memristor cell is different in the high-resistance state. The reference current source is used to provide a stable reference current signal; The number of current comparators is equal to the number of columns in the memristor array. One end of each comparator is connected to the output terminal of the corresponding column of the memristor array, and the other end is connected to the reference current source. It is used to compare the magnitude of the column output current with the reference current signal and output logic level "1" or "0" to the processing module. The processing module is used to receive external challenge signals, apply challenge signals to the memristor array, cause some memristor units to change from a high-resistance state to a low-resistance state with a certain probability, obtain the output logic level of the current comparator, splice the logic signals to obtain the PUF response sequence, and then control the memristor array to return to the high-resistance state.

[0023] In this application, the PUF device can switch between a hidden state and an active state. In the hidden state, the processing module determines which memristor cells in the array are selected and the number of selected cells based on an externally input challenge signal, wherein the number of selected cells corresponds to the number of response bits to be generated. The processing module applies a SET voltage pulse to the selected memristors, causing them to switch from a high-resistance state to a low-resistance state, thus entering the active state. Affected by the voltage amplitude, pulse width, and local defect distribution of the device, approximately half of the selected memristors switch from the high-resistance state to the low-resistance state, forming a random conductive path. In the active state, the processing module again applies a read voltage pulse to the selected memristors corresponding to the challenge signal. The conduction current of the low-resistance memristors increases significantly, while the conduction current of the high-resistance memristors is smaller. The reference current source is set to be greater than the high-resistance current and less than the low-resistance current, enabling the current comparator to stably determine the logic state of each cell, mapping the high-resistance state to logic "0" and the low-resistance state to logic "1", thereby stably reading "1" or "0". The processing module concatenates the output bits of each unit in the array spatial order to generate a complete PUF response sequence. After completing the response reading, the processing module applies a RESET voltage to all memristor units in the array, restoring them all to a high-resistivity state, thus returning to the hidden state. When the device enters the hidden state, all memristor units in the array return to a high-resistivity state. At this time, all conductive paths within the array are closed, and there is no effective current at the output terminal, thereby significantly reducing static power consumption and physically shielding external probe signals, achieving information hiding and security protection. This hiding mechanism can be automatically activated in non-operating mode or protection mode, ensuring the concealment and security of the system in standby mode or under attack, while providing effective protection for low-power hardware security applications. The SET voltage refers to the voltage required to switch the device from a high-resistivity state (HRS) to a low-resistivity state (LRS), also known as the "write" voltage or "on" voltage. The RESET voltage refers to the voltage required to return the device from a low-resistivity state (LRS) to a high-resistivity state (HRS), also known as the "erase" voltage or "off" voltage.

[0024] It should be noted that, compared to voltage comparison / resistance comparison solutions, the memristor array and processing module are designed in tandem, and through current comparison and threshold decision, the response stability is further enhanced, the impact of environmental fluctuations (such as temperature and voltage) and noise on the output is reduced, and the consistency and repeatability of the response are guaranteed.

[0025] The memristor unit serves two purposes: firstly, it operates in a hidden state to achieve low static power consumption and probe resistance; secondly, it can switch to an active state in response to a challenge signal. Preferably, the memristor unit employs a 1T1R structure formed by a gating transistor and a memristor connected in series. The control terminal of the gating transistor is connected to the processing module, used to turn on when selected and turn off when not selected, achieving unit-level addressing and current path control. By blocking the current path of non-target units through the gating transistor, parasitic path currents are suppressed, ensuring that each memristor unit can be addressed independently and preventing unselected units from interfering with the output results. The memristor unit has a hideable characteristic, dynamically switching between a hidden state and an active state. It should be noted that, due to the 1T1R array design suppressing parasitic path currents, the memristor array can be scaled up to large-scale integration, ensuring stable output, low power consumption, and reliability even in high-density systems.

[0026] Preferably, the reference current source is configured to be greater than the high-resistivity current of the memristor and less than the low-resistivity current.

[0027] Preferably, the SET voltage threshold of each memristor unit differs in the high-resistivity state, and the difference is greater than ±10% of the median.

[0028] Preferably, the challenge signal is the median of the distribution of the memristor SET voltage threshold in the memristor array under the active state.

[0029] It should be noted that this application optimizes the operating state control and read / write strategy of the memristor array. By measuring and statistically analyzing the SET voltage threshold distribution of the memristors in the array under high-resistance conditions, and selecting the median voltage as the write voltage based on the distribution results, approximately half of the memristor cells randomly switch from a high-resistance state to a low-resistance state, thereby generating response characteristics with high randomness and unpredictability at the physical level. This method avoids complex random number control circuit design while fully utilizing the inherent physical differences between memristor devices to achieve low-power, high-randomness, and repeatable PUF response generation.

[0030] Preferably, the current comparator will turn on a current greater than the reference current signal. The cells with a current less than the reference current signal are mapped to logic "1", and the cells with a current less than the reference current signal are mapped to logic "0". In one illustrated embodiment, the SA (SenseAmplifier) ​​is used as a current comparator.

[0031] Preferably, the output signal of the current comparator is digitized and then the processing module generates a response bit stream to ensure the stability and repeatability of the output results.

[0032] Preferably, the processing module splices the output bits of each unit in the spatial order of the memristor array to generate a complete PUF response sequence. The PUF response sequence is a binary bit sequence, and its length is adaptively adjusted according to the number of selected memristor units and is not limited by a fixed number of bits.

[0033] Preferably, the processing module restores all memristor cells in the memristor array to a high-resistivity state by removing the operating voltage or applying a RESET voltage to the memristor array.

[0034] Preferably, the processing module is further configured to generate challenge-response pairs during the registration and authentication phases respectively, thereby achieving unique identity authentication of the device.

[0035] Preferably, the concealable PUF device is integrated with an external security processor, encryption module and / or communication interface to build a security chip or trusted hardware system.

[0036] Based on the above, this application provides an operation method for the aforementioned hidden PUF device based on a memristor array, comprising: Excitation Phase: An external challenge signal is received and applied to the memristor array, causing some memristor cells to transition from a high-resistance state to a low-resistance state with a certain probability. Specifically, the processing module selects several cells in the array based on the challenge signal and applies a control voltage signal to the selected cells, causing some memristor cells to transition to a low-resistance state with a certain probability. This random conduction behavior is determined by the physical characteristics of the device and has inherent uncertainty and unpredictability.

[0037] Reading phase: The output logic level of the current comparator is obtained, and the logic signals are concatenated to obtain the PUF response sequence. Specifically, the processing module reads the conduction state of the selected unit one by one, and makes a judgment with the reference current source through the current comparator. The unit with the conduction current greater than the reference value is mapped to logic "1", and the unit with the conduction current less than the reference value is mapped to logic "0", thereby forming a stable bit response sequence.

[0038] Concealment Phase: The memristor array is restored to a high-resistance state. Specifically, the processing module controls the memristor array to return to a high-resistance state, completely clearing the internal conduction state of the array. This physically shields internal information, preventing external detection and reverse engineering, thus achieving a concealable security feature.

[0039] Through the above embodiments, this invention realizes a random response generation and physical-level hiding mechanism based on the electrical characteristics of memristors. The device has extremely low power consumption in static standby mode and can achieve anti-cloning and anti-physical attack functions without additional encryption modules, offering advantages such as low power consumption, high security, and good scalability.

[0040] In this application, the terms "first" and "second," etc., are used to distinguish different objects, not to describe a specific order of objects. For example, "first response message" and "second response message," etc., are used to distinguish different response messages, not to describe a specific order of response messages.

[0041] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0042] In the description of the embodiments of this application, unless otherwise stated, "multiple" means two or more, for example, multiple processing units means two or more processing units, multiple elements means two or more elements, etc.

[0043] It should be understood that expressions such as “comprising” and “may include” used in this application indicate the existence of the disclosed functions, operations, or constituent elements, and do not limit one or more additional functions, operations, and constituent elements. In this application, terms such as “comprising” and / or “having” are to be interpreted as indicating a particular characteristic, number, operation, constituent element, component, or combination thereof, but not to exclude the existence or possibility of adding one or more other characteristics, numbers, operations, constituent elements, components, or combinations thereof.

[0044] Furthermore, in this application, the expression "and / or" includes any and all combinations of the associated listed words. For example, the expression "A and / or B" may include A, may include B, or may include both A and B.

[0045] In the description of the embodiments of this application, it should be noted that, unless otherwise explicitly specified and limited, the term "connection" should be interpreted broadly. For example, "connection" can be a detachable connection or a non-detachable connection; it can be a direct connection or an indirect connection through an intermediate medium. "Fixed connection" refers to a connection where the relative positional relationship remains unchanged after connection. "Rotary connection" refers to a connection where the two parts can rotate relative to each other after connection. "Sliding connection" refers to a connection where the two parts can slide relative to each other after connection.

[0046] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A hidden PUF device based on a memristor array, characterized in that, The hideable PUF device can switch between a hidden state and an active state. The hideable PUF device includes a processing module, a memristor array, a reference current source, and a current comparator; wherein... The memristor array is composed of multiple independently addressable memristor cells. The initial state of each memristor cell is a high-resistance state, and the SET voltage threshold of each memristor cell is different in the high-resistance state. The reference current source is used to provide a stable reference current signal; The number of current comparators is equal to the number of columns in the memristor array. One end of each comparator is connected to the output terminal of the corresponding column of the memristor array, and the other end is connected to the reference current source. It is used to compare the magnitude of the column output current with the reference current signal and output a logic level "1" or "0" to the processing module. The processing module, in the hidden state, determines which memristor units in the memristor array are selected and the number of selected units based on the externally input challenge signal, wherein the number of selected units corresponds to the number of response bits to be generated; applies a SET voltage pulse to the selected memristor units to switch them from a high-resistance state to a low-resistance state, forming a random conductive path, thereby entering the active state, the random conduction behavior being determined by the physical characteristics of the device; acquires the output logic level of the current comparator, splices the output bits of each unit in the array spatial order to generate a complete PUF response sequence, and after obtaining the PUF response sequence, controls the memristor array to return to the high-resistance state.

2. The concealable PUF device as described in claim 1, characterized in that, The memristor unit adopts a 1T1R structure formed by a gating transistor and a memristor connected in series. The control terminal of the gating transistor is connected to the processing module to conduct when selected and turn off when not selected, thereby realizing unit-level addressing and current path control.

3. The concealable PUF device as described in claim 1, characterized in that, The reference current source is set to be greater than the high-resistivity current of the memristor and less than the low-resistivity current.

4. The concealable PUF device as described in claim 1, characterized in that, The challenge signal is the median of the SET voltage threshold distribution of the memristors in the memristor array under high impedance conditions.

5. The concealable PUF device as described in claim 1, characterized in that, The current comparator maps cells with on-current greater than the reference current signal to logic "1" and cells with on-current less than the reference current signal to logic "0".

6. The concealable PUF device as described in claim 1, characterized in that, The length of the PUF response sequence is adaptively adjusted according to the number of selected memristor cells and is not limited by a fixed number of bits.

7. The concealable PUF device as described in claim 1, characterized in that, The processing module restores all memristor cells in the memristor array to a high-resistivity state by applying a RESET voltage to the memristor array.

8. The concealable PUF device as described in any one of claims 1 to 7, characterized in that, The processing module is also used to generate challenge-response pairs during the registration and authentication phases to achieve unique identity authentication of the device.

9. The concealable PUF device as described in any one of claims 1 to 7, characterized in that, The concealable PUF device is integrated with an external security processor, encryption module and / or communication interface to build a secure chip or trusted hardware system.

10. A method of operating a hidden PUF device based on a memristor array as described in any one of claims 1 to 9, characterized in that, include: Excitation phase: Receive external challenge signals and apply challenge signals to the memristor array, causing some memristor cells to change from a high-resistivity state to a low-resistivity state with a certain probability; Reading phase: Obtain the output logic level of the current comparator, concatenate the logic signals to obtain the PUF response sequence; Hidden phase: Control the memristor array to return to a high-resistivity state.

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