An adaptive sampling rate pipelined analog-to-digital converter and a control method thereof

Abstract

The application relates to the technical field of code conversion, and discloses a pipeline analog-to-digital converter with an adaptive sampling rate and a control method thereof, which comprises the following steps: a first analog-to-digital converter quantizes an input signal in response to a first working clock to generate a first digital code; a residual generation module is connected with an output end of the first analog-to-digital converter and simultaneously accesses the input signal, and is used for generating a residual signal; a second analog-to-digital converter is used for quantizing the residual signal in a second working clock to generate a second digital code; and a dynamic trigger logic module is used for receiving the second digital code and generating the first working clock; wherein the dynamic trigger logic module is configured to monitor the second digital code, generate a pulse of the first working clock when a preset trigger condition is met, and trigger the first analog-to-digital converter to perform a quantization operation once. The application improves the stability and energy efficiency ratio of the analog-to-digital converter, widens the application scene of the analog-to-digital converter, and is especially suitable for a scene which is sensitive to power consumption and needs to cope with complex signals.

Description

Technical Field

[0001] This application relates to the field of code conversion technology, and in particular to an adaptive sampling rate pipelined analog-to-digital converter and its control method. Background Technology

[0002] Analog-to-digital converters (ADCs) serve as a bridge between the physical and digital worlds, finding wide application in fields such as communications, healthcare, and consumer electronics. Among them, pipelined ADCs have become the mainstream high-performance ADC architecture due to their excellent balance between high speed and high accuracy. In recent years, continuous-time pipelined ADCs (CT-Pipelined ADCs) have garnered significant attention for simplifying front-end circuit design and integrating anti-aliasing filters. This architecture combines the advantages of continuous-time signal processing with pipelined architecture, optimizing system integration while maintaining high performance, and has become an important development direction in the field of high-performance ADCs.

[0003] However, traditional CT-Pipelined ADCs face inherent contradictions in practical applications. Their first-stage ADC (coarse quantization stage) typically uses a fixed clock frequency for sampling. While this design simplifies circuit implementation, it cannot adapt to input signals with varying characteristics. On the one hand, when the input signal changes slowly, high-frequency fixed sampling results in unnecessary power consumption waste and easily introduces additional noise and circuit disturbances during sampling, affecting conversion stability. On the other hand, if a lower fixed sampling frequency is used to reduce power consumption, when the slope of the input signal suddenly increases, the signal change between two sampling points will exceed the preset range. This causes the residual signal transmitted to the subsequent stage to exceed its linear processing range (i.e., over-range), or causes the residual amplifier to operate in a nonlinear region with extremely poor linearity. Ultimately, this leads to a severe decrease in the conversion accuracy of the entire ADC or even conversion errors.

[0004] Therefore, existing technologies struggle to achieve an ideal balance between power consumption control and large dynamic range signal processing capabilities. This limitation restricts the widespread application of CT-Pipelined ADCs in power-sensitive scenarios that require handling complex signals. Summary of the Invention

[0005] To address the aforementioned technical problems, this application provides an adaptive sampling rate pipelined analog-to-digital converter and its control method.

[0006] Firstly, this application provides an adaptive sampling rate pipelined analog-to-digital converter, which adopts the following technical solution:

[0007] An adaptive sampling rate pipelined analog-to-digital converter, comprising:

[0008] A first analog-to-digital converter (ADC) quantizes the input signal in response to a first operating clock to generate a first digital code. A residual generation module is connected to the output of the first ADC and simultaneously receives the input signal to generate a residual signal based on the first digital code and the input signal. A second ADC is connected to the output of the residual generation module and quantizes the residual signal using a second operating clock to generate a second digital code. A dynamic triggering logic module has its input connected to the output of the second ADC and its output connected to the input of the first ADC. It receives the second digital code and generates the first operating clock. The dynamic triggering logic module is configured to monitor the second digital code and generate a pulse of the first operating clock when the second digital code meets a preset triggering condition, thereby triggering the first ADC to perform a quantization operation.

[0009] By adopting the above technical solution, the first working clock is adaptively generated through the linkage between the dynamic triggering logic module and the second digital code. This allows the quantization frequency of the first analog-to-digital converter to be dynamically adjusted according to the characteristics of the input signal. This avoids amplifier distortion and over-range problems when the input signal has a large rate of change, and saves power consumption when the signal is flat. It significantly improves the stability, accuracy, and energy efficiency ratio of the analog-to-digital converter, and expands its application scenarios. It is especially suitable for power-sensitive scenarios that need to deal with complex signals (such as IoT terminals, portable medical devices, mobile smart terminals, etc.).

[0010] Optionally, the preset trigger condition is that the most significant bit and the second most significant bit of the second digital code are both 0 or both are 1.

[0011] By adopting the above technical solution, the highest two bits of the second digital code are used directly as the trigger judgment basis, eliminating the need for complex signal calculations or additional detection circuits. This simplifies the logic design of the dynamic trigger logic module and enables rapid identification of the residual signal amplitude. When both highest two bits are 0 or both are 1, it indicates that the residual signal has approached the range boundary of the second analog-to-digital converter after processing. At this time, triggering the quantization of the first analog-to-digital converter can promptly pull the residual signal back to a reasonable range, ensuring the linear operation of the residual amplifier. At the same time, the judgment logic responds quickly without additional delay, ensuring the real-time performance of adaptive adjustment.

[0012] Optionally, the residual generation module includes: a digital-to-analog converter connected to the output of the first analog-to-digital converter, used to convert the first digital code into an analog reconstructed signal; and a subtractor, whose input receives the input signal and the analog reconstructed signal, used to subtract the analog reconstructed signal from the input signal to obtain the residual signal.

[0013] By adopting the above technical solution, the digital-to-analog converter realizes the analog reconstruction of the first digital code. The subtractor obtains the residual signal by calculating the difference between the input signal and the reconstructed signal. This structure is logically clear and easy to implement. It can accurately reflect the deviation between the input signal and the quantization result of the first analog-to-digital converter, providing a reliable signal basis for the fine quantization of the second analog-to-digital converter. At the same time, it ensures that the amplitude change of the residual signal is consistent with the characteristics of the input signal, thus providing a guarantee for the effective execution of the dynamic triggering logic.

[0014] Optionally, a residual amplifier is also included, positioned between the residual generation module and the second analog-to-digital converter, to amplify the residual signal.

[0015] By adopting the above technical solution, the residual amplifier amplifies small-amplitude residual signals, increasing the amplitude range of the residual signals. This allows the second analog-to-digital converter to more easily capture signal details and improve the overall quantization resolution. At the same time, the amplitude changes of the amplified residual signals are more easily recognized by the dynamic triggering logic module, further optimizing the response sensitivity of the triggering conditions. This ensures that the first analog-to-digital converter can be triggered to adjust in a timely manner when the residual signal approaches the range boundary, avoiding nonlinear distortion caused by excessive output swing of the amplifier.

[0016] Optionally, a delay module is also included, with its signal input terminal connected to the input terminal of the first analog-to-digital converter and its output terminal connected to the input terminal of the subtractor, for matching the delay between the input terminal of the first analog-to-digital converter and the output terminal of the digital-to-analog converter.

[0017] By adopting the above technical solution, the delay module can compensate for the signal delay generated during the quantization process of the first analog-to-digital converter and the reconstruction process of the digital-to-analog converter, so that the input signal and the analog reconstructed signal are phase aligned at the input of the subtractor, reducing the calculation error of the residual signal caused by the delay, and ensuring that the residual signal can truly reflect the deviation between the input signal and the quantization result; at the same time, the phase-aligned signal can reduce the probability of misjudging the amplitude of the residual signal by the dynamic triggering logic module, further improving the accuracy and stability of adaptive sampling.

[0018] Optionally, the dynamic triggering logic module includes logic gate circuits and at least two cascaded flip-flop circuits. The input of the logic gate circuit is connected to the output of the second analog-to-digital converter, and the input of the flip-flop circuit is connected to the output of the logic gate. The output outputs a first working clock. The dynamic triggering logic module transmits signals through the logic gate circuit and the flip-flop circuit, so that the effective edge of the output first working clock lags behind the preset trigger edge of the second working clock.

[0019] By adopting the above technical solution, the timing coordination between the first and second working clocks is achieved by utilizing the delay characteristics of the flip-flop. This ensures that the quantization start time of the first analog-to-digital converter (ADC) is later than the sampling time of the second ADC, avoiding timing conflicts between the two clock signals. At the same time, the reasonable edge hysteresis design ensures that the first ADC is triggered only after the second digital code is fully output, preventing triggering misjudgments caused by the instability of the second digital code. This ensures the reliability of the dynamic triggering logic and further improves the overall working stability of the ADC.

[0020] Secondly, the control method for a pipelined analog-to-digital converter provided in this application adopts the following technical solution:

[0021] A control method for a pipelined analog-to-digital converter, applied to a pipelined analog-to-digital converter including a first analog-to-digital converter and a second analog-to-digital converter, includes the following steps:

[0022] S1. The residual signal is quantized by the second analog-to-digital converter using a preset second working clock to generate a second digital code;

[0023] S2. Monitor the code value of the second digital code, and generate a trigger signal when the code value meets the preset trigger conditions;

[0024] S3. In response to the trigger signal, the first analog-to-digital converter is triggered to perform a quantization operation on the input signal at the first operating clock to update the residual signal.

[0025] By adopting the above technical solution, the control method of this application is based on the continuous quantization of the second analog-to-digital converter. By monitoring the triggering state of the second digital code in real time, the first analog-to-digital converter is adaptively triggered, realizing the dynamic adjustment of the sampling rate. There is no need to pre-set a fixed first working clock frequency. Instead, the quantization timing is flexibly adjusted according to the state of the residual signal derived from the input signal. This solves the problem of insufficient accuracy when the input signal has a large rate of change at a fixed frequency, and avoids the waste of power consumption when the signal is flat. This enables the analog-to-digital converter to achieve the optimal balance between power consumption and accuracy under different input scenarios. The operation logic is simple and easy to implement in hardware.

[0026] Optionally, the preset trigger condition is that the most significant bit and the second most significant bit of the second digital code are both 0 or both are 1.

[0027] By adopting the above technical solution, using the highest two bits of the second digital code as the trigger judgment standard simplifies the detection logic of the trigger condition, eliminates the need for complex signal processing algorithms, and reduces the execution complexity of the control method. At the same time, this trigger condition can directly reflect the amplitude boundary state of the residual signal, ensuring timely triggering of updates when the residual signal approaches the range of the second analog-to-digital converter, effectively reducing the probability of residual amplifier distortion and input over-range, and ensuring the stability of quantization accuracy.

[0028] Optionally, the steps for updating the residual signal include:

[0029] S31. Convert the quantization result of the first analog-to-digital converter into an analog reconstructed signal through a digital-to-analog converter;

[0030] S32. Subtract the analog reconstructed signal from the input signal to obtain the updated residual signal;

[0031] S33. Amplify the updated residual signal and input it into the second analog-to-digital converter for quantization.

[0032] By adopting the above technical solution, the update process of the residual signal is clarified. The analog reconstruction of the quantization result is realized through the digital-to-analog converter. The new residual signal is obtained by subtraction operation and then amplified to adapt to the quantization requirements of the second analog-to-digital converter, ensuring that the updated residual signal can accurately reflect the latest state of the input signal. At the same time, the amplification step further improves the identifiability of the residual signal, provides a reliable basis for the judgment of subsequent trigger conditions, and ensures the closed-loop stability of the adaptive control process.

[0033] Optionally, the frequency of the second operating clock is configured according to the frequency of the input signal, and the two satisfy the following relationship: ; Where α is the ratio of the input signal frequency to the second clock frequency, N1 is the quantization bit depth of ADC1, FS is the range of ADC2, and A in The amplitude of the input signal.

[0034] By adopting the above technical solution, the adaptation relationship between the second working clock frequency and the input signal characteristics and the parameters of each ADC can be accurately matched, ensuring that the residual signal is always within the effective processing range of ADC2, avoiding over-range problems and optimizing the overall conversion accuracy.

[0035] In summary, this application includes at least one of the following beneficial technical effects:

[0036] 1. By linking the dynamic trigger logic module with the second digital code, the adaptive generation of the first working clock is realized, so that the quantization frequency of the first analog-to-digital converter is dynamically adjusted according to the characteristics of the input signal. This avoids amplifier distortion and over-range problems when the input signal has a large rate of change, and saves power consumption when the signal is flat, significantly improving the stability, accuracy and energy efficiency of the analog-to-digital converter.

[0037] 2. By using the highest two bits of the second digital code as the trigger condition, combined with the timing design of the flip-flop, the complexity of the circuit and control logic is simplified, the difficulty of hardware implementation is reduced, and the speed and accuracy of trigger judgment are guaranteed, providing reliable logical support for adaptive sampling.

[0038] 3. The control method achieves dynamic optimization of the sampling rate through a closed-loop process of "continuous quantization - real-time monitoring - adaptive triggering - signal update", enabling the analog-to-digital converter to adapt to input signals with different rates of change, thus broadening the application scenarios and balancing power consumption and accuracy. Attached Figure Description

[0039] Figure 1 This is a circuit structure diagram of a pipelined analog-to-digital converter provided in related technologies;

[0040] Figure 2 This is a circuit structure diagram of an adaptive sampling rate pipelined analog-to-digital converter provided in an embodiment of this application;

[0041] Figure 3 This is a circuit structure diagram of the dynamic triggering logic module provided in the embodiments of this application;

[0042] Figure 4 This is a timing waveform diagram of the dynamic triggering logic module provided in the embodiments of this application;

[0043] Figure 5 This is a schematic diagram of the signal waveforms of each node of the pipelined analog-to-digital converter with adaptive sampling rate provided in the embodiments of this application;

[0044] Figure 6 This application provides a control method for an adaptive sampling rate pipelined analog-to-digital converter.

[0045] Explanation of reference numerals in the attached figures:

[0046] 1. First analog-to-digital converter; 2. Residual generation module; 21. Digital-to-analog converter; 22. Subtractor; 3. Second analog-to-digital converter; 4. Dynamic trigger logic module; 41. XNOR gate circuit; 42. First flip-flop; 43. Second flip-flop; 5. Residual amplifier; 6. Delay module. Detailed Implementation

[0047] The following is in conjunction with the appendix Figure 1-6This application will be described in further detail.

[0048] Reference Figure 1 This paper illustrates the circuit structure of a continuous-time pipelined analog-to-digital converter (CT-PipelinedADC) in the related art. In this structure, the first-stage analog-to-digital converter (ADC1) operates with a fixed-frequency clock. During the interval between two operations of ADC1, the residual signal Vres increases as the input signal Vin increases. If the operating frequency of ADC1 is low, changes in the input signal can easily cause the amplifier input to exceed the reasonable operating range, thereby causing problems such as nonlinear distortion of the amplifier output and over-range input of the second-stage analog-to-digital converter (ADC2). Therefore, the operating frequency of ADC1 in this structure cannot be too low, and the input signal frequency cannot be too high, which limits its application scenarios.

[0049] To address the aforementioned issues, this application discloses an adaptive sampling rate pipelined analog-to-digital converter.

[0050] Reference Figure 2 The adaptive sampling rate pipelined analog-to-digital converter provided in this application includes a first analog-to-digital converter 1 (hereinafter referred to as ADC1), a residual generation module 2, a second analog-to-digital converter 3 (hereinafter referred to as ADC2), and a dynamic triggering logic module 4;

[0051] A first analog-to-digital converter 1 (ADC1) quantizes the input signal (Vin) in response to a first operating clock (CK1) to generate a first digital code (DOUT1). A residual generation module 2 is connected to the output of the first ADC1 and simultaneously receives the input signal (Vin), generating a residual signal (Vres) based on the first digital code (DOUT1) and the input signal (Vin). A second analog-to-digital converter 3 (ADC2) is connected to the output of the residual generation module 2 and quantizes the residual signal (Vres) with a second operating clock (CK2) to generate a second digital code (DOUT1). The second digital code (DOUT2) and the dynamic triggering logic module are connected to the output of the second analog-to-digital converter 3 (ADC2) and the input of the first analog-to-digital converter 1 (ADC1). The module is used to receive the second digital code (DOUT2) and generate the first working clock (CK1). The dynamic triggering logic module is configured to monitor the second digital code (DOUT2) in real time and generate a pulse of the first working clock (CK1) when the second digital code (DOUT2) meets the preset triggering conditions, so as to trigger the first analog-to-digital converter 1 (ADC1) to perform a quantization operation.

[0052] This application embodiment provides an adaptive sampling rate pipelined analog-to-digital converter (ADC) that no longer provides a fixed operating clock for ADC1. Instead, the back-end circuit module determines the operation of ADC1 based on the real-time status of signal processing. The implementation principle is as follows: The input signal (Vin) is a continuously changing analog voltage signal, and its voltage change slope directly reflects the speed of signal change. This signal is first input to the first analog-to-digital converter 1 (ADC1). Triggered by the first operating clock (CK1), ADC1 performs coarse quantization on Vin and outputs the first digital code (DOUT1) (that is, converting the continuous analog voltage into a discrete digital code, for example, quantizing 2.7V into the digital code "1011"). The residual generation module 2 generates a residual signal (Vres) based on DOUT1. The magnitude of Vres is positively correlated with the slope of Vin's change: when Vin changes quickly (large slope), Vres accumulates rapidly; when Vin changes slowly (small slope), Vres increases relatively slowly (the residual signal is the difference between the current input signal and the reconstructed signal from the previous quantization; the faster the input signal changes, the faster this difference accumulates, and the larger the residual signal).

[0053] The residual signal (Vres) is then input to the second analog-to-digital converter 3 (ADC2). ADC2 is driven by a preset fixed-frequency second operating clock (CK2) to continuously fine-quantize the residual signal and output a second digital code (DOUT2). The dynamic triggering logic module receives and monitors DOUT2 in real time. Since DOUT2 corresponds to the quantization result of Vres, when the code value of DOUT2 approaches the range boundary of ADC2, it means that Vres is approaching the over-range threshold or may cause nonlinear distortion. At this time, the dynamic triggering logic module generates a pulse of the first operating clock (CK1) to trigger ADC1 to re-quantize the current Vin. This new quantization updates DOUT1 and synchronously adjusts the subsequently generated Vres (residual signal), so that Vres quickly returns to the safe operating range. In this way, the quantization frequency of ADC1 is matched with the characteristics of the input signal Vin, thereby greatly optimizing power consumption while ensuring accuracy.

[0054] It is understood that the dynamic triggering logic module of this application can adaptively generate the first working clock (CK1) based on the real-time state of the second digital code (DOUT2), so that the quantization frequency of the first analog-to-digital converter 1 (ADC1) is accurately matched with the characteristics of the input signal (Vin). When the rate of change of the input signal (Vin) is small, the second digital code (DOUT2) is not easy to meet the triggering condition, which can reduce the working frequency of the first analog-to-digital converter 1 (ADC1), effectively saving power consumption and reducing unnecessary circuit disturbances. When the rate of change of the input signal (Vin) is large, the second digital code (DOUT2) quickly meets the triggering condition, and the first analog-to-digital converter 1 (ADC1) is triggered at high frequency for quantization, and the amplitude of the residual signal (Vres) is adjusted in time to prevent the output nonlinear distortion of the residual amplifier 5 and the input over-range of the second analog-to-digital converter 3 (ADC2), thereby improving the working stability and quantization accuracy of the analog-to-digital converter and broadening its application scenarios, especially suitable for power-sensitive scenarios that need to deal with complex signals (such as IoT terminals, portable medical devices, mobile smart terminals, etc.).

[0055] like Figure 2 As shown, in a preferred embodiment, the adaptive sampling rate pipelined analog-to-digital converter further includes a residual amplifier 5 (G) and a delay module 6 (delay). The residual amplifier 5 (G) is disposed between the residual generation module 2 and the second analog-to-digital converter 3 (ADC2) to amplify the residual signal (Vres). The residual amplifier 5 amplifies the small-amplitude residual signal, increasing the amplitude range of the residual signal, making it easier for the second analog-to-digital converter 3 to capture signal details and improve the overall quantization resolution. At the same time, the amplitude change of the amplified residual signal is more easily identified by the dynamic trigger logic module 4, further optimizing the response sensitivity of the trigger condition, ensuring that the first analog-to-digital converter 1 can be triggered to adjust in time when the residual signal approaches the range boundary, and improving the nonlinear distortion caused by the amplifier's excessive output swing.

[0056] The residual generation module 2 includes a digital-to-analog converter 21 (hereinafter referred to as DAC1) and a subtractor 22. The digital-to-analog converter 21 (DAC1) is connected to the output of the first analog-to-digital converter 1 (ADC1) and is used to convert the first digital code (DOUT1) into an analog reconstructed signal (VDA1). The input of the subtractor 22 receives the input signal (Vin) and the analog reconstructed signal (VDA1) and is used to subtract the analog reconstructed signal from the input signal (Vin) to obtain the residual signal (Vres). This structure is logically clear and easy to implement. It can accurately reflect the deviation between the input signal and the quantization result of the first analog-to-digital converter 1, providing a reliable signal basis for the fine quantization of the second analog-to-digital converter 3. At the same time, it ensures that the amplitude change of the residual signal is consistent with the characteristics of the input signal, thus providing a guarantee for the effective execution of the dynamic triggering logic.

[0057] The signal input terminal of the delay module 6 is connected to the input terminal of the first analog-to-digital converter 1 (ADC1), and the signal output terminal is connected to the input terminal of the subtractor 22. It is used to match the delay between the input terminal of the first analog-to-digital converter 1 (ADC1) and the output terminal of the digital-to-analog converter 21 (DAC1). The delay module 6 can compensate for the signal delay generated during the quantization process of the first analog-to-digital converter 1 and the reconstruction process of the digital-to-analog converter 21, so that the input signal and the analog reconstructed signal are phase aligned at the input terminal of the subtractor 22, reducing the calculation error of the residual signal caused by the delay, and ensuring that the residual signal can truly reflect the deviation between the input signal and the quantization result. At the same time, the phase-aligned signal can reduce the probability of misjudging the amplitude of the residual signal by the dynamic triggering logic module 4, further improving the accuracy and stability of adaptive sampling.

[0058] The preset triggering condition configured in the dynamic triggering logic module 4 is that the most significant bit and the second most significant bit of the second digital code (DOUT2) are both 0 or both are 1.

[0059] Specifically, in one embodiment, the input signal Vin is coarsely quantized by ADC1 to obtain DOUT1, and Vin is also sent to the delay module 6. DOUT1 is reconstructed into an analog signal VDA1 by DAC1. The function of the delay module 6 is to match the signal processing delay from the input of ADC1 to the output of DAC1 VDA1, ensuring that its output signal is phase-aligned with VDA1 at the input of subtractor 22.

[0060] Subtractor 22 subtracts VDA1 from the delayed Vin to obtain the residual signal (Vres). Vres is sent to residual amplifier 5 and amplified by gain G to obtain G*Vres. The amplified signal G*Vres is sent to ADC2 for requantization to generate the second digital code (DOUT2). After DOUT1 and DOUT2 are processed by digital alignment and concatenation logic (not shown in the figure), the final quantized codeword is obtained.

[0061] In one embodiment, the second analog-to-digital converter 3 (ADC2) adopts a 10-bit resolution and continuously quantizes the amplified residual signal (G*Vres) under the drive of a preset fixed-frequency second working clock (CK2). For example, it outputs a 10-bit second digital code (DOUT2), whose codeword vector can be represented from the most significant bit to the least significant bit as DOUT2

[10] , DOUT2[9], DOUT2[8], ..., DOUT2[1]).

[0062] The dynamic triggering logic module 4 executes the triggering logic by detecting the two highest bits of DOUT2, namely DOUT2[MSB] (DOUT2

[10] ) and DOUT2[MSB-1] (DOUT2[9]). The preset triggering condition is: when the two highest bits are all 1 (11) or all 0 (00), it indicates that G*Vres has approached the upper or lower limit of the range. At this time, the dynamic triggering logic module 4 triggers ADC1 and DAC1 to perform new quantization and reconstruction. By changing VDA1, Vres is adjusted to be reduced or increased, thereby limiting the output swing of the residual amplifier 5 to the preset ideal range.

[0063] Understandably, using the highest two bits of the second digital code as the trigger judgment basis directly eliminates the need for complex signal calculations or additional detection circuits, simplifying the logic design of the dynamic trigger logic module 4 and enabling rapid identification of the residual signal amplitude. When both highest two bits are 0 or both are 1, it indicates that the residual signal has approached the range boundary of the second analog-to-digital converter 3 after processing. At this time, triggering the quantization of the first analog-to-digital converter 1 can promptly pull the residual signal back to a reasonable range, ensuring the linear operation of the residual amplifier 5. At the same time, this judgment logic responds quickly without additional delay, ensuring the real-time performance of adaptive adjustment.

[0064] It should be noted that during the system power-on initialization phase, a first operating clock pulse can be forcibly generated by an external reset circuit to initiate the first quantization of the first analog-to-digital converter, preventing the system from being in a deadlock state. Additionally, in a preferred embodiment of this application, at the instant the ADC1 performs quantization, the front-end anti-aliasing filter (AAF, not shown in the figure) can be temporarily turned off or bypassed to prevent it from causing filtering delay to the rapidly established input signal, further improving quantization accuracy.

[0065] In one embodiment, the dynamic triggering logic module 4 includes a logic gate circuit and at least two cascaded flip-flop circuits. The input of the logic gate circuit is connected to the output of the second analog-to-digital converter 3, and the input of the flip-flop circuit is connected to the output of the logic gate circuit. The output of the flip-flop circuit outputs a first working clock. Through the signal transmission of the logic gate circuit and the flip-flop circuit, the dynamic triggering logic module 4 makes the effective edge of the output first working clock lag behind the preset trigger edge of the second working clock.

[0066] Reference Figure 3In one embodiment, a specific circuit implementation structure of the dynamic triggering logic module 4 is shown. This circuit consists of an XNOR gate 41 and two D-type flip-flops (DFF1, DFF2). Signal CD1 is an indication signal indicating the completion of ADC1 quantization (active high); signal CD2 is an indication signal indicating the completion of ADC2 quantization (active high). The most significant two bits of DOUT2 are fed into the XNOR gate. When the triggering condition (all 1s or all 0s) is met, the XNOR gate outputs a high level.

[0067] Reference Figure 4 The timing waveform diagram shows that when the XNOR signal goes high, this high level is latched by the first flip-flop 42 (DFF1) on the rising edge of CD2, generating the trigger signal TRI. The high level of TRI is aligned with the rising edge of CD2. Subsequently, the TRI signal is latched by the second flip-flop 43 (DFF2) on the falling edge of CK2 (i.e., the preset trigger edge of the second operating clock), generating the operating clock signal CK1 of ADC1. The high level of CK1 is aligned with the falling edge of CK2. When ADC1 completes quantization and sends the rising edge of the CD1 signal, this signal will act as a reset signal, causing TRI and CK1 to return to low levels. This logic ensures that CK1 is set high and reset once within one CK2 cycle after each high XNOR signal. Since CK1 is triggered by the falling edge of CK2 and has undergone the propagation delay of DFF2, it is ensured that the rising edge of CK1 is always later than the falling edge of CK2 (i.e., the effective edge of the first working clock lags behind the preset trigger edge of the second working clock). This means that the start time of ADC1 and DAC1 is later than the sampling time of ADC2, avoiding timing conflicts. This lag time is the delay time of flip-flop DFF2.

[0068] Understandably, the delay characteristics of the flip-flop are used to coordinate the timing of the first and second operating clocks, ensuring that the quantization start time of the first analog-to-digital converter 1 is later than the sampling time of the second analog-to-digital converter 3, thus avoiding timing conflicts between the two clock signals. At the same time, the reasonable edge hysteresis design ensures that the first analog-to-digital converter 1 is triggered only after the second digital code is fully output, preventing triggering misjudgments caused by the instability of the second digital code, ensuring the reliability of the dynamic triggering logic, and further improving the working stability of the entire analog-to-digital converter.

[0069] It should be noted that the logic gate circuit used to detect the trigger condition of the second digital code is not limited to the form of the XOR gate circuit 41. In other feasible embodiments, an equivalent logic circuit formed by combining basic logic gates such as AND gate, OR gate, and XOR gate can also be used, as long as it can detect the preset trigger condition of the second digital code and output a level signal that matches the trigger condition.

[0070] Furthermore, the cascaded structure of the flip-flops in this application is not limited to the two-stage cascaded form in the embodiment; depending on the different requirements for clock edge lag time in actual application scenarios, it can also be extended to a cascaded structure of three, four or even more stages of flip-flops. By increasing the number of cascaded stages of the flip-flops, the transmission delay of the clock signal can be flexibly adjusted to adapt to different timing requirements.

[0071] To further clarify the parameter design basis and quantization constraint logic of this application, and to ensure that the continuous-time pipelined analog-to-digital converter (CT-pipelined ADC) has both high quantization accuracy and low power consumption, the system operating conditions are described in detail below with reference to the main formulas and specific embodiments:

[0072] In one embodiment, to address the problem in traditional CT-pipelined ADCs where the clock frequency of CK2 does not match the input signal variation, leading to the residual amplifier 5 output exceeding its range and ADC2 quantization abnormalities, this application implements a bidirectional constraint design for the frequency of the second operating clock (CK2). CK2 serves as the preset fixed operating clock for ADC2, with its upper frequency limit defined by the ADC2's own performance parameters, and its lower frequency limit simultaneously satisfying the requirements of "residual amplifier 5 output not exceeding its range" and "ADC2 quantization normally," thereby achieving precise matching between the clock frequency and the input signal.

[0073] In one embodiment, to clarify the design basis for the upper frequency limit of CK2 and ensure that the clock frequency matches the hardware performance of ADC2, this application determines its maximum operating frequency based on the resolution of ADC2. For example, when the resolution of ADC2 is 10-bit, the corresponding upper frequency limit of CK2 is approximately 300MHz. The design principle is as follows: the clock frequency of the ADC must match its conversion rate. A single quantization of a 10-bit resolution ADC typically requires approximately 10 clock cycles, while the typical maximum conversion rate of a high-speed 10-bit ADC is 30MSPS (megasamples / second). Therefore, the upper limit of the clock frequency = conversion rate × number of single conversion cycles = 30 × 10 6 Samples / second × 10 cycles / sample = 300 × 10 6 Period / second = 300MHz.

[0074] Understandably, this frequency limit design ensures the maximum quantization rate of ADC2 while avoiding power consumption waste and stability issues caused by excessively high clock frequencies, thus achieving a balance between performance and power consumption.

[0075] In one embodiment, to ensure that the output of the residual amplifier 5 does not exceed its range and to prevent nonlinear distortion, while ensuring the compatibility of the input signal change rate with the clock frequency of CK2 (improving the synchronization imbalance caused by the signal changing too quickly and CK2 not keeping up), this application provides an output constraint formula for the residual amplifier 5: ,in, f in f is the frequency of the input signal. ck2 CK2 clock frequency, α is the ratio of input signal frequency to clock frequency, N1 is the quantization bit depth of ADC1, FS is the range of ADC2, A in This refers to the input signal swing. In this embodiment, the output range of the residual amplifier is set to not exceed half of the ADC2 range to reserve buffer space for signal fluctuations. For example, when N1=10, FS=5V, and Ain=1.5V, substituting into the formula, we can obtain: the right side of the formula ≈ 0.000512, that is, α<0.000512. If the input signal frequency f in actual applications... in =153kHz, then the minimum clock frequency required for CK2 is 300MHz.

[0076] Understandably, by quantizing the upper limit of α, the matching relationship between the input signal frequency and the CK2 frequency is established, reflecting the matching degree between the "input signal change rate" and the "CK2 sampling rate". The formula limits α to no more than the critical value, which means that the CK2 frequency can always meet the requirement that the change of the input signal will not exceed the system processing capacity within a sampling period. This formula limits the ratio of the input signal frequency to the CK2 frequency. On the one hand, the minimum frequency of CK2 can be calculated. Even if the change rate of the input sinusoidal signal reaches its maximum, it can ensure that the residual signal Vres will not accumulate excessively. After being amplified by the residual amplifier, it is still within the safe range of ADC2. This not only improves the problem of signal and clock asynchrony, but also reduces the probability of amplifier nonlinear distortion, achieving the dual effect of frequency matching and distortion control.

[0077] In one embodiment, to further ensure stable quantization of ADC2 and improve quantization error, while clarifying the system's guaranteed operating conditions, this application provides a normal operating constraint formula for ADC2: This formula and the residual amplifier 5 output constraint formula must be satisfied simultaneously. The former is a strict constraint of "no distortion," and the latter is a minimum constraint of "quantization stability." Together, they constitute a dual constraint on the CK2 frequency. Compared with the residual amplifier 5 output constraint formula, this formula reduces the denominator term from 2... N1-1 Adjust to 2 N1 The upper limit of α obtained is more lenient (for example, when N1=10, 0.000977, compared to (0.000488 is larger), but due to the principle of "simultaneous satisfaction", the actual lower limit of the CK2 frequency is still determined by the more stringent residual amplifier 5 output constraint formula.

[0078] Understandably, the purpose of this formula is to provide "safety redundancy" for the quantization stability of the system. On the one hand, its lenient upper limit of α ensures that even in scenarios where the rate of change of the input signal is slightly lower than the "maximum distortion threshold", the ADC2 can still quantize stably, preventing quantization errors caused by slight mismatch between the signal and the clock.

[0079] It should be noted that in practical applications, those skilled in the art can select a suitable second operating clock frequency based on the design principles of the above formula and in combination with specific circuit process parameters, rather than being limited to the strictly calculated value of the above specific formula.

[0080] In one embodiment, to restore the N1-bit digital code DOUT1 output by ADC1 to the analog reconstructed signal VDA1 and provide a basis for subsequent residual signal calculation, this application provides an analog reconstructed signal calculation formula: Among them, the summation term Used to convert the binary code of DOUT1 to a decimal value. The i-th bit of DOUT1 takes the value 0 or 1, 2 i-1 This is the weight of that bit; adding 0.5 provides redundancy buffering for the quantization process to mitigate errors caused by signal fluctuations; multiply by (i.e., the quantization step size of ADC1) can accurately map the converted decimal value to the actual measurement range of ADC1.

[0081] Understandably, this formula, through step-by-step optimization design, achieves high-precision restoration of digital codes to analog signals, providing a reliable prerequisite for accurate calculation of residual signals.

[0082] In one embodiment, to prevent the initial amplitude of the residual signal Vres from being too large, causing the subsequent residual amplifier 5 to exceed its range, this application provides a residual signal amplitude constraint formula: Wherein, the residual signal Vres is the difference between the input signal Vin and the reconstructed signal VDA1, representing the detail signals not captured by ADC1 after coarse quantization (e.g., Vin = 2.53V, VDA1 = 2.512V, Vres = 0.018V); constraint range ± The quantization step size is determined by ADC1, for example, when FS=5V and N1=10 bits. ≈0.00244V, meaning the range of Vres is ±0.00244V.

[0083] Understandably, this constraint formula ensures that Vres is a low-amplitude, small signal, which facilitates the subsequent amplification processing by the residual amplifier 5, and also prevents amplification distortion caused by excessive initial signal amplitude, further guaranteeing the quantization accuracy of the system.

[0084] In one embodiment, to accurately amplify the residual signal Vres to a range suitable for ADC2 quantization, while preventing the amplifier output from exceeding its range, this application sets the gain G of the residual amplifier 5 to a fixed value. And provide the formula for residual constraint after amplification: This gain is the optimal solution after engineering optimization. For example, when N1=10 bits, G=512, it can amplify the previous ±0.00244V Vres to ±1.248V; when FS=5V, the constraint range of the residual after amplification is ±FS / 4=±1.25V, which is almost consistent with the amplified Vres (±1.248V).

[0085] Understandably, this design keeps the amplified residual signal within ±1 / 3 of the ADC2 range. Within, while the maximum input range of ADC2 is ± (That is, half of the ADC2 range is the safety boundary), therefore, the amplified residual signal is not only far from the edge of the ADC2 range, but also in the middle region where its linearity is optimal, reserving sufficient buffer space for signal fluctuations, effectively preventing the output of the residual amplifier 5 from entering the nonlinear region, while not occupying the entire range resources of the ADC2, thus balancing quantization accuracy and range utilization, ultimately ensuring that the ADC2 is always in a stable and high-precision quantization state. In one embodiment, in order to provide a clear quantization basis for the dynamic triggering logic and achieve precise control of the output swing of the residual amplifier 5, this application establishes a correspondence between the voltage range of the amplified residual and the ADC2 output digital code DOUT2: the maximum input range of the ADC2 is The corresponding DOUT2 binary codeword range is 00000…0~11111…1; the output voltage range of residual amplifier 5 is… The corresponding binary codeword range of DOUT2 is 00111…1~11000…0; when the two highest bits of DOUT2 (DOUT2[N2] and DOUT2[N2-1]) are all high (11) or all low (00), it means that the amplifier output voltage has reached the upper or lower boundary of the set range. At this time, ADC1 and DAC1 are triggered to perform quantization and reconstruction, so that VDA1 becomes larger or smaller, thereby adjusting Vres smaller or larger, limiting the amplifier output swing.

[0086] Understandably, this correspondence transforms the abstract voltage signal into an easily detectable digital code signal, eliminating the need for additional analog comparison circuits, simplifying the implementation of dynamic triggering logic, and ensuring the accuracy of the triggering timing.

[0087] In one embodiment, to adapt to the accuracy and power consumption requirements of different application scenarios, the dynamic triggering conditions of this application can be flexibly modified. The purpose is to limit the output of the residual amplifier 5 to a preset safety range. The DOUT2 codeword vector corresponding to the voltage at and outside the range boundary satisfies the triggering conditions. By triggering ADC1, the output of the residual amplifier 5 can be brought back to the set voltage range. For example, when the triggering condition is set to DOUT2≤01011…1 or ≥10100…0, the corresponding output voltage range of the residual amplifier 5 is ±FS / 8; when the triggering condition is set to DOUT2≤00011…1 or ≥11100…0, the corresponding output voltage range of the residual amplifier 5 is ±3*FS / 8. Compared with the basic triggering logic of "only detecting the highest two bits (DOUT2[N2], DOUT2[N2-1]) all 0 or all 1" in the above embodiment, these two cases are flexible extensions of the triggering conditions. By judging the state of the "highest 3 bits" of DOUT2, a narrower or wider voltage range constraint is achieved to adapt to different accuracy and power consumption requirements.

[0088] In one embodiment, to visually demonstrate the signal variation characteristics of the ADC of this application under different input signals, refer to... Figure 5 This application provides 8 signal waveform diagrams, categorized by signal type as sinusoidal signals (Sine) ( Figure 5 a to Figure 5 d) with ramp signal (Ramp) Figure 5 e to Figure 5 h) Two types of scenarios, which are explained below:

[0089] In one embodiment, to illustrate the system's operating state under a sinusoidal input signal, this application provides four sub-graphs depicting the sinusoidal signal scenario, as follows: Figure 5 Figure a shows the input signal Vin, which illustrates the voltage waveform when the input is a sinusoidal signal. Its amplitude varies periodically within ±1, serving as the quantization source for the ADC in this application. Figure 5 Figure b shows the analog reconstructed signal diagram of VDA1. This diagram shows the waveform of the analog reconstructed signal after quantization by ADC1. It presents a step-shaped curve that is consistent with the trend of the input sinusoidal signal, reflecting the coarse quantization effect of ADC1 on the input signal. Figure 5 c is the G*Vres (amplified residual signal) signal diagram. This diagram shows the residual signal waveform after amplification by residual amplifier 5. The dashed line in the diagram represents the ideal output range of the amplifier. It can be observed that the amplified residual is always within this range, which verifies the effectiveness of the residual amplitude constraint and amplifier gain design. Figure 5Figure d shows the trigger pulse signal of the first working clock CK1. The figure shows the waveform of the trigger pulse signal of ADC1. It can be seen that in the region where the slope of the input sine signal is large (the signal changes quickly), the pulse interval is short and the trigger frequency is high; in the region where the slope is small (the signal changes slowly), the pulse interval is long and the trigger frequency is low, which reflects the power consumption optimization characteristics of dynamic triggering.

[0090] Understandably, the four sub-graphs of the sinusoidal signal scenario clearly demonstrate the quantization accuracy and power consumption optimization effect of the ADC in this application under dynamic signals, ensuring that the residual after amplification is always within a safe range while achieving the adaptation of the trigger frequency and the rate of signal change.

[0091] In another embodiment, to illustrate the system's operating state under a ramp input signal, this application provides four sub-graphs for a ramp signal scenario: as follows Figure 5 Figure e shows the input signal diagram of the ramp type Vin. This figure illustrates the voltage waveform when the input is a slowly ramped signal, with its amplitude increasing linearly from -1 to 1. This is another type of signal source to be quantized in the ADC of this application; as shown... Figure 5 Figure f shows the analog reconstructed signal waveform of the VDA1 with a ramp-type quantization. This figure illustrates the waveform of the analog reconstructed signal after ADC1 quantization, exhibiting a uniform stepped curve consistent with the trend of the input ramp signal. This reflects the coarse quantization effect of the ADC1 on linear, slowly varying signals. Figure 5 As shown in g, the corresponding G*Vres signal diagram is displayed. This diagram shows the residual signal waveform after amplification by residual amplifier 5. The dashed line in the diagram represents the ideal output range of the amplifier. It can be observed that the amplified residual remains stable within this range, further verifying the versatility of residual constraint and gain design; as shown in g. Figure 5 As shown in h, this is the trigger pulse signal diagram of the first working clock CK1: This diagram shows the trigger pulse signal waveform of ADC1. It can be seen that the pulse interval is uniform and the trigger frequency is stable, which adapts to the linear change characteristics of the ramp signal and also achieves dynamic triggering with optimal power consumption.

[0092] It should be noted that the analog-to-digital converter of this application is not limited to the aforementioned sinusoidal and ramp signals. Its core constraint logic, dynamic triggering mechanism, and parameter design have broad applicability and can be adapted to various typical analog signal scenarios in the field of electronic engineering. For example, square wave signals commonly used in communication systems (used to test transient response and settling time), high-frequency radio frequency signals in 5G base stations or radar systems (with sampling rate requirements reaching GSPS level), physiological sensing signals in medical equipment (such as MRI and ultrasound), sensor output signals in industrial control scenarios (including slowly varying signals with DC offset), and transient pulse signals in scientific experiments can all be accurately quantized through the frequency constraint formula, residual amplitude control, and dynamic triggering logic of this application.

[0093] Understandably, regardless of whether the input signal is a periodic signal (such as a sine wave or square wave), a linearly changing signal (such as a ramp wave), or a non-periodic, noisy, and complex real-world signal, this application ensures that the signal change matches the quantization rhythm through the bidirectional constraint of the CK2 clock frequency, avoids over-range distortion through residual signal amplitude limitation and amplifier gain optimization, and dynamically adjusts the quantization timing of ADC1 through the DOUT2 digital code trigger logic. By adapting to the signal change characteristics, ensuring quantization accuracy, and optimizing power consumption, this application can maintain stable conversion performance in various signal scenarios, further broadening the application adaptability of this application's ADC in multiple fields such as communication, medical, industrial control, and radar remote sensing.

[0094] This application also provides a control method for a pipelined analog-to-digital converter, applied to a pipelined analog-to-digital converter including a first analog-to-digital converter 1 (ADC1) and a second analog-to-digital converter 3, comprising the following steps:

[0095] S1. The second analog-to-digital converter 3 (ADC2) continuously quantizes the residual signal (the signal amplified by gain G after Vres) using a preset second operating clock (CK2) to generate a second digital code (DOUT2). The upper frequency limit of CK2 is determined by the resolution of ADC2 (e.g., 300MHz for a 10-bit ADC2), and the lower frequency limit is constrained by the output formula of the residual amplifier 5. and ADC2 normal operation constraint formula The limitation ensures adaptation to changes in the input signal (Vin). The residual signal Vres is the difference between the input signal Vin and the analog signal (VDA1) reconstructed by DAC1 after quantization by ADC1.

[0096] S2. Monitor the code value of the second digital code (DOUT2) in real time, and generate a trigger signal when the code value meets the preset trigger conditions;

[0097] In some embodiments, the trigger condition is that the two highest bits of DOUT2 (DOUT2[N2] and DOUT2[N2-1]) are all 1 or all 0 (e.g., 10 bits of DOUT2 correspond to "1100000000" or "0011111111"). Using the state of the two highest bits of the second digital code as the trigger judgment standard simplifies the detection logic of the trigger condition, eliminates the need for complex signal processing algorithms, and reduces the execution complexity of the control method. At the same time, this trigger condition can directly reflect the amplitude boundary state of the residual signal, ensuring timely triggering of updates when the residual signal approaches the range of the second analog-to-digital converter 3, effectively reducing the probability of distortion of the residual amplifier 5 and input over-range, and ensuring the stability of quantization accuracy.

[0098] In other embodiments, the conditions can also be flexibly adjusted to "≤01011…1 or ≥10100…0" and other conditions, corresponding to different amplifier output voltage ranges (such as ±FS / 8, ±3FS / 8). The flexible expansion of the triggering conditions can adapt to different accuracy and power consumption requirements.

[0099] S3. In response to the trigger signal, the first analog-to-digital converter 1 (ADC1) is triggered to perform a quantization operation on the input signal (Vin) to generate the first digital code (DOUT1). The analog signal VDA1 is reconstructed and updated by ADC1, and then the residual signal Vres is updated. For example, when the input is a sinusoidal signal, the DOUT2 region with a larger signal slope is more likely to trigger the condition, and the trigger frequency of ADC1 is higher (shorter pulse interval). When the signal slope is smaller, the trigger frequency is lower (longer pulse interval). When the input is a slowly sloping signal, the trigger frequency is stable (uniform pulse interval).

[0100] By adopting the above technical solution, the control method of this application is based on the continuous quantization of the second analog-to-digital converter 3. By monitoring the triggering state of the second digital code in real time, the first analog-to-digital converter 1 is adaptively triggered, realizing the dynamic adjustment of the sampling rate. There is no need to pre-set a fixed first working clock frequency. Instead, the quantization timing is flexibly adjusted according to the state of the residual signal derived from the input signal. This solves the problem of insufficient accuracy when the input signal has a large rate of change at a fixed frequency, and avoids the waste of power consumption when the signal is flat. This enables the analog-to-digital converter to achieve the optimal balance between power consumption and accuracy under different input scenarios. The operation logic is simple and easy to implement in hardware.

[0101] In one embodiment, the step of updating the residual signal includes:

[0102] S31. The quantization result (DOUT1) of the first analog-to-digital converter 1 (ADC1) is converted into an analog reconstructed signal (VDA1) through the digital-to-analog converter 21 (DAC1). The conversion process uses the following formula: The summation term converts the binary code of DOUT1 to a decimal value, and the addition of 0.5 provides redundant buffering for the quantization process to mitigate signal fluctuation errors. Multiplying by... The quantization step size of ADC1 accurately maps decimal values ​​to the actual range of ADC1. At the same time, the delay matching module compensates for the delay from the input of ADC1 to the output of DAC1, ensuring that VDA1 is phase-aligned with the input signal Vin.

[0103] S32. Subtract the analog reconstructed signal (VDA1) from the input signal (Vin) to obtain the updated residual signal (Vres), which satisfies the amplitude constraint formula: This ensures that Vres is a low-amplitude, small signal, accurately reflecting the detailed information that was not captured after coarse quantization by ADC1.

[0104] S33. The updated residual signal (Vres) is amplified by a residual amplifier, with the amplifier gain G set to a fixed value. After amplification, the signal G*Vres is obtained, which satisfies the constraint formula: The signal is adapted to the safe quantization range of the second analog-to-digital converter 3 (ADC2) (half of the ADC2 range), and then the amplified residual signal is input into the second analog-to-digital converter 3 (ADC2) for continuous quantization.

[0105] By adopting the above technical solution, the update process of the residual signal is clarified. The analog reconstruction of the quantization result is realized through the digital-to-analog converter 21, and the signal phase alignment is ensured by the delay matching module, laying the foundation for the accuracy of the subtraction operation. The new residual signal obtained by the subtraction operation is strictly limited to a low amplitude range, avoiding the risk of distortion in the subsequent amplification process from the source. The targeted amplifier gain design not only accurately amplifies the residual signal to the effective range that ADC2 can quantize, but also does not waste the range resources of ADC2, ensuring that the updated residual signal can accurately reflect the latest state of the input signal. At the same time, the amplification step further improves the recognizability of the residual signal, enabling the second digital code (DOUT2) to accurately map the amplitude change of the residual signal, providing a reliable basis for the judgment of subsequent trigger conditions, ensuring the closed-loop stability of the "quantization-reconstruction-residual update-requantization" adaptive control process, and finally realizing the dynamic adaptation of the ADC1 operating frequency and the rate of change of the input signal.

[0106] The control method of this application achieves dynamic optimization of the sampling rate through a closed-loop process of "continuous quantization - real-time monitoring - adaptive triggering - signal update", enabling the analog-to-digital converter to adapt to input signals with different rates of change, thus broadening the application scenarios and balancing power consumption and accuracy.

[0107] The above are all preferred embodiments of this application, and are not intended to limit the scope of protection of this application. Therefore, all equivalent changes made in accordance with the structure, shape and principle of this application should be covered within the scope of protection of this application.

Claims

1. A pipelined analog-to-digital converter with adaptive sampling rate, characterized in that, include: A first analog-to-digital converter (1) is used to quantize the input signal in response to a first operating clock and generate a first digital code; The residual generation module (2) is connected to the output terminal of the first analog-to-digital converter (1) and simultaneously receives the input signal to generate a residual signal based on the first digital code and the input signal. The residual generation module (2) includes: a digital-to-analog converter (21), connected to the output of the first analog-to-digital converter (1), for converting the first digital code into an analog reconstruction signal; and a subtractor (22), whose input receives the input signal and the analog reconstruction signal, for subtracting the analog reconstruction signal from the input signal to obtain the residual signal. The second analog-to-digital converter (3) is connected to the output of the residual generation module (2) and is used to quantize the residual signal with the second working clock to generate a second digital code; The dynamic triggering logic module (4) has its input terminal connected to the output terminal of the second analog-to-digital converter (3) and its output terminal connected to the input terminal of the first analog-to-digital converter (1). It is used to receive the second digital code and generate the first working clock. The dynamic triggering logic module (4) includes a logic gate circuit and at least two cascaded flip-flop circuits. The input terminal of the logic gate circuit is connected to the output terminal of the second analog-to-digital converter (3). The input terminal of the flip-flop circuit is connected to the output terminal of the logic gate circuit. The output terminal outputs the first working clock. The dynamic triggering logic module (4) transmits signals through the logic gate circuit and the flip-flop circuit, so that the effective edge of the output first working clock lags behind the preset trigger edge of the second working clock. The dynamic triggering logic module (4) is configured to monitor the second digital code and generate a pulse of the first working clock when the second digital code meets the preset triggering conditions, so as to trigger the first analog-to-digital converter (1) to perform a quantization operation.

2. The pipelined analog-to-digital converter according to claim 1, characterized in that, The preset triggering condition is that the most significant bit and the second most significant bit of the second digital code are both 0 or both are 1.

3. The pipelined analog-to-digital converter according to claim 1, characterized in that, It also includes a residual amplifier (5), which is disposed between the residual generation module (2) and the second analog-to-digital converter (3) for amplifying the residual signal.

4. The pipelined analog-to-digital converter according to claim 1, characterized in that, It also includes a delay module (6), whose input end is connected to the input end of the first analog-to-digital converter (1) and whose output end is connected to the input end of the subtractor (22), for matching the delay between the input end of the first analog-to-digital converter (1) and the output end of the digital-to-analog converter (21).

5. A control method for a pipelined analog-to-digital converter, applied to a pipelined analog-to-digital converter including a first analog-to-digital converter (1) and a second analog-to-digital converter (3), characterized in that, Includes the following steps: S1. The second analog-to-digital converter (3) continuously quantizes the residual signal using a preset second working clock to generate a second digital code; S2. Monitor the code value of the second digital code in real time, and generate a trigger signal when the code value meets the preset triggering conditions; S3. In response to the trigger signal, the first analog-to-digital converter (1) is triggered to perform a quantization operation on the input signal at a first working clock to update the residual signal; The steps for updating the residual signal include: S31. The quantization result of the first analog-to-digital converter (1) is converted into an analog reconstructed signal by the digital-to-analog converter (21); S32. Subtract the analog reconstructed signal from the input signal to obtain the updated residual signal; S33. The updated residual signal is amplified and then input into the second analog-to-digital converter (3) for quantization. The frequency of the second operating clock is configured according to the frequency of the input signal, and the two satisfy the following relationship: ; , where α is the ratio of the input signal frequency to the second working clock frequency, N1 is the quantization bit of the first analog-to-digital converter (1), FS is the range of the second analog-to-digital converter (3), and Ain is the swing of the input signal.

6. The control method according to claim 5, characterized in that, The preset triggering condition is that the most significant bit and the second most significant bit of the second digital code are both 0 or both are 1.

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