Method and apparatus for distributed coherent waveform generation and reception with variable symbol rate
Patent Information
- Application Number
- CN202511469230.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2025-10-15
- Publication Date
- 2026-10-20
- Estimated Expiration
- 2045-10-15
AI Technical Summary
但在进行节点的相对距离测量时,由于时间同步、器件等原因,总会引入误差,而引入的误差会带来预补偿的时延估计错误,从而造成接收端各个到达信号的相位不同步
[0011]本申请实施例还提出一种变码元速率的分布式相干波形通信系统,包括如前述的变码元速率的分布式相干波形生成装置和前述的变码元速率的分布式相干波形接收装置。
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Figure CN121547328B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the fields of signal processing and distributed coherent technology, and in particular to a method and device for generating and receiving distributed coherent waveforms with variable symbol rate. Background Technology
[0002] To achieve accurate distributed coherence, multiple nodes need to control the signal transmission delay, phase, and frequency based on high-precision time synchronization and their distance from the destination node. This aims to generate a coherent effect at the receiving node and improve the signal-to-noise ratio. However, when measuring the relative distance between nodes, errors are always introduced due to time synchronization and device limitations. These errors lead to incorrect pre-compensation delay estimations, resulting in phase asynchrony among arriving signals at the receiving end. For high symbol rate signals, the signal bandwidth is large, and the phase changes rapidly over time; even a small time error can cause a significant phase deviation. Conversely, for low symbol rate signals, the signal bandwidth is narrow, and the same time error results in a smaller phase change. Furthermore, for relative time synchronization, at the same sampling rate, a higher symbol rate leads to faster signal phase changes and more accurate estimated signal arrival times. In contrast, a lower symbol rate results in less significant signal phase changes at different sampling times, leading to larger signal arrival time errors.
[0003] Compared to traditional MIMO where multiple antennas reside on a single node and signal processing is also performed at that node, coherent multi-antenna systems distribute multiple antennas across multiple nodes, relying on cooperative communication to form aggregated signals, with signal processing also being distributed across multiple nodes. For distributed multi-node systems to generate coherent phenomena, time, frequency, and phase alignment is required. Therefore, time, frequency, and phase synchronization must be performed first, followed by signal synthesis under unified spatiotemporal conditions.
[0004] Assume that N nodes use distributed coherent cooperation to transmit to a single user, and the transmit power of each user is... By appropriately setting the initial phase to achieve beam superposition—that is, the peaks of all cooperating users superimpose their peaks and the troughs superimpose their troughs—then the signal received at the receiver will be... ,in Let be the noise standard deviation. Then the signal-to-noise ratio of the system is... In other words, ideally, when N users collaborate, the maximum signal-to-noise ratio gain is... In practice, due to factors such as component performance and time-space accuracy, its gain will be less than [the actual gain]. .
[0005] The prior art, CN 102523619 A, involves a communication system comprising a cluster of distributed single-antenna nodes and a remote wireless base station. The system employs time-division duplexing, and the information collected by the node cluster is transmitted to the remote base station through coherent cooperation. This invention mainly designs a communication cooperation process, estimating time, frequency, and phase errors through multiple information exchanges between master and slave nodes, thereby improving the signal-to-noise ratio of the coherent signal. Summary of the Invention
[0006] This application provides a method and device for generating and receiving distributed coherent waveforms with variable symbol rates, which combines the advantages of different symbol rates to design communication waveforms for high symbol rate synchronization segments and low symbol rate data segments. This satisfies the requirements for precise time synchronization of distributed coherent signals and makes it easier for data segment signals to achieve coherence, thereby improving the signal-to-noise ratio of data segment signals.
[0007] This application provides a distributed coherent waveform generation method with variable symbol rate, which employs waveform synchronization segments and data segments, and is implemented based on a multi-channel parallel processing architecture, so that the waveform synchronization segment and data segment signals with different symbol rates operate in the same clock domain; wherein, The waveform synchronization segment uses a first signal sequence with a first symbol rate, which is modulated and interpolated in parallel through multiple channels. Multiple signals are then subjected to shaping filtering in parallel, waiting to be framed with the data segment. The first symbol rate is used for carrier acquisition and time synchronization between distributed nodes. The first symbol rate is much greater than the second symbol rate of the data segment. The data segment, based on the original data with the second symbol rate, is modulated and then digitally up-converted in parallel through multiple interpolations and multi-phase compensation filtering to frame the waveform synchronization segment. Distributed nodes synchronize their time according to the first symbol rate. Based on the same first sampling rate, the waveform synchronization segment and the data segment are assembled into a frame signal in chronological order, and then transmitted after conversion.
[0008] This application provides a method for receiving distributed coherent waveforms with variable symbol rate, including: Determine the clock domain for the waveform synchronization segment and data segment signals; The data sampled at the first sampling rate is output in parallel to the waveform synchronization segment processing and the data segment processing. The waveform synchronization segment processing performs the following: Parallel multi-channel data is matched and filtered, and frames are captured. The captured portion is correlated with the local sequence to obtain the correlation peak, thus completing frame synchronization detection. By using timed synchronization, the optimal sampling point is obtained, and the symbol boundary of the waveform synchronization segment is determined in order to obtain data at the first symbol rate. The timed synchronized data is then synchronized with the carrier in parallel, and the initial relevant parameters of the data segment carrier synchronization loop are estimated. After completing the processing of the synchronization sequence of the predetermined length, the data segment processing is triggered, and the following is executed: The data sampled at the first sampling rate is digitally down-converted in parallel and then converted into clock domain data through digital filtering and multiphase compensation filtering. The transformed clock domain data is processed through matched filtering and timing synchronization to restore it to data at a second symbol rate, wherein the first symbol rate is much greater than the second symbol rate. The data at the second symbol rate is estimated by carrier synchronization and related parameters are processed to demodulate and recover the communication data.
[0009] This application also proposes a distributed coherent waveform generation device with variable symbol rate, including a processor and a memory. The memory stores a computer program, which, when executed by the processor, implements the steps of the method described above.
[0010] This application also proposes a variable symbol rate distributed coherent waveform receiving device, including a processor and a memory, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the steps of the method described above.
[0011] This application also proposes a variable symbol rate distributed coherent waveform communication system, including the aforementioned variable symbol rate distributed coherent waveform generation device and the aforementioned variable symbol rate distributed coherent waveform receiving device.
[0012] The waveform synchronization segment and data segment in this application embodiment are implemented based on a multi-channel parallel processing architecture, which enables waveform synchronization segment and data segment signals with different symbol rates to operate in the same clock domain. Moreover, the first symbol rate of the waveform synchronization segment is much greater than the second symbol rate of the data segment. This combines the advantages of different symbol rates to design communication waveforms for high symbol rate synchronization segments and low symbol rate data segments. This satisfies the requirements for distributed coherent and precise time synchronization, and makes it easier for the data segment signal to achieve coherence, thereby improving the signal-to-noise ratio of the data segment signal.
[0013] The above description is only an overview of the technical solution of this application. In order to better understand the technical means of this application and to implement it in accordance with the contents of the specification, and to make the above and other objects, features and advantages of this application more obvious and understandable, the following are specific embodiments of this application. Attached Figure Description
[0014] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the scope of this application. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings: Figure 1 This is a flowchart illustrating the distributed coherent waveform generation method with variable symbol rate according to an embodiment of this application. Figure 2 This is a time-domain and frequency-domain illustration of the distributed coherent waveform generated by the variable symbol rate according to an embodiment of this application. Figure 3 This is a flowchart illustrating the distributed coherent waveform receiving method with variable symbol rate according to an embodiment of this application. Figure 4 This is a measured signal gain for the distributed coherent waveform generation and reception points with variable symbol rate in an embodiment of this application. Detailed Implementation
[0015] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.
[0016] This application provides a distributed coherent waveform generation method with variable symbol rate, employing waveform synchronization segments and data segments, and implemented based on a multi-channel parallel processing architecture, so that the waveform synchronization segment and data segment signals with different symbol rates operate in the same clock domain; such as Figure 1 As shown, where, The waveform synchronization segment uses a first signal sequence with a first symbol rate, which is modulated and interpolated in parallel through multiple channels. Multiple signals are then subjected to shaping filtering in parallel, waiting to be framed with the data segment. The first symbol rate is used for carrier acquisition and time synchronization between distributed nodes. The first symbol rate is much greater than the second symbol rate of the data segment. The data segment, based on the original data with the second symbol rate, is modulated and then digitally up-converted in parallel through multiple interpolations and multi-phase compensation filtering to frame the waveform synchronization segment. Distributed nodes synchronize their time according to the first symbol rate. Based on the same first sampling rate, the waveform synchronization segment and the data segment are assembled into a frame signal in chronological order, and then transmitted after conversion.
[0017] In some embodiments, the first symbol rate is greater than ten times the second symbol rate.
[0018] Based on the technical concept of this application, this embodiment proposes a specific example. Other specific modulations, first symbol rates, second symbol rates, and clock domains can be adjusted according to actual needs, and this embodiment does not provide examples for each. In one example of this application, the waveform synchronization segment uses a Gray sequence with a first symbol rate of 300 Msps to achieve carrier acquisition and time synchronization between distributed nodes. The data segment uses a modulation signal (including but not limited to PSK, QAM, etc.) with a second symbol rate of 9.375 Msps for data transmission. The time and frequency domain diagrams of this waveform are shown below. Figure 2 As shown.
[0019] In this example, the FPGA implementation employs a multi-parallel processing architecture, enabling synchronization and data segment signals with different symbol rates to operate within the same clock domain (37.5MHz, or other clock domains), thus avoiding system instability issues caused by clock switching. A specific example of the signal generation process at the transmitting end based on the method of this application embodiment is as follows: (1) Synchronization segment processing: Gray sequence with good autocorrelation characteristics is adopted, and the symbol rate is 300Msps; after BPSK modulation, 8 channels enter interpolation in parallel, and the oversampling rate is set to 4, corresponding to a sampling rate of 1.2Gsps; 32 channels enter shaping filter in parallel (root raised cosine filter is used in this example, and the specific settings can be adjusted according to needs), waiting to be framed with the data segment signal.
[0020] (2) Data segment processing: The raw data with a symbol rate of 9.375 Msps is processed using a two-stage interpolation filter of 4*32 (to prevent excessive resource consumption of a single high-order filter), as detailed below. Figure 2 As shown, it first enters 4x interpolation and shaping filtering, then 32x digital filtering CIC interpolation and multiphase compensation filtering; 32 channels enter digital upconversion in parallel (upconverted to 70MHz in this example, but other frequencies are also possible), waiting to be framed with the synchronization segment signal.
[0021] (3) Frame control and radio frequency transmission: The data of the synchronization segment and the data segment are both sampled at a rate of 1.2 Gsps. Therefore, they can be directly assembled into a frame signal in time sequence, converted into an analog signal by a DAC, up-converted to the radio frequency, and then transmitted after passing through a power amplifier.
[0022] In some embodiments, assembling the waveform synchronization segment and the data segment into a frame signal in chronological order includes: in the time domain, framing according to the sequential order of the waveform synchronization segment and the data segment; and in the frequency domain, the bandwidth of the synchronization segment at the first symbol rate is much larger than the bandwidth of the data segment at the second symbol rate. That is, the framed data structure is as follows: Figure 2 As shown.
[0023] The method in this embodiment uses a Gray sequence with a symbol rate of ≥200Msps for the synchronization segment and a BPSK modulation signal with a symbol rate of ≤20Msps for the data segment. The symbol rate of the synchronization segment is ≥10 times that of the symbol rate of the data segment, ensuring that the time synchronization accuracy supported by the synchronization segment can meet the time synchronization requirements of the data segment signal aggregation.
[0024] This application adopts a single-clock-domain parallel implementation architecture, which processes high-speed data in the synchronous segment through multiple parallel processing channels and generates and receives high-multiple (128 times) oversampled signals through multi-level decimation / interpolation. This ensures that the entire system operates in a fixed master clock domain (37.5MHz), avoiding the clock switching problem caused by different clock domains processing different symbol rates, and making it easier to implement in engineering.
[0025] This application also proposes a method for receiving distributed coherent waveforms with variable symbol rates, comprising the following steps: Determine the clock domain for the waveform synchronization segment and data segment signals; The data sampled at the first sampling rate is output in parallel to the waveform synchronization segment processing and the data segment processing. The waveform synchronization segment processing performs the following: Parallel multi-channel data is matched and filtered, and frames are captured. The captured portion is correlated with the local sequence to obtain the correlation peak, thus completing frame synchronization detection. By using timed synchronization, the optimal sampling point is obtained, and the symbol boundary of the waveform synchronization segment is determined in order to obtain data at the first symbol rate. The timed synchronized data is then synchronized with the carrier in parallel, and the initial relevant parameters of the data segment carrier synchronization loop are estimated. After completing the processing of the synchronization sequence of the predetermined length, the data segment processing is triggered, and the following is executed: The data sampled at the first sampling rate is digitally down-converted in parallel and then converted into clock domain data through digital filtering and multiphase compensation filtering. The transformed clock domain data is processed through matched filtering and timing synchronization to restore it to data at a second symbol rate, wherein the first symbol rate is much greater than the second symbol rate; in some embodiments, the first symbol rate is greater than ten times the second symbol rate.
[0026] The data at the second symbol rate is estimated by carrier synchronization and related parameters are processed to demodulate and recover the communication data.
[0027] In some embodiments, the relevant parameters for the initial data segment carrier synchronization loop include carrier frequency offset and initial phase offset.
[0028] In some embodiments, the entry into the data segment processing is triggered by data switching control logic.
[0029] Based on the technical concept of this application, this embodiment proposes a specific example. Other specific modulations, first symbol rates, second symbol rates, and clock domains can be adjusted according to actual needs, and this application embodiment does not provide examples of each. In one example of this application, the waveform synchronization segment uses a Gray sequence with a first symbol rate of 300 Msps to achieve carrier acquisition and time synchronization between distributed nodes. The data segment uses a modulation signal (including but not limited to PSK, QAM, etc.) with a second symbol rate of 9.375 Msps for data transmission. At the receiving end, corresponding to the aforementioned application example, the signal processing flow at the receiving end of this application embodiment is as follows: Figure 3 As shown: (1) The ADC samples the analog signal at 1.2Gsps and outputs 32 parallel channels to the synchronization segment processing and data segment processing. The working clock is 37.5MHz, which corresponds to the transmitting end, but can be other working clocks.
[0030] (2) Waveform synchronization segment processing: 32 channels of 1.2Gsps data are fed into the matched filter module (root raised cosine filter is used in this example) and output to the frame capture module; the frame capture part obtains the correlation peak by correlating with the local sequence and completes the frame synchronization detection; then, through timed synchronization (Gardner algorithm is used in this example), the best sampling point is obtained and the symbol boundary of the synchronization segment is determined. At this time, the data rate becomes the first symbol rate of 300Msps; the data after timed synchronization enters the carrier synchronization module in parallel in 8 channels to estimate the carrier frequency offset and initial phase offset. These parameters are used as the initial values of the data segment carrier synchronization loop.
[0031] Once the synchronization sequence of the predetermined length has been processed, the data switching control logic is triggered to process the data segment: (3) 1.2Gsps data enters the digital downconversion module in parallel through 32 channels. After being filtered by a 32x digital CIC filter and a multiphase compensation filter, it becomes 37.5Msps data in the clock domain. After being filtered by a matched filter (a root raised cosine filter is used in this example) and a timing synchronization module, the data rate becomes the second symbol rate of 9.375Msps. The data after timing synchronization is estimated and compensated for by the carrier frequency offset and initial phase offset by the carrier synchronization module. Finally, the communication data is restored by the demodulation module.
[0032] The embodiments in this application only describe the waveform design and implementation process. There are mature methods for specific multi-node distributed coherent processes and time synchronization, frequency synchronization and phase synchronization, which will not be described in detail in this application.
[0033] Using the waveform and device of this invention, the signal gain at the two nodes reached 4.2 dB (the theoretical gain is 20log2 = 6.02 dB). Specific measured results are as follows: Figure 4 As shown.
[0034] This application's method fully leverages the high time resolution and high synchronization efficiency brought by high symbol rates, as well as the higher tolerance for time-frequency errors at low symbol rates in distributed coherent circuits. It enables more efficient signal aggregation without external time synchronization, achieving reliable transmission with low power, long distance, and strong interference resistance. Furthermore, for this type of waveform design method, this application designs a dual-segment parallel processing architecture, with both the high-speed synchronization processing segment and the low-speed data processing segment using fixed clocks, eliminating the risk of core clock switching and making it easier to implement in engineering.
[0035] This application also proposes a distributed coherent waveform generation device with variable symbol rate, including a processor and a memory. The memory stores a computer program, which, when executed by the processor, implements the steps of the method described above.
[0036] This application also proposes a variable symbol rate distributed coherent waveform receiving device, including a processor and a memory, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the steps of the method described above.
[0037] This application also proposes a variable symbol rate distributed coherent waveform communication system, including the aforementioned variable symbol rate distributed coherent waveform generation device and the aforementioned variable symbol rate distributed coherent waveform receiving device.
[0038] It should be noted that, in the embodiments of this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes that element.
[0039] The sequence numbers of the embodiments in this application are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.
[0040] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods of the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal (which may be a mobile phone, computer, server, air conditioner, or network device, etc.) to execute the methods described in the various embodiments of this application.
[0041] The embodiments of this application have been described above with reference to the accompanying drawings. However, this application is not limited to the specific embodiments described above. The specific embodiments described above are merely illustrative and not restrictive. Those skilled in the art can make many other forms under the guidance of this application without departing from the spirit and scope of the claims. All of these forms are within the protection scope of this application.
Claims
1. A method for generating distributed coherent waveforms with variable symbol rate, characterized in that, It employs waveform synchronization segments and data segments, implemented using a multi-channel parallel processing architecture, enabling waveform synchronization and data segment signals with different symbol rates to operate in the same clock domain; among which, The waveform synchronization segment uses a first signal sequence with a first symbol rate, which is modulated and interpolated in multiple parallel paths. After multiple oversampling, the multiple signals are subjected to shaping filtering in parallel, waiting to be framed with the data segment. The first symbol rate is used for carrier acquisition and time synchronization between distributed nodes. The first symbol rate is greater than ten times the second symbol rate of the data segment. The data segment, based on the original data with the second symbol rate, is modulated and sequentially passed through the first-level interpolation and shaping filter, the second-level digital filter interpolation and multi-phase compensation filter, and digital up-conversion is performed in parallel to frame the waveform synchronization segment. Distributed nodes synchronize their time according to the first symbol rate. Based on the same first sampling rate, the waveform synchronization segment and the data segment are assembled into a frame signal in chronological order. The frame signal is converted into an analog signal through digital-to-analog conversion, and then transmitted after up-conversion and power amplification.
2. The distributed coherent waveform generation method with variable symbol rate as described in claim 1, characterized in that, Assembling the waveform synchronization segment and the data segment into a signal frame in chronological order includes: In the time domain, frames are assembled according to the order of waveform synchronization segment and data segment. In the frequency domain, the bandwidth of the synchronization segment at the first symbol rate is much greater than the bandwidth of the data segment at the second symbol rate.
3. A method for receiving distributed coherent waveforms with variable symbol rate, characterized in that, include: Determine the clock domain for the waveform synchronization segment and data segment signals; The data sampled at the first sampling rate is output in parallel to the waveform synchronization segment processing and the data segment processing. The waveform synchronization segment processing performs the following: The parallel multi-channel data is matched and filtered and then captured. The captured part is correlated with the local sequence to obtain the correlation peak and complete the frame synchronization detection. By using timed synchronization, the optimal sampling point is obtained, and the symbol boundary of the waveform synchronization segment is determined in order to obtain data at the first symbol rate. The timed synchronized data is then synchronized with the carrier in parallel, and the initial relevant parameters of the data segment carrier synchronization loop are estimated. After completing the processing of the synchronization sequence of the predetermined length, the data segment processing is triggered, and the following is executed: The data sampled at the first sampling rate is digitally down-converted in parallel and then converted into clock domain data through digital filtering and multiphase compensation filtering. The transformed clock domain data is processed through matched filtering and timing synchronization to restore it to data at the second symbol rate, wherein the first symbol rate is greater than ten times the second symbol rate. The data at the second symbol rate is demodulated and recovered by estimating the carrier synchronization and compensating for the carrier frequency offset and initial phase shift.
4. The distributed coherent waveform reception method with variable symbol rate as described in claim 3, characterized in that, The initial parameters of the data segment carrier synchronization loop include carrier frequency offset and initial phase offset.
5. The distributed coherent waveform reception method with variable symbol rate as described in claim 3, characterized in that, The process of entering the data segment is triggered by the data switching control logic.
6. A distributed coherent waveform generation device with variable symbol rate, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, implements the steps of the method as described in claim 1 or 2.
7. A distributed coherent waveform receiving device with variable symbol rate, characterized in that, It includes a processor and a memory, wherein the memory stores a computer program that, when executed by the processor, implements the steps of the method as described in any one of claims 3 to 5.
8. A distributed coherent waveform communication system with variable symbol rate, characterized in that, It includes the variable symbol rate distributed coherent waveform generation device as described in claim 6 and the variable symbol rate distributed coherent waveform receiving device as described in claim 7.
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