Semiconductor structure and its fabrication method

Abstract

This invention discloses a semiconductor structure and its fabrication method, belonging to the semiconductor field. This invention changes the stress silicon technology process in the existing fin transistor fabrication technology by advancing the source and drain stress silicon epitaxy to before fin formation. The fins are directly etched using a self-aligned technique with a hard mask layer on the fins. An unexpected technical advantage is that this invention eliminates the need for a hard mask layer removal process; after subsequent deposition of the interlayer dielectric layer, the source, drain, and gate can be brought out via a via process. It also eliminates the need for the complex epitaxy techniques of high carrier mobility semiconductor materials, simplifying the manufacturing process and reducing control complexity. This invention employs a method of first forming the well region and then epitaxially forming the MOS region, combined with fin epitaxy technology. This allows the stress silicon technology to be extended into the gate, increasing the channel carrier mobility, resulting in lower energy consumption and enabling the fabrication of high-quality fin transistors.

Description

Technical Field

[0001] This invention belongs to the field of semiconductors and relates to a transistor manufacturing technology, specifically a semiconductor structure and its manufacturing method. Background Technology

[0002] FinFETs are field-effect transistors based on a three-dimensional architecture, named for their gate structure resembling a fish fin. This technology upgrades traditional planar transistors to a three-dimensional fin-shaped channel structure, achieving dual-side circuit control through a forked gate, effectively improving the gate's control over the channel and significantly reducing leakage current. Current FinFET fabrication typically involves first forming the fins, removing the top hard mask, and then using stressed silicon technology to re-epitaxy generate SiC (silicon carbide) and SiGe (silicon germanium or silicon germanium) to obtain a channel with high carrier mobility. However, both removing the top hard mask and epitaxially generating SiC and SiGe as the fins are technically challenging processes.

[0003] First, precisely and non-destructively removing the top hard mask is extremely difficult. The top hard mask (usually silicon nitride) needs to be removed with 100% selectivity, meaning the etching process can only etch the silicon nitride, without damaging the exposed silicon fins (Si fins) and the surrounding shallow trench isolation (STI) silicon oxide (SiO2). Any over-etching of the silicon fins will result in smaller fin sizes and poorer shapes, directly altering the critical electrical characteristics of the transistor. The etching must be extremely uniform; uneven removal across the entire wafer or even a single chip will cause some areas of the fins to be prematurely exposed and etched, while other areas remain with the top hard mask. Furthermore, the top hard mask must be completely removed without any residue. Even tiny residues can hinder subsequent epitaxial growth, leading to defects in the epitaxial material or the formation of undesirable crystal planes.

[0004] Secondly, after removing the top hard mask, it is very difficult to perform high-quality epitaxial growth of stressed silicon on the exposed silicon fins, specifically in the following aspects:

[0005] First, epitaxial growth can only occur on exposed silicon surfaces (the top and sides of the fins), and not on surrounding insulating layers (such as SiO2 in STI) or any residual hard mask. Non-selective growth on any insulating medium will result in polysilicon, leading to short circuits, leakage, and performance degradation.

[0006] Secondly, the epitaxial growth of silicon-germanium (SiGe) on the fins of a PMOS requires precise control of the germanium (Ge) concentration (typically >25%), because the Ge content directly determines the magnitude of the compressive stress applied to the channel, thus affecting the hole mobility. Inconsistent Ge concentration can lead to inconsistent device performance.

[0007] Third, silicon carbide (SiC) is epitaxially grown on the fins of the NMOS. This requires precisely doping carbon (C) atoms into the silicon lattice. The atomic radius of C is very small, and its doping generates tensile stress, increasing electron mobility. However, C doping is very difficult, easily forming defects (such as dislocations), and achieving high carbon concentrations is challenging.

[0008] Fourth, morphology control is difficult. The interface between the epitaxial layer and the original silicon fins must be atomically flat and defect-free. Any interface defects will become scattering centers for charge carriers, reducing mobility and contradicting the initial goal of improving performance. Epitaxial growth requires the formation of ideal, symmetrical "diamond" or "octahedral" shapes. The process must precisely control the difference in epitaxial growth rate across various crystal planes. Irregular shapes will lead to uneven stress distribution and abnormal electric field distribution.

[0009] Fifth, epitaxial growth is usually carried out at relatively high temperatures, so the temperature needs to be strictly controlled to prevent unnecessary impurity re-diffusion in the previously completed device structure (such as lightly doped source-drain extension regions), which would affect the short-channel effect of the device.

[0010] In summary, there are many difficulties in the existing fin transistor fabrication process to improve device performance using stressed silicon technology. Therefore, it is necessary to conduct relevant research and propose a new process route that may avoid some or all of the above-mentioned problems. Summary of the Invention

[0011] One of the objectives of this invention is to provide a method for fabricating a semiconductor structure. By advancing the stress silicon epitaxy of the source and drain electrodes before the formation of the fins, the fins are formed directly by trenching and filling on the substrate, and a hard mask is formed on the fins. This allows the subsequent processes of this invention to obtain high-quality transistor devices without removing the hard mask or forming the source and drain electrodes again.

[0012] Another objective of this invention is to provide a method for fabricating a finned transistor. Based on the aforementioned semiconductor structure fabrication method, the source, drain, and gate can be directly brought out through through-silicon via (TSV) technology by depositing an interlayer dielectric layer, thereby enabling the low-cost fabrication of a high-quality finned transistor.

[0013] To solve the above-mentioned technical problems, the present invention employs the following technical means:

[0014] In a first aspect, the present invention provides a method for fabricating a semiconductor structure, comprising the following steps:

[0015] Provide semiconductor substrates;

[0016] P-well and N-well regions are formed on the semiconductor substrate, respectively;

[0017] An epitaxial silicon layer and a first sacrificial layer are sequentially fabricated on a semiconductor substrate;

[0018] A first groove is etched on the epitaxial silicon layer, wherein the first groove extends to the P-well region or N-well region of the semiconductor substrate;

[0019] High carrier mobility semiconductor materials are epitaxially grown in the first groove to form fins of N-channel and P-channel.

[0020] The fins outside the gate region are etched back, and a hard mask layer is deposited on top of the etched fins;

[0021] Remove the first sacrificial layer to expose the fins;

[0022] Using a hard mask as a barrier layer, corresponding ions are implanted on both sides and the bottom of the fin outside the gate region to form an active region;

[0023] The gate is fabricated in the gate region;

[0024] An isolation structure is fabricated by etching the active regions on both sides of the fin outside the gate region, thus completing the semiconductor structure fabrication.

[0025] In the semiconductor structure fabrication method provided by the present invention, the material of the first sacrificial layer is any one or more of silicon dioxide, polycrystalline silicon, silicon nitride, and amorphous carbon.

[0026] In the semiconductor structure fabrication method provided by the present invention, the first groove is a sigma groove.

[0027] In the semiconductor structure fabrication method provided by this invention, the process for etching the first groove on the epitaxial silicon layer is as follows:

[0028] An opening is created by isotropic dry etching of the first sacrificial layer;

[0029] Sigma grooves are formed by etching along the (111) crystal plane using anisotropic wet etching.

[0030] In the semiconductor structure fabrication method provided by the present invention, the semiconductor material includes a compressive stress semiconductor material for forming the P-channel fin and a tensile stress semiconductor material for forming the N-channel fin.

[0031] In the semiconductor structure fabrication method provided by the present invention, the compressive stress semiconductor material includes germanium silicon and boron-doped silicon; the tensile stress semiconductor material includes silicon carbide and phosphorus-doped silicon.

[0032] In the semiconductor structure fabrication method provided by the present invention, when etching back the fins outside the gate region, the etching depth is 1 / 6 to 1 / 3 of the thickness of the first sacrificial layer.

[0033] In the semiconductor structure fabrication method provided by the present invention, the thickness of the first sacrificial layer is used to define the fin height, and the thickness of the first sacrificial layer ranges from 30nm to 50nm.

[0034] In the semiconductor structure fabrication method provided by the present invention, the material of the hard mask layer includes oxides, nitrides or metal compounds, and is different from the material type of the first sacrificial layer.

[0035] In the semiconductor structure fabrication method provided by the present invention, fabricating the gate in the gate region includes the following steps:

[0036] Deposited gate oxide layer;

[0037] A second sacrificial layer is deposited that does not cover the gate region;

[0038] Deposited gate material layer;

[0039] Remove the gate material layer outside the gate region to obtain the gate;

[0040] Remove the second sacrificial layer to complete the fabrication of the gate in the gate region.

[0041] In the semiconductor structure fabrication method provided by this invention, the method for removing the gate material layer outside the gate region is as follows:

[0042] Photoresist is applied, and a photoresist pattern that protects the gate region is obtained through exposure and development.

[0043] Using the photoresist pattern as a protection, the gate material layer outside the gate region is removed by an etching process.

[0044] In the semiconductor structure fabrication method provided by this invention, the method for removing the second sacrificial layer is as follows:

[0045] Using the photoresist pattern as a protection, the second sacrificial layer is removed by an etching process.

[0046] Secondly, the present invention provides a semiconductor structure prepared by the above-described fabrication method.

[0047] Thirdly, the present invention provides a method for manufacturing a finned transistor, comprising the following steps:

[0048] Provide semiconductor substrates;

[0049] P-well and N-well regions are formed on the semiconductor substrate, respectively;

[0050] An epitaxial silicon layer and a first sacrificial layer are sequentially fabricated on a semiconductor substrate;

[0051] A first groove is etched on the epitaxial silicon layer, wherein the first groove extends to the P-well region or N-well region of the semiconductor substrate;

[0052] Fins of N-channel and P-channel are formed by epitaxially extending semiconductor materials with high carrier mobility in the first groove.

[0053] The fins outside the gate region are etched back, and a hard mask layer is deposited on top of the etched fins;

[0054] Remove the first sacrificial layer to expose the fins;

[0055] Using a hard mask layer as a barrier layer, corresponding ions are implanted on both sides and the bottom of the fin outside the gate region to form an active region;

[0056] The gate is fabricated in the gate region;

[0057] An isolation structure is fabricated in the active regions on both sides of the fin, excluding the gate region;

[0058] Interlayer medium layer;

[0059] The source, drain, and gate are brought out using a metal interconnect process.

[0060] Fourthly, the present invention provides a finned transistor, which is prepared using a finned transistor fabrication method.

[0061] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0062] This invention changes the stress silicon technique process in the fabrication of fin transistors in existing technologies. It advances the source and drain stress silicon epitaxy to before fin formation, directly etching the fins using a self-aligned technique with a hard mask on the fin. The unexpected technical advantages are: this invention eliminates the need for the complex process of hard mask removal; the source, drain, and gate can be brought out via a via process after the deposition of the intercalation dielectric layer. Furthermore, this invention eliminates the need for the complex epitaxy techniques of high carrier mobility semiconductor materials, simplifying the manufacturing process and reducing control complexity. This invention uses a method of first forming the well region and then epitaxially forming the fin, enabling the fabrication of both stress-free fin transistors with no internal stress silicon in the gate and fin transistors with stress silicon technology extended into the gate. Extending the stress silicon into the gate, i.e., using SiGe or SiC to fabricate the entire fin, increases the channel carrier mobility, resulting in lower energy consumption and enabling the fabrication of high-quality fin transistors.

[0063] In the fabrication process of this invention, a sacrificial layer is fabricated twice. Unexpectedly, the first sacrificial layer not only defines the fin height, reducing the difficulty of height control during fin etching, but also changes the hard mask formation process on the fin, allowing the hard mask to be defined using a simple planarization process. The second sacrificial layer not only protects the fin and reduces the difficulty of gate fabrication, but also almost completely avoids the impact of the gate fabrication process on the fin, simplifying the fabrication process, reducing control difficulty, and lowering manufacturing costs from a technical perspective. Attached Figure Description

[0064] Figure 1 This is a flowchart of a method for fabricating a semiconductor structure according to Embodiment 1 of the present invention.

[0065] Figure 2 This is a schematic diagram of the semiconductor substrate after the well region is prepared in step S120 of Embodiment 1 of the present invention.

[0066] Figure 3 This is a schematic diagram of the epitaxial first sacrificial layer in step S130 of Embodiment 1 of the present invention.

[0067] Figure 4 This is a schematic diagram of the formation of the first photoresist pattern in step S140 of Embodiment 1 of the present invention.

[0068] Figure 5 This is a schematic diagram of etching the first groove in step S140 of Embodiment 1 of the present invention.

[0069] Figure 6 This is a schematic diagram of the formation of the N-channel fin and the P-channel fin in step S150 of Embodiment 1 of the present invention.

[0070] Figure 7 This is a schematic diagram of the top of the fin being re-etched in step S162 of Embodiment 1 of the present invention.

[0071] Figure 8 This is a schematic diagram of filling the groove on the top of the etched fin with hard mask material in step S163 of embodiment 1 of the present invention.

[0072] Figure 9 This is a schematic diagram of the hard mask layer obtained by planarizing the hard mask material in step S164 of Embodiment 1 of the present invention.

[0073] Figure 10 This is a schematic diagram of removing the first sacrificial layer in step S170 of Embodiment 1 of the present invention.

[0074] Figure 11 This is a schematic diagram of the formation of an NMOS active region by injecting group V elements in step S181 of embodiment 1 of the present invention.

[0075] Figure 12 This is a schematic diagram of the formation of a PMOS active region by injecting group III elements in step S182 of embodiment 1 of the present invention.

[0076] Figure 13 This is a schematic diagram of the deposition of the gate oxide layer in step S191 of Embodiment 1 of the present invention.

[0077] Figure 14 This is a schematic diagram of the deposition of a second sacrificial layer that does not cover the gate region in step S192 of Embodiment 1 of the present invention.

[0078] Figure 15 This is a schematic diagram of the deposition of the gate material layer in step S193 of Embodiment 1 of the present invention.

[0079] Figure 16 This is a schematic diagram of removing the gate material layer outside the gate region in step S194 of Embodiment 1 of the present invention.

[0080] Figure 17 This is a schematic diagram of removing the second sacrificial layer in step S195 of Embodiment 1 of the present invention.

[0081] Figure 18 This is a schematic diagram of obtaining the second groove by etching the semiconductor substrate in step S210 of Embodiment 1 of the present invention.

[0082] Figure 19 This is a schematic diagram of the deposition of isolation material in the second groove during step S220 of Embodiment 1 of the present invention.

[0083] Figure 20 This is a top view of the semiconductor structure prepared in Example 1 of the present invention.

[0084] Figure 21 This is a schematic diagram of the finned transistor prepared in Embodiment 2 of the present invention.

[0085] in, Figures 2 to 19 In the diagram, 'a' represents a partial cross-sectional view of the fin of a finned transistor, that is... Figure 20 Sectional view of the BB position; Figures 2 to 19 Image b shows a partial cross-sectional view of a finned transistor along its gate length, specifically the cross-sectional view at position AA. Since the gate length direction is perpendicular to the fin length direction, therefore... Figures 2 to 19 The cross-sectional direction shown in section a is parallel to the cross-sectional direction shown in section b.

[0086] Figure 21 a and Figures 2 to 19 In the diagram, 'a' represents a sectional view at the same location. Figure 21 b and Figures 2 to 19 View b is also a sectional view at the same location.

[0087] 100 - Semiconductor substrate, 110 - P-well region, 120 - N-well region, 130 - Epitaxial silicon layer, 140 - First trench, 150 - Second trench;

[0088] 210 - Photoresist mask, 220 - First photoresist pattern, 230 - Second photoresist pattern, 240 - Third photoresist pattern;

[0089] 310 - First sacrificial layer, 320 - Second sacrificial layer;

[0090] 410-N-channel fin, 411-NMOS active region, 420-P-channel fin, 421-PMOS active region;

[0091] 500 - Hard mask layer, 510 - Hard mask material;

[0092] 600 - Gate, 610 - Gate oxide layer, 620 - Gate material layer;

[0093] 700 - Insulation material;

[0094] 800 - Interlayer dielectric layer, 810 - Through silicon via. Detailed Implementation

[0095] The embodiments of the present invention will be described in further detail below with reference to the accompanying drawings and examples. The following examples are for illustrative purposes only and should not be construed as limiting the scope of the invention.

[0096] In the description of this invention, it should be noted that the terms "center," "longitudinal," "lateral," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the invention. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0097] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "connected" and "linked" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0098] The method for reducing defects after photoresist development provided by this invention is applicable to all known photolithography layers in semiconductor manufacturing, including common ion implantation layer photolithography, isolation layer photolithography, gate layer photolithography, wiring layer photolithography, etc. It is also applicable to all known photolithography processes in semiconductor manufacturing, including common single-photoresist processes and photolithography processes based on anti-reflective coatings. Furthermore, it is applicable to all known types of photoresist in semiconductor manufacturing, including positive and negative photoresists, and is particularly suitable for positive photoresists.

[0099] Example 1: As Figure 1 As shown, this embodiment provides a method for fabricating a semiconductor structure, including the following steps:

[0100] S110, provides a semiconductor substrate;

[0101] S120. A P-well region and an N-well region are formed on a semiconductor substrate, respectively.

[0102] S130. An epitaxial silicon layer and a first sacrificial layer are sequentially fabricated on a semiconductor substrate;

[0103] S140. Etch a first groove on the epitaxial silicon layer, wherein the first groove extends to the P-well region or N-well region of the semiconductor substrate.

[0104] S150. A semiconductor material with high carrier mobility is epitaxially grown inside and outside the first groove to form fins of N-channel and P-channel.

[0105] S160, Etch back the fins outside the gate region, and deposit a hard mask layer on top of the etched fins;

[0106] S170. Remove the first sacrificial layer to expose the fins;

[0107] S180. Using a hard mask layer as a barrier layer, corresponding ions are implanted on both sides and the bottom of the fin outside the gate region to form an active region.

[0108] S190, Fabricate the gate in the gate region;

[0109] S200: An isolation structure is fabricated in the active regions on both sides of the fins outside the gate region to complete the semiconductor structure fabrication.

[0110] This invention changes the stress silicon technology process in the fabrication of fin transistors in existing technologies. It advances the source and drain stress silicon epitaxy to before fin formation, directly etching the fins using a self-aligned technique with a hard mask on the fin. Unexpectedly, this invention eliminates the need for the complex process of hard mask removal; after depositing the interlayer dielectric layer, the source, drain, and gate can be brought out via a via process; and it also eliminates the need for the complex epitaxy techniques of high carrier mobility semiconductor materials, simplifying the manufacturing process and reducing control complexity. This invention uses a method of first forming the well region and then epitaxially forming the fin, enabling it to produce both stress-free fin transistors with no internal stress silicon in the gate, as in existing technologies, and fin transistors with stress silicon technology extended into the gate. Extending the stress silicon into the gate, i.e., using SiGe or SiC to fabricate the entire fin, increases the channel carrier mobility, resulting in lower energy consumption and enabling the fabrication of high-quality fin transistors.

[0111] In the fabrication process of this invention, a sacrificial layer is fabricated twice. Unexpectedly, the first sacrificial layer not only defines the fin height, reducing the difficulty of height control during fin etching, but also changes the hard mask formation process on the fin, allowing the hard mask to be defined using a simple planarization process. The second sacrificial layer not only protects the fin and reduces the difficulty of gate fabrication, but also almost completely avoids the impact of the gate fabrication process on the fin, simplifying the fabrication process, reducing control difficulty, and lowering manufacturing costs from a technical perspective.

[0112] In step S110, the provided semiconductor substrate can be a common semiconductor substrate in the prior art, such as a silicon (Si) substrate, a silicon-germanium (SiGe) substrate, a silicon-germanium-carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates; for example, a silicon substrate is used in this embodiment.

[0113] For example, in step S120, a P-well region 110 and an N-well region 120 are formed on the semiconductor substrate 100 by an ion implantation process, such as... Figure 2 As shown, Figure 2 Image a shows a partial cross-sectional view of the fin of a finned transistor. Figure 2 Figure b shows a partial cross-sectional view of a fin transistor along its gate length. Since the gate length direction is perpendicular to the fin length direction, therefore... Figure 2 The cross-sectional direction shown in section a is parallel to that shown in section b. In all subsequent attached figures, a and b are shown in the same direction, so they will not be explained individually. Figure 2Figure a illustrates approximately two P-well regions 110 for forming NOMS transistors and two N-well regions 120 for forming POMS transistors. During ion implantation, N-well regions 120 are formed by implanting Group V ions, with common Group V elements including phosphorus (P), arsenic (As), and antimony (Sb). P-well regions 110 are formed by implanting Group III ions, with common Group III ions including boron (B) and indium (In). When forming the corresponding type of well region, a photoresist mask 210 needs to be formed using a photoresist process to cover and shield other areas. For example, when forming P-well region 110, the N-well region 120 and the gate region need to be shielded by the photoresist mask 210.

[0114] For example, in step S130, an epitaxial silicon layer 130 and a first sacrificial layer 310 are sequentially formed on the semiconductor substrate 100, such as... Figure 3 As shown, an epitaxial silicon layer 130 was fabricated using techniques such as vapor phase epitaxy (VPE) and molecular beam epitaxy (MBE). Vapor phase epitaxy processes include common epitaxial technologies such as CVD (chemical vapor deposition), APCVD (atmospheric pressure chemical vapor deposition), LPCVD (low pressure chemical vapor deposition), and UHV / CVD (ultra-high vacuum chemical vapor deposition).

[0115] Typically, the semiconductor substrate 100 is a low-resistivity (heavily doped) silicon wafer, primarily to provide mechanical support and prevent latch-up. Low resistance also helps collect and discharge parasitic currents. This invention uses an epitaxial silicon layer 130 to form the substrate for fabricating fins, allowing the growth of high-resistivity (lightly doped) or specifically doped silicon layers on the semiconductor substrate 100. This enables the creation of a working region with excellent surface electrical properties on a low-cost, mechanically sound, low-resistivity substrate, thereby fabricating high-performance devices (such as high-Q inductors and low-loss transmission lines). Furthermore, the epitaxial silicon layer 130 is grown in a highly optimized reaction chamber, achieving a purity far exceeding that of the original substrate. The growth process can cover some minor defects on the substrate surface, providing a near-perfect crystal surface. This provides a high-quality substrate for subsequent formation of sigma grooves and epitaxial fins, avoiding fin defects and improving device yield and reliability.

[0116] For example, a low-pressure chemical vapor deposition (LPCVD) process is used, with silane (SiH4) or dichlorosilane (SiH2Cl2) as the silicon source and high-temperature in-situ cleaning in a hydrogen environment, to epitaxially produce a high-quality (100) crystal plane single-crystal silicon wafer, which provides the basis for the subsequent fabrication of the first groove 140.

[0117] In step S130, the material of the first sacrificial layer 310 is any one or more of silicon dioxide, polycrystalline silicon, silicon nitride, and amorphous carbon, and can be fabricated using a corresponding deposition process; the thickness of the first sacrificial layer 310 is used to define the fin height, therefore, the thickness range of the first sacrificial layer 310 is 30nm~50nm; the structure obtained after epitaxially extending the first sacrificial layer 310 is as follows Figure 3 As shown, for example, the first sacrificial layer 310 of the present invention is silicon dioxide, and the process used includes LPCVD (low-pressure chemical vapor deposition), PECVD (plasma-enhanced chemical vapor deposition), APCVD (atmospheric pressure chemical vapor deposition), and HDP-CVD (high-density plasma chemical vapor deposition). In this embodiment of the present invention, silicon nitride is used as the first sacrificial layer 310, which not only serves as a sacrificial layer to define the height of the fin, but also serves as a mask for etching the first groove 140.

[0118] In step S140, the method for etching the first groove 140 on the epitaxial silicon layer 130 is as follows:

[0119] S141. Photoresist is coated on the first sacrificial layer 310, and the designed opening pattern (i.e., the top opening shape of the sigma groove) is transferred to the photoresist through exposure and development to obtain the first photoresist pattern 220. The window of the first photoresist pattern 220 is the area where the first groove 140 is located. Figure 4 As shown.

[0120] S142. Using the first photoresist pattern 220 as a mask, the first sacrificial layer 310 and the epitaxial silicon layer 130 are sequentially etched through an etching process to form the first groove 140, as shown. Figure 5 As shown.

[0121] It should be noted that when the epitaxial fins to be fabricated subsequently exist only on both sides of the gate region, the first groove 140 does not need to be drilled through in the gate region, see [reference]. Figure 20 As shown, the area below the gate 600 is still formed by the epitaxial silicon layer 130; when the epitaxial fins to be fabricated need to extend into the gate area, the first groove 140 needs to be drilled through along the direction shown by the red dashed box, and the subsequent epitaxial fins completely replace the epitaxial silicon layer 130 as fins.

[0122] In some embodiments, the first groove 140 is a Sigma groove, and the method for etching the Sigma groove is as follows:

[0123] S1421. The first sacrificial layer 310 is opened by dry etching, and the first photoresist pattern 220 is transferred to the lower first sacrificial layer 310. After completion, the first photoresist pattern 220 is removed, and the first sacrificial layer 310 is opened to form a mask layer that can be etched into the epitaxial silicon layer 130.

[0124] For example, CF4 (carbon tetrafluoride) or a mixture of CF4 with O2, H2, etc., is used as the etching gas. CF4 generates fluorine radicals in a plasma environment, and the fluorine radicals react with SiO2 (or silicon nitride) to generate gaseous products (such as SiF4, CO, CO2), thereby etching away the exposed portion of the first sacrificial layer 310.

[0125] S1422. Anisotropic wet etching is used to etch the epitaxial silicon layer 130 and the semiconductor substrate 100 along the (111) crystal plane to form sigma grooves, such as Figure 5 As shown.

[0126] Typically, sigma grooves need to be etched into the semiconductor substrate 100 to improve the channel carrier migration rate.

[0127] For example, TMAH (tetramethylammonium hydroxide) wet etching forms sigma grooves. Utilizing the anisotropy of TMAH, grooves determined by the crystal structure are etched in the exposed silicon region (epitaxy silicon layer 130 and semiconductor substrate 100) to form sigma grooves of a special shape. After subsequent filling with semiconductor material, the special shape of the sigma grooves generates stress, thereby improving the carrier migration rate.

[0128] The etching principle is as follows:

[0129] TMAH etches silicon (100) facets at extremely high speeds and silicon (111) facets at extremely slow speeds (typically more than 100 times slower than the (100) facets). When etching through a window on a (100) facet silicon wafer, rapid longitudinal (depth) etching and lateral etching occur simultaneously, forming a downwardly widening groove. Upon encountering the (111) facet, the etching rate drops sharply. Eventually, the etching stops at a wedge-shaped groove formed by two (111) facets. Because TMAH etching offers high selectivity between the (111) and (100) facets, this process is not only precise and controllable but also effectively avoids the damage and defects caused by traditional dry etching. For a (100) facet silicon wafer, the angle between the (111) facet and the surface is 54.74°, so the sidewall angle of the formed V-groove is 54.74°, which is the typical shape of a sigma groove.

[0130] It should be noted that the etching solution usually uses a TMAH aqueous solution with a concentration of 5% to 25%. The concentration affects the etching rate and surface roughness. High concentration (>20%) of TMAH can obtain a smoother etched surface, but too high a concentration makes it difficult to control the size accurately. Therefore, 20-25% is commonly used to achieve a better balance between the smoothness of the etched surface and the accuracy of size control.

[0131] It should be noted that the higher the temperature, the faster the etching rate, but more precise control is required; the best anisotropic performance is achieved at 80-90℃.

[0132] It should be noted that the etching time is precisely calculated based on the required first groove depth of 140 and the etching rate. The relationship between the depth D and the window width W is as follows: W / 2) 1.414; Etching time must be strictly controlled to achieve the target depth.

[0133] In step S150, semiconductor materials with high carrier mobility are epitaxially grown in the first groove 140 to form fins for the N-channel and P-channel respectively; the semiconductor materials include a compressive stress semiconductor material for forming the P-channel fin 420 and a tensile stress semiconductor material for forming the N-channel fin 410, and the resulting N-channel fin 410 and P-channel fin 420 are as follows: Figure 6 As shown.

[0134] This invention utilizes a high carrier mobility semiconductor material within the first groove 140, thereby not only leveraging the inherent high carrier mobility of the semiconductor material but also further enhancing it through stress silicon technology. When the semiconductor material is a compressive semiconductor, its lattice constant is greater than that of silicon. When confined within the first groove 140, it exerts compressive stress on the surrounding silicon substrate. This stress is transmitted back to the channel itself, significantly improving the performance of the PMOS device.

[0135] When the semiconductor material is a tensile semiconductor material, the lattice constant of the tensile semiconductor material is smaller than that of silicon. When it is confined to grow in the first groove 140, it will stretch the surrounding silicon substrate and generate tensile stress in the channel, which will further significantly improve the performance of the NMOS device.

[0136] In some embodiments, the compressive stress semiconductor material includes silicon germanium (SiGe) or boron-doped silicon; in this embodiment, silicon germanium (SiGe) is preferred. The lattice constant of silicon germanium (SiGe) is 4.2% larger than that of silicon. This difference in lattice constant can generate significant compressive stress in the PMOS channel region, significantly improving hole mobility. However, how to effectively transfer this stress to the device channel has always been a technical challenge.

[0137] In the prior art, U-shaped trenches are commonly used for epitaxial channels. The sidewalls are (110) crystal planes and the bottom is (001) crystal plane. When growing germanium-silicon epitaxially, the nucleation rate of the (110) crystal plane is much higher than that of the (001) crystal plane, resulting in poor surface roughness and easy formation of dislocation defects, which hinders the effective transmission of stress to the device channel.

[0138] This invention utilizes the selectivity of wet etching on different crystal planes of a silicon substrate to form sigma-type trenches containing only (111) and (001) crystal planes. An unexpected effect is that when forming fins as channels in epitaxial silicon germanium (SiGe), this invention significantly reduces epitaxial growth defects by replacing the (110) crystal plane with the (111) crystal plane. Simultaneously, the large undercut sigma-type trench concentrates stress in the undercut sharp corner region, enhancing the stress transfer efficiency of the silicon germanium / silicon heterojunction, thereby significantly improving the carrier mobility performance of P-type transistors.

[0139] In some embodiments, the tensile semiconductor material includes silicon carbide (SiC) or phosphorus-doped silicon. Taking SiC as an example, the lattice constant of SiC is about 20% lower than that of the silicon substrate. After epitaxial silicon carbide is formed inside the first groove 140, a large tensile stress is generated through lattice mismatch. On the other hand, the present invention also utilizes its unique undercut geometry to concentrate and amplify the beneficial lattice stress. The sharp corner regions of the groove can efficiently transfer the substrate tensile stress to the SiC channel within the sigma-type groove. By reducing the effective mass of electrons through bandgap engineering, the electron mobility and performance of NMOS devices are significantly improved.

[0140] In step S150, the process steps for forming N-channel and P-channel fins by epitaxially growing high carrier mobility semiconductor materials within the first groove 140 are as follows:

[0141] When applying compressive stress semiconductor material to a portion of the first groove 140, it is necessary to cover and protect the other portion of the groove with a photoresist mask.

[0142] After the compressive and tensile semiconductor materials are epitaxially grown to fill the corresponding first groove 140, a planarization process (such as CMP) is performed on the surface of the first sacrificial layer 310 to remove excess compressive and tensile semiconductor materials, resulting in the N-channel fin 410 and the P-channel fin 420. Figure 6 As shown.

[0143] In step S160, the method for etching back the fins outside the gate region is as follows:

[0144] S161. A second photoresist pattern 230 is formed using a photoresist process to protect and shield the gate region.

[0145] S162. The fins of the source and drain regions are etched using an etching process to form grooves, such as... Figure 7 As shown. The etch-back depth (groove depth) is the thickness of the subsequently formed hard mask layer 500, and the etch-back depth is generally 1 / 6 to 1 / 3 of the thickness of the first sacrificial layer 310.

[0146] During the etching process, the difference between compressive stress semiconductor materials and tensile stress semiconductor materials is generally large, so they can be etched separately. Of course, a special process can also be used to etch them all at once.

[0147] For example, when the compressive stress semiconductor material and the tensile stress semiconductor material are germanium-silicon and silicon carbide, respectively, strong physical-assisted plasma etching based on fluorine chemistry can be used to achieve synchronous etching by adjusting the process parameters.

[0148] The specific equipment used is an inductively coupled plasma (ICP / ICP-RIE) etching machine, and the etching gas is SF6 + O2. SF6 is an efficient source of fluorine atoms and is the main etching component; adding O2 can promote the removal of polymerization byproducts, prevent the formation of micromasks, and may change the surface chemical state, making the etching rates of the two converge.

[0149] In step S160, the method for filling the hard mask layer 500 after etching back the fin is as follows:

[0150] S163. Remove the second photoresist pattern 230 and deposit hard mask material 510 to fill the etched grooves, such as... Figure 8 As shown; the hard mask material 510 can be any one of silicon dioxide, silicon nitride, titanium nitride, and amorphous carbon. It should be noted that the hard mask material 510 needs to be different from the material of the first sacrificial layer 310. For example, when the first sacrificial layer 310 is silicon nitride, the hard mask material 510 is titanium nitride.

[0151] S164. Excess hard mask material 510 is removed by CMP planarization, remaining on the surface of the first sacrificial layer 310, to obtain the hard mask layer 500, as shown. Figure 9 As shown.

[0152] In step S170, the first sacrificial layer 310 is removed by dry etching or wet etching depending on the material type of the first sacrificial layer 310. See the schematic diagram of the structure after removal. Figure 10 As shown.

[0153] For example, when the first sacrificial layer 310 is made of silicon dioxide, wet etching can be used to remove it with a hydrofluoric acid (HF) solution, typically diluted hydrofluoric acid (DHF, e.g., HF:H2O = 1:10) or a buffered oxide etchant (BOE / BHF, e.g., HF + NH4F). HF reacts chemically with SiO2 to form water-soluble hexafluorosilicic acid (H2SiF6), which is then removed. This method is extremely low-cost, simple to operate, and exhibits very slow etching rates and high selectivity for silicon (Si), silicon nitride, most metals, and photoresists.

[0154] Dry etching can also be selected, such as reactive ion etching (RIE) or ICP-RIE. The process gases usually use fluorinated chemical gases, such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride (SF6), etc. Sometimes argon (Ar) is added to enhance physical bombardment.

[0155] In S180, a hard mask layer 500 is used as a barrier layer. Ions are implanted on both sides and the bottom of the fin outside the gate region to form active regions including a PMOS active region 421 and an NMOS active region 411. The result is as follows: Figure 12 As shown.

[0156] It should be noted that when forming the PMOS active region 421, a photoresist mask 210 needs to be formed using a photoresist process to cover the NMOS active region 411 and the gate region; when forming the NMOS active region 411, a photoresist mask 210 needs to be formed using a photoresist process to cover the PMOS active region 421 and the gate region.

[0157] For example, this embodiment provides an ion implantation method as follows:

[0158] S181. A photoresist mask 210 is formed using a photoresist process to cover the PMOS active region 421 and the gate region. Then, group V elements are implanted using an ion implantation process to form the NMOS active region 411. Figure 11 As shown, Figure 11 The middle arrow is a schematic diagram of ion implantation. By changing the ion implantation angle, the required concentration of group V elements can be implanted into the P-well region 110 below the N-channel fin 410 to form the NMOS active region 411.

[0159] S182. After removing the photoresist mask 210, a photoresist mask 210 is formed again using a photoresist process to cover the NMOS active region 411 and the gate region. Then, group III elements are implanted using an ion implantation process to form the PMOS active region 421. The result after removing the photoresist mask 210 is as follows. Figure 12 As shown, the NMOS active region 411 and the PMOS active region 421 are obtained.

[0160] In step S190, the method for fabricating the gate 600 in the gate region is as follows:

[0161] S191, Prepare gate oxide layer 610; results are as follows Figure 13 As shown, the gate oxide layer 610 covers all N-channel fins 410 and P-channel fins 420.

[0162] The gate oxide layer 610 uses materials including silicon dioxide (SiO2), silicon oxynitride (SiON) and other high-k materials. Other high-k materials mainly include hafnium dioxide (HfO2), hafnium silicate (HfSiO) and nitrogen-doped hafnium-based materials.

[0163] Silicon dioxide can be prepared by thermal oxidation, while silicon oxynitride (SiON) and other high-k materials can be prepared by chemical vapor deposition (CVD) and atomic layer deposition (ALD).

[0164] S192, Deposit a second sacrificial layer 320 that does not cover the gate region, such as Figure 14 As shown;

[0165] The method for depositing the second sacrificial layer 320 that does not cover the gate region is as follows:

[0166] A sacrificial material layer is deposited on the gate oxide layer 610;

[0167] Photoresist is coated and a photoresist mask with the gate region as a window is obtained by exposure and development.

[0168] The sacrificial material layer in the gate region is removed by etching or corrosion processes to obtain a second sacrificial layer 320 that does not cover the gate region. Figure 14 As shown.

[0169] The material type of the second sacrificial layer 320 can be any one or more of silicon dioxide, polycrystalline silicon, silicon nitride, and amorphous carbon. The material type of the second sacrificial layer 320 can be the same as or different from that of the first sacrificial layer 310.

[0170] The material type of the second sacrificial layer 320 is different from that of the gate oxide layer 610. For example, when the gate oxide layer 610 is silicon dioxide, the second sacrificial layer 320 can be made of amorphous carbon.

[0171] S193, Deposit gate material layer 620;

[0172] Using the second sacrificial layer 320 as a mask, a gate material layer 620 is deposited, such as... Figure 15 As shown.

[0173] The gate material layer 620 can be a single-layer material, such as polysilicon, or a multi-layer material, depending on the actual device requirements. Of course, a gate with sidewalls can also be fabricated. If a gate with sidewalls is required, a sidewall material layer needs to be deposited first, and then the bottom sidewall material is removed by selective etching, leaving the sidewalls. Then, polysilicon or other high-k materials are deposited as the gate material layer 620. The sidewall material layer can be silicon dioxide or silicon carbide, etc.

[0174] S194. Remove the gate material layer 620 outside the gate region to obtain the gate 600, as shown. Figure 16 As shown.

[0175] There are various processes for removing the gate material layer 620 outside the gate region. It can be removed by planarization and resting on the surface of the second sacrificial layer 320, or it can be removed by etching. This embodiment provides an etching process for removal, as detailed below:

[0176] S1941. Photoresist is coated on the gate material layer 620, and a third photoresist pattern 240 is obtained by exposure and development. The third photoresist pattern 240 covers the gate region and exposes other regions.

[0177] S1942. Using the third photoresist pattern 240 as a mask, the gate material layer 620 is etched to obtain the gate 600. The result is as follows: Figure 16 As shown.

[0178] The etching process generally chooses dry etching, specifically reactive ion etching (RIE). It uses active free radicals in plasma to carry out chemical reactions, while simultaneously using an electric field to accelerate ions for physical bombardment, thereby achieving anisotropic etching.

[0179] For polysilicon (Poly-Si) gate etching gases, chlorine-based (Cl2) and bromine-based (HBr) chemical gases are selected. An exemplary etching gas is a mixture of HBr / Cl2 / O2 / He (or Ar). In this mixture, HBr provides good anisotropy and high selectivity for SiO2, making it the primary etching gas. Cl2 provides a high polysilicon etching rate but slightly lower selectivity and is typically used in combination with HBr to optimize overall performance. O2 is a key additive; the addition of a small amount of O2 can form a thin protective polymer (SiOxBry) layer on the polysilicon sidewalls, helping to improve selectivity for photoresist and the underlying oxide layer. He / Ar inert gases are used to dilute and stabilize the plasma, and Ar ions also provide physical bombardment-assisted etching.

[0180] S195, Remove the second sacrificial layer 320 to complete the fabrication of the gate 600 in the gate region, as shown. Figure 17 As shown.

[0181] In one embodiment, the third photoresist pattern 240 is used as a mask for further etching. Dry etching can still be used, but the etching gas needs to be switched to a fluorinated chemical gas, such as carbon tetrafluoride (CF4), trifluoromethane (CHF3), sulfur hexafluoride (SF6), etc., to continue etching the second sacrificial layer 320 and remove it. During the removal process, the gate oxide layer 610 in the non-gate region is also removed under the action of the etching gas. Since there is a hard mask layer 500 as a barrier layer, there is no need to worry about the etching damaging the fins. At the same time, it should be noted that the materials of the second sacrificial layer 320 and the hard mask layer 500 cannot be the same.

[0182] In S200, an isolation structure is fabricated in the active regions on both sides of the fin outside the etched gate region. The specific method is as follows:

[0183] S210, using the third photoresist pattern 240 as a mask to block the gate region, and using the hard mask layer 500 as a barrier layer to block the fins, the semiconductor substrate 100 is etched to obtain the second groove 150, as shown. Figure 18 As shown.

[0184] The etching gas can be a combination of bromine / chlorine-based chemical gases (HBr, Cl2) and passivating gases (O2, SF6), which can achieve better etching results.

[0185] In this embodiment, the third photoresist pattern 240 was used as a mask for three etching processes, which greatly saved the number of steps and reduced production costs.

[0186] S220. An isolation material 700 is deposited in the second groove 150. After planarization using CMP technology, it remains on top of the gate 600, forming a trench isolation structure (e.g., a shallow trench isolation structure, STI) between adjacent fins. The isolation material 700 in other areas can serve as an interlayer dielectric layer. The fabrication of the PMOS and NMOS transistors is completed, as shown in the figure. Figure 19 As shown, the top view is shown in Figure 20 (with the isolation material 700 as a transparent material). Figure 19 In the figure, the epitaxial silicon layer 130 below the gate has the same function and properties as the original semiconductor substrate 100. Therefore, the epitaxial silicon layer 130 is also part of the semiconductor substrate 100, and is combined and labeled in the figure.

[0187] The isolation material 700 is generally silicon dioxide and can be fabricated using processes such as high-density plasma chemical vapor deposition (HDP-CVD), flow chemical vapor deposition (FCVD), and subatmospheric pressure chemical vapor deposition (SACVD). Alternatively, a pad oxide layer can be formed by a thermal oxidation process before depositing the isolation material 700 to repair etching damage in the active region.

[0188] Example 2: This example provides a method for fabricating a finned transistor, including the following steps:

[0189] S110, provides a semiconductor substrate;

[0190] S120. A P-well region and an N-well region are formed on a semiconductor substrate, respectively.

[0191] S130. An epitaxial silicon layer and a first sacrificial layer are sequentially fabricated on a semiconductor substrate;

[0192] S140. Etch a first groove on the epitaxial silicon layer, wherein the first groove extends to the P-well region or N-well region of the semiconductor substrate.

[0193] S150. A semiconductor material with high carrier mobility is epitaxially grown inside and outside the first groove to form fins of N-channel and P-channel.

[0194] S160, Etch back the fins outside the gate region, and deposit a hard mask layer on top of the etched fins;

[0195] S170. Remove the first sacrificial layer to expose the fins;

[0196] S180. Using a hard mask layer as a barrier layer, corresponding ions are implanted on both sides and the bottom of the fin outside the gate region to form an active region.

[0197] S190, Fabricate the gate in the gate region;

[0198] S200: An isolation structure is fabricated in the active regions on both sides of the fins outside the gate region to complete the semiconductor structure fabrication.

[0199] S210, an interlayer dielectric layer 800, through which the source, drain, and gate are led out via silicon vias 810 (VIA), resulting in a finned transistor as shown in the figure. Figure 21 As shown.

[0200] The above embodiments are for illustrative purposes only and are not intended to limit the scope of the invention. Although the invention has been described in detail with reference to the embodiments, those skilled in the art should understand that various combinations, modifications, or equivalent substitutions of the technical solutions of the invention do not depart from the spirit and scope of the invention and should be covered within the scope of the claims of the invention.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Includes the following steps: Provide semiconductor substrates; P-well and N-well regions are formed on the semiconductor substrate, respectively; An epitaxial silicon layer and a first sacrificial layer are sequentially fabricated on a semiconductor substrate; A first groove is etched on the epitaxial silicon layer, wherein the first groove extends to the P-well region or N-well region of the semiconductor substrate; High carrier mobility semiconductor material is epitaxially grown inside and outside the first groove to form fins of N-channel and P-channel; The fins outside the gate region are etched back, and a hard mask layer is deposited on top of the etched fins; Remove the first sacrificial layer to expose the fins; Using a hard mask layer as a barrier layer, corresponding ions are implanted on both sides and the bottom of the fin outside the gate region to form an active region; The gate is fabricated in the gate region; An isolation structure is fabricated by etching the active regions on both sides of the fin outside the gate region, thus completing the semiconductor structure fabrication.

2. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The material of the first sacrificial layer is any one or more of silicon dioxide, polycrystalline silicon, silicon nitride, and amorphous carbon; the material of the hard mask layer includes oxides, nitrides, or metal compounds, and is different from the material type of the first sacrificial layer.

3. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The first groove is a sigma groove.

4. The method for fabricating the semiconductor structure according to claim 3, characterized in that, The process used to etch the first groove on the epitaxial silicon layer is as follows: An opening is created by dry etching the first sacrificial layer; Sigma grooves are formed by etching along the (111) crystal plane using anisotropic wet etching.

5. The method for fabricating a semiconductor structure according to claim 1, characterized in that, The semiconductor material includes a compressive semiconductor material for forming the P-channel fin and a tensile semiconductor material for forming the N-channel fin. The compressive stress semiconductor material includes germanium-silicon and boron-doped silicon; the tensile stress semiconductor material includes silicon carbide and phosphorus-doped silicon.

6. The method for fabricating a semiconductor structure according to claim 1, characterized in that, When etching back the fins outside the gate region, the etching depth is 1 / 6 to 1 / 3 of the thickness of the first sacrificial layer; the thickness of the first sacrificial layer is used to define the fin height, and the thickness of the first sacrificial layer ranges from 30nm to 50nm.

7. The method for fabricating a semiconductor structure according to claim 1, characterized in that, Fabricating the gate in the gate region includes the following steps: Deposited gate oxide layer; A second sacrificial layer is deposited that does not cover the gate region; Deposited gate material layer; Remove the gate material layer outside the gate region to obtain the gate; Remove the second sacrificial layer to complete the fabrication of the gate in the gate region.

8. The method for fabricating a semiconductor structure according to claim 7, characterized in that, The method for removing the gate material layer outside the gate region is as follows: Photoresist is applied, and a photoresist pattern that protects the gate region is obtained through exposure and development. Using the photoresist pattern as a protection, the gate material layer outside the gate region is removed by an etching process.

9. The method for fabricating a semiconductor structure according to claim 8, characterized in that, The method for removing the second sacrificial layer is as follows: Using the photoresist pattern as a protection, the second sacrificial layer is removed by an etching process.

10. A semiconductor structure, characterized in that, It is prepared by the manufacturing method described in any one of claims 1-9.

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