A chip debug interface control method and apparatus supporting batch access

Abstract

This invention provides a chip debug interface control method and apparatus supporting batch access. The method includes: a host sending an access command frame to the chip through a serial debug interface; the chip controlling the parsing process of the access command frame using a state machine; when the access mode of the access command frame is batch access mode, and when the sequence mode is non-contiguous address batch access mode, the host sequentially sends multiple address fields, and the chip performs a read / write operation after receiving each address field, and decrements the word count field after each read / write operation; when the sequence mode is contiguous address batch access mode, the host sends a starting address through the address field, the chip automatically generates the next address field based on the initial address, and sequentially performs multiple contiguous address read / write operations based on the value of the word count field, decrementing the value of the word count field after each read / write operation; when the value of the word count field is 0, the batch access ends and the result is returned.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a chip debugging interface control method and apparatus that supports batch access. Background Technology

[0002] In chip design, testing, and system development, controlling and monitoring the internal state of a chip is crucial, and chip debugging is a key technology for verifying chip functionality and yield. Currently, mainstream chip debugging methods include JTAG, SWD, and serial ports. JTAG technology is an international standard testing protocol that uses dedicated test ports and boundary scan chains to access chip pins and internal registers. Adding hardware interconnect logic and using an external debugger can also achieve CPU core debugging. However, JTAG consumes valuable chip pin resources (TMS, TCK, TDI, TDO), and the standard JTAG clock frequency is relatively low, resulting in long test times when transmitting large amounts of debug data. SWD, a debugging technology proposed by ARM, can only debug the CPU core and requires specialized hardware tools and software drivers, unable to utilize the chip's general-purpose interfaces.

[0003] To save on dedicated debug pins, some designs reuse existing general-purpose serial interfaces on the chip for debugging, such as UART, I / O pins, etc. 2 While C and SPI are both supported, general-purpose serial port technology can only access a single address at a time. For example, to read a contiguous block of memory, the host needs to send a "read command + address" and receive "return data," repeating this process continuously. This generates significant command overhead and communication latency. Furthermore, testing costs are directly proportional to testing time. Traditional serial port frame formats increase both testing time and costs. Even with multi-chip interconnect debugging technology (where a host connects to multiple chips simultaneously), maximizing testing efficiency remains difficult.

[0004] Therefore, it is necessary to provide a chip debugging interface control method and device that supports batch access in order to effectively solve the above problems. Summary of the Invention

[0005] This invention addresses the problems and shortcomings of existing technologies by providing a chip debugging interface control method and apparatus that supports batch access. It enables efficient access to the chip address space without relying on whether the chip's internal bus has batch transmission capabilities.

[0006] This invention provides a chip debugging interface control method that supports batch access, the method comprising: Step S101: The host sends an access command frame to the chip through the serial debug interface. The access command frame includes a read / write flag, access mode, sequence mode, word count field, and address field. Step S102: The chip parses the access command frame to obtain the corresponding field information in the access command frame, and uses a state machine to control the parsing process; Step S103: When the access mode of the access command frame is batch access mode, perform batch access operation according to the sequence mode, including: When the sequence mode is a non-contiguous address batch access mode, the host sends multiple address fields in sequence. After receiving each address field, the chip performs a word data read operation or a word data write operation once, and decrements the value of the word count field after each word data read operation or write operation is completed. When the sequence mode is the continuous address batch access mode, the host sends the starting address through the address field, the chip automatically generates the next address field according to the initial address, and performs multiple consecutive address read or write operations in sequence according to the value of the word count field. After each word data read or write operation is completed, the value of the word count field is decremented. Step S104: When the value of the word count field is 0, the batch access ends and the access result is returned through the serial debugging interface.

[0007] Preferably, the read / write flag is determined when the access mode is a batch access mode and the sequence mode is a non-contiguous address batch access mode; When the read / write flag is set to read, the chip receives each address field and reads the word data corresponding to that address. When the read / write flag is set to write, the chip receives each address field and writes a word of data to the corresponding address.

[0008] Preferably, the read / write flag is determined when the access mode is a batch access mode and the sequence mode is a continuous address batch access mode; When the read / write flag is set to read, the chip automatically generates the next address field after reading the starting address, and then reads the data from consecutive addresses sequentially. When the read / write flag indicates a write operation, the chip automatically generates the next address field after reading the starting address, and sequentially writes multiple words of data into a continuous address space.

[0009] Preferably, the method further includes configuring the bit width of the word count field by the word count length to adjust the maximum number of word accesses that the batch access operation can support.

[0010] Preferably, when the sequence mode indicator is a non-contiguous address bulk access mode and the read / write flag indicates a read operation: After sending each address field, the host sends a wait field, the length of which is configured by a wait field length parameter. The chip begins returning the word data corresponding to the address field within the shift clock cycle corresponding to the waiting field. When the host detects that word data corresponding to the address field has started to return, it sends the next address field.

[0011] Preferably, the parsing of the access command frame by the chip is performed by a state machine, which includes a bit counter; The bit counter is loaded with an initial value when the state machine enters the parsing state for each field. The initial value is the bit length corresponding to the current field. The bit counter decreases during each working clock cycle of the serial debug interface. When the value of the bit counter decreases to 0, the state machine jumps from the current field parsing state to the next field parsing state.

[0012] Preferably, before performing batch access operations, the chip performs address space validity checks on the access addresses corresponding to the address fields; When the access address is detected to be outside the accessible address space, the chip does not initiate the corresponding access operation.

[0013] Preferably, the chip returns the execution result of the batch access operation by using the result flag in the access command frame when the batch access operation ends; When the result flag is 1, it indicates that the batch access operation was successful; when the result flag is 0, it indicates that the batch access operation failed. When the chip bulk access operation fails, the error type is recorded in the error information register.

[0014] The present invention also provides a chip debugging interface control device that supports batch access, the device comprising: The serial-to-parallel conversion module is used to parse the access command frames sent by the host through the serial debugging interface to obtain the read / write flags, access mode, sequence mode, word count field, and address field. A state machine is used to parse the access command frame field by field. The state machine includes a bit counter. The bit counter is loaded with an initial value when the state machine enters each field parsing state. The initial value is the bit length corresponding to the current field. The bit counter is decremented in each working clock cycle of the serial debug interface. When the value of the bit counter is decremented to 0, the state machine jumps from the current field parsing state to the next field parsing state. The register unit is used to store the values ​​of the word count field, address field, word data, word count length, and wait field length parameters; The parallel-to-serial conversion module is used to perform read or write operations in batch access mode according to the address field, word count field and access mode, and to return the read word data to the host through the serial debugging interface during the read operation. The transmission control module is used to automatically generate the next address field based on the starting address in the continuous address batch access mode, and to perform read or write operations sequentially based on the multiple address fields sent by the host in the non-contiguous address batch access mode. An error information register is used to record the error type when a chip bulk access operation fails.

[0015] Compared with the prior art, the technical solution of the embodiments of the present invention has the following beneficial effects: This invention provides a chip debug interface control method and apparatus supporting batch access. The method includes: Step S101: The host sends an access command frame to the chip through a serial debug interface. The access command frame includes a read / write flag, an access mode, a sequence mode, a word count field, and an address field; Step S102: The chip parses the access command frame to obtain the corresponding field information in the access command frame, and uses a state machine to control the parsing process; Step S103: When the access mode of the access command frame is a batch access mode, a batch access operation is performed according to the sequence mode, including: when the sequence mode is a non-contiguous address batch access mode, the host sequentially sends... The chip receives each address field and performs a read or write operation on each word of data. After each read or write operation, the value of the word count field is decremented. When the sequence mode is a continuous address batch access mode, the host sends the starting address through the address field. The chip automatically generates the next address field based on the initial address and sequentially performs read or write operations on multiple consecutive addresses based on the value of the word count field. After each read or write operation, the value of the word count field is decremented. Step S104: When the value of the word count field is 0, the batch access ends, and the access result is returned through the serial debug interface. This method sets the access mode, sequence mode, and word count field in the access command frame, and combines the processing mechanisms of continuous address batch access mode and non-contiguous address batch access mode. This allows the host to efficiently complete read and write operations on multiple addresses without repeatedly sending complete command frames during debugging. This batch access mechanism can significantly reduce command overhead and communication round trips, thereby improving chip debugging efficiency and shortening test time.

[0016] Furthermore, the chip debugging interface control device of the present invention achieves accurate parsing of access command frames and efficient execution of batch access through the coordinated work of a serial-to-parallel conversion module, a field-by-field parsing state machine, a register unit, a parallel-to-serial conversion module, and a transmission control module. The device employs a bit counter for field length control and a register unit to store the word count length and waiting field length parameters, enabling stable completion of word data read / write operations in both continuous and non-contiguous address batch access modes, ensuring the reliability and real-time performance of the batch debugging process.

[0017] Furthermore, this invention distinguishes between two batch access modes—contiguous and non-contiguous addresses—and executes word data read or write operations based on read / write flags, making batch access behavior more flexible and adaptable to various debugging scenarios. Combined with measures such as configuring the word count field width, setting the wait field length parameter, a state machine-based field-by-field parsing mechanism, and address space validity detection, the accuracy of access control and the timeliness of data return can be further improved. In the event of access failure, fault traceability is achieved through result flags and error information registers, thereby enhancing the reliability and maintainability of the entire debugging process. Attached Figure Description

[0018] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the accompanying drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention, but not all embodiments. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0019] Figure 1 This is a flowchart illustrating a preferred embodiment of the chip debugging interface control method supporting batch access according to the present invention. Figure 2 This is a schematic diagram of the access command frame format for a single data transmission mode according to a preferred embodiment of the present invention. Figure 3 A schematic diagram of the access command frame format for the non-contiguous address bulk access mode of a preferred embodiment of the present invention; Figure 4 This is a schematic diagram of the access command frame format for the continuous address batch access mode of a preferred embodiment of the present invention; Figure 5 This is a schematic diagram of the structure of the chip debugging interface control with batch access according to a preferred embodiment of the present invention; Figure 6 This is a schematic diagram of the signal timing for a write operation in the non-contiguous address bulk access mode according to a preferred embodiment of the present invention. Figure 7This is a schematic diagram of the signal timing for a read operation in a non-contiguous address bulk access mode according to a preferred embodiment of the present invention. Figure 8 This is a schematic diagram of the signal timing for a write operation in the continuous address bulk access mode according to a preferred embodiment of the present invention. Figure 9 This is a schematic diagram of the signal timing for a read operation in the continuous address batch access mode according to a preferred embodiment of the present invention. Detailed Implementation

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0021] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.

[0022] This invention addresses the problems and shortcomings of existing technologies by providing a chip debugging interface control method and apparatus that supports batch access. It enables efficient access to the chip address space without relying on whether the chip's internal bus has batch transmission capabilities.

[0023] Figure 1 This is a flowchart illustrating a preferred embodiment of a chip debugging interface control method supporting batch access according to the present invention. See now. Figure 1 The present invention provides a chip debugging interface control method supporting batch access, comprising: Step S101: The host sends an access command frame to the chip through the serial debug interface. The access command frame includes a read / write flag, access mode, sequence mode, word count field, and address field.

[0024] In this step, such as Figure 2 , Figure 3 and Figure 4 As shown, the access command frame includes a read / write flag (R / W flag), access mode, sequence mode, word count field, and address or start address field. Among these: The read / write flag (R / W flag) has values ​​of 0 and 1. 0 indicates a read operation, and 1 indicates a write operation.

[0025] The Access Mode value includes 0 and 1. 0 is for single data transfer mode, and 1 is for bulk access mode.

[0026] The sequence mode value includes 0 and 1. 0 is non-sequential bulk access mode, and 1 is sequential bulk access mode.

[0027] The Word Count field is used to identify the total number of words to be executed in batch access mode. Whether it is Sequential or Non-sequential batch access mode, this field is used as the counting basis to control the number of read or write operations.

[0028] The access command frame also includes an end bit to indicate the execution result of the bulk access operation. When the end bit is 1, it indicates that the bulk access operation was successful; when the end bit is 0, it indicates that the bulk access operation failed.

[0029] It should be noted that, Figure 2 and Figure 3 The diagram also illustrates the transmission sequence during bulk access, including a stuff field following the address field, an address field (Address or Start Address), and multiple returned word data, which includes read data and write data.

[0030] Step S102: The chip parses the access command frame to obtain the corresponding field information in the access command frame, and uses a state machine to control the parsing process.

[0031] In this step, the parsing of the access command frame by the chip is performed by a state machine, which includes a bit counter; The bit counter is loaded with an initial value when the state machine enters the parsing state for each field. The initial value is the bit length corresponding to the current field. The bit counter decreases during each working clock cycle of the serial debug interface. When the value of the bit counter decreases to 0, the state machine jumps from the current field parsing state to the next field parsing state.

[0032] Step S103: When the access mode of the access command frame is the batch access mode, perform the batch access operation according to the sequence mode.

[0033] In this step, performing bulk access operations includes: When the sequence mode is non-sequential (non-contiguous address bulk access mode), the access command frame format for non-sequential (non-contiguous address bulk access mode) is as follows: Figure 3 As shown, the host sequentially sends multiple address fields. After receiving each address field, the chip performs a word data read or write operation once, and decrements the value of the word count field after each word data read or write operation is completed.

[0034] Specifically, when the access mode is bulk access mode and the sequence mode is non-sequential address bulk access mode, the read / write flag is determined.

[0035] When the read / write flag indicates a read operation, the chip receives each address field and reads the corresponding word data (read data). Specifically: After sending each address field, the host sends a stuff field, the length of which is configured by a stuff field length parameter. The chip begins to return the word data (read data) corresponding to the address field within the shift clock cycle corresponding to the waiting field. When the host detects that the word data (read data) corresponding to the address field has started to return, it sends the next address field.

[0036] When the read / write flag is set to write, the chip receives each address field and writes a word of data (write data) to the corresponding address.

[0037] When the sequence mode is the sequential address bulk access mode, the access command frame format for the sequential address bulk access mode is as follows: Figure 4 As shown. The host sends the starting address through the address field (Start Address). The chip automatically generates the next address field based on the initial address, and sequentially performs multiple consecutive address read or write operations according to the value of the word count field. After each word data read or write operation is completed, the value of the word count field is decremented.

[0038] Specifically, when the access mode is bulk access mode and the sequence mode is continuous address bulk access mode, the read / write flag (R / W flag) is determined.

[0039] When the read / write flag is set to read, the chip automatically generates the next address field after reading the starting address, and then reads the data from consecutive addresses in sequence.

[0040] When the read / write flag indicates a write operation, the chip automatically generates the next address field after reading the starting address, and sequentially writes multiple words of data (write data) into a continuous address space.

[0041] In this embodiment, the bit width of the word count field is configured by the word count length to adjust the maximum number of word accesses that can be supported by the batch access operation.

[0042] In bulk access mode, the value of the Word Count field is parsed out. The value of the Word Count field is decremented by 1 after each address data transfer is completed, until the value of the Word Count field equals 0, at which point the bulk access operation stops.

[0043] It should be noted that as long as the number of words to be transmitted in this batch access exceeds half of the maximum number of words that the WordCount field can represent, the batch access mechanism of this invention can reduce the number of times access command frames are repeatedly sent, making the overall debugging efficiency significantly higher than the traditional word-by-word access debugging method. Furthermore, it avoids the efficiency loss caused by using a longer "Word Count" when the data volume is small.

[0044] Step S104: When the value of the word count field is 0, the batch access ends and the access result is returned through the serial debugging interface.

[0045] In this step, the chip returns the execution result of the batch access operation by using the result flag in the access command frame when the batch access operation ends; When the result flag is 1, it indicates that the batch access operation was successful; when the result flag is 0, it indicates that the batch access operation failed. When the chip bulk access operation fails, the error type is recorded in the error information register.

[0046] In this embodiment, before performing a batch access operation, the chip performs an address space validity check on the access address corresponding to the address field; when the access address is detected to be outside the accessible address space, the chip does not initiate the corresponding access operation.

[0047] It should be noted that address space validity detection can be achieved through conventional methods in the field, such as address range comparison, address decoder, or mask matching, and this invention does not limit this.

[0048] This invention enables efficient access to the chip's address space without relying on whether the chip's internal bus has batch transmission capabilities.

[0049] With both address and data widths at 32 bits and a stuff bit length of 2 bits, the traditional word-by-word debugging method requires 680 debugging clock cycles to read 10 non-contiguous addresses, while the batch access method of this invention requires only 380 debugging clock cycles, reducing debugging time by approximately 55.88%.

[0050] Under the same conditions, when writing to 10 consecutive addresses, the traditional word-by-word debugging method requires 680 debugging clock cycles, while the batch access method of this invention only requires 362 debugging clock cycles, reducing debugging time by approximately 53.24%. As the scale of batch access further increases, the advantages of the batch access mechanism of this invention in reducing the repeated transmission of command frames will become even more significant.

[0051] Therefore, the chip debugging interface control method proposed in this invention can effectively shorten chip debugging time, improve testing efficiency, and reduce testing costs.

[0052] Figure 2 This is a schematic diagram of the access command frame format for a single data transmission mode according to a preferred embodiment of the present invention. (See now) Figure 2 This invention provides an access command frame format for a single data transmission mode: In this embodiment, a single data transmission mode is also included. In this mode, the format of the access command frame only adds 1 bit compared to the traditional frame format to indicate the transmission mode. Figure 2 The Access Mode field shown.

[0053] In reality, during chip debugging, most scenarios require configuring or reading multiple registers, and many register addresses are contiguous. Furthermore, debugging scenarios involving reading SRAM or FLASH inevitably require batch access operations to contiguous addresses.

[0054] Therefore, this invention improves debugging efficiency in scenarios involving multiple register accesses and sequential memory cell reads by setting a batch access mode.

[0055] Figure 5 This is a schematic diagram of a chip debugging interface control device supporting batch access according to a preferred embodiment of the present invention. Referring now... Figure 5 The chip debugging interface control device 500 supporting batch access provided by the present invention includes a serial-to-parallel conversion module 510 whose output is written to a register unit 530 under the control of a state machine 520, and a transmission control module 550 controlling a parallel-to-serial conversion module 540 to perform batch access based on the contents of the register unit 530. Wherein: The serial-to-parallel conversion module 510 is used to parse the access command frame sent by the host through the serial debugging interface to obtain the read / write flag, access mode, sequence mode, word count field and address field. State machine 520 is used to parse the access command frame field by field. The state machine includes a bit counter. The bit counter is loaded with an initial value when the state machine enters each field parsing state. The initial value is the bit length corresponding to the current field. The bit counter is decremented in each working clock cycle of the serial debug interface. When the value of the bit counter is decremented to 0, the state machine jumps from the current field parsing state to the next field parsing state. Register unit 530 is used to store the values ​​of the word count field, address field, word data, word count length, and wait field length parameters; The parallel-to-serial conversion module 540 is used to perform read or write operations in batch access mode according to the address field, word count field and access mode, and to return the read word data to the host through the serial debugging interface during the read operation. The transmission control module 550 is used to automatically generate the next address field based on the starting address in the continuous address batch access mode, and to perform read or write operations sequentially based on the multiple address fields sent by the host in the non-contiguous address batch access mode. Error information register 560 is used to record the error type when a chip bulk access operation fails.

[0056] Figure 6 This is a signal timing diagram of a write operation in the non-contiguous address bulk access mode according to a preferred embodiment of the present invention. Figure 7 This is a signal timing diagram of a read operation in a non-contiguous address batch access mode according to a preferred embodiment of the present invention. Figure 8 This is a schematic diagram of the signal timing for a write operation in the continuous address bulk access mode according to a preferred embodiment of the present invention. Figure 9 This is a schematic diagram of the signal timing for a read operation in the continuous address batch access mode according to a preferred embodiment of the present invention.

[0057] Now see Figures 6-9In this embodiment, taking the SPI serial interface and AHB bus as internal chips as examples, four schematic diagrams illustrate the typical timing relationship between SPI and AHB signals during batch transmission during chip debugging. It should be noted that the diagrams are only for illustrating the batch access mechanism of this invention and do not limit the specific interface type or bus structure of this invention. Those skilled in the art can also use other serial interfaces such as UART and I2C, combined with different types of on-chip buses, to implement the chip debugging interface control method supporting batch access proposed in this invention.

[0058] In summary, the present invention provides a chip debug interface control method and apparatus supporting batch access. The method includes: Step S101: The host sends an access command frame to the chip through a serial debug interface. The access command frame includes a read / write flag, an access mode, a sequence mode, a word count field, and an address field; Step S102: The chip parses the access command frame to obtain the corresponding field information in the access command frame, and uses a state machine to control the parsing process; Step S103: When the access mode of the access command frame is a batch access mode, a batch access operation is performed according to the sequence mode, including: when the sequence mode is a non-contiguous address batch access mode, the host... Multiple address fields are sent at once. After receiving each address field, the chip performs a read or write operation on a word of data, and decrements the value of the word count field after each read or write operation. When the sequence mode is a continuous address batch access mode, the host sends the starting address through the address field. The chip automatically generates the next address field based on the initial address and sequentially performs read or write operations on multiple consecutive addresses based on the value of the word count field. After each read or write operation on a word of data, the value of the word count field is decremented. Step S104: When the value of the word count field is 0, the batch access ends, and the access result is returned through the serial debug interface. This method, by setting the access mode, sequence mode, and word count field in the access command frame, and combining the processing mechanisms of continuous address batch access mode and non-contiguous address batch access mode, enables the host to efficiently complete read and write operations on multiple addresses without repeatedly sending complete command frames during debugging. This batch access mechanism can significantly reduce command overhead and communication round trips, thereby improving chip debugging efficiency and shortening test time.

[0059] Furthermore, the chip debugging interface control device of the present invention achieves accurate parsing of access command frames and efficient execution of batch access through the coordinated work of a serial-to-parallel conversion module, a field-by-field parsing state machine, a register unit, a parallel-to-serial conversion module, and a transmission control module. The device employs a bit counter for field length control and a register unit to store the word count length and waiting field length parameters, enabling stable completion of word data read / write operations in both continuous and non-contiguous address batch access modes, ensuring the reliability and real-time performance of the batch debugging process.

[0060] Furthermore, this invention distinguishes between two batch access modes—contiguous and non-contiguous addresses—and executes word data read or write operations based on read / write flags, making batch access behavior more flexible and adaptable to various debugging scenarios. Combined with measures such as configuring the word count field width, setting the wait field length parameter, a state machine-based field-by-field parsing mechanism, and address space validity detection, the accuracy of access control and the timeliness of data return can be further improved. In the event of access failure, fault traceability is achieved through result flags and error information registers, thereby enhancing the reliability and maintainability of the entire debugging process.

[0061] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A chip debug interface control method supporting batch access, characterized by, The method includes: Step S101: The host sends an access command frame to the chip through the serial debug interface. The access command frame includes a read / write flag, access mode, sequence mode, word count field, and address field. Step S102: The chip parses the access command frame to obtain the corresponding field information in the access command frame, and uses a state machine to control the parsing process; the parsing of the access command frame by the chip is performed by the state machine, which includes a bit counter; the bit counter is loaded with an initial value when the state machine enters each field parsing state, and the initial value is the bit length corresponding to the current field; the bit counter decrements within each working clock cycle of the serial debug interface, and when the value of the bit counter decrements to 0, the state machine jumps from the current field parsing state to the next field parsing state; Step S103: When the access mode of the access command frame is batch access mode, perform batch access operation according to the sequence mode, including: When the sequence mode is a non-contiguous address batch access mode, the host sends multiple address fields in sequence. After receiving each address field, the chip performs a word data read operation or a word data write operation once, and decrements the value of the word count field after each word data read operation or write operation is completed. When the sequence mode is the continuous address batch access mode, the host sends the starting address through the address field, the chip automatically generates the next address field according to the initial address, and performs multiple consecutive address read or write operations in sequence according to the value of the word count field. After each word data read or write operation is completed, the value of the word count field is decremented. Step S104: When the value of the word count field is 0, the batch access ends and the access result is returned through the serial debugging interface.

2. The method of claim 1, wherein the chip debug interface control method supports batch access. When the access mode is batch access mode and the sequence mode is non-contiguous address batch access mode, determine the read / write flag; When the read / write flag is set to read, the chip receives each address field and reads the word data corresponding to that address. When the read / write flag is set to write, the chip receives each address field and writes a word of data to the corresponding address.

3. The method of claim 1, wherein the chip debug interface control method supports batch access. When the access mode is batch access mode and the sequence mode is continuous address batch access mode, determine the read / write flag; When the read / write flag is set to read, the chip automatically generates the next address field after reading the starting address, and then reads the data from consecutive addresses sequentially. When the read / write flag indicates a write operation, the chip automatically generates the next address field after reading the starting address, and sequentially writes multiple words of data into a continuous address space.

4. The method of claim 1, wherein the chip debug interface control method supports batch access. The method also includes configuring the bit width of the word count field by the word count length, which is used to adjust the maximum number of word accesses that the batch access operation can support.

5. The method of claim 1, wherein the chip debug interface control method supports batch access, and When the sequence mode indicates a non-contiguous address bulk access mode and the read / write flag indicates a read operation: After sending each address field, the host sends a wait field, the length of which is configured by a wait field length parameter. The chip begins returning the word data corresponding to the address field within the shift clock cycle corresponding to the waiting field. When the host detects that word data corresponding to the address field has started to return, it sends the next address field.

6. The method of claim 1, wherein the chip debug interface control method supports batch access, and Before performing batch access operations, the chip performs address space validity checks on the access addresses corresponding to the address fields. When the access address is detected to be outside the accessible address space, the chip does not initiate the corresponding access operation.

7. The method of claim 1, wherein the method further comprises: receiving a request for a batch access; and determining whether the request is valid. 7 The chip returns the execution result of the batch access operation by using the result flag in the access command frame when the batch access operation ends. When the result flag is 1, it indicates that the batch access operation was successful; when the result flag is 0, it indicates that the batch access operation failed. When the chip bulk access operation fails, the error type is recorded in the error information register.

8. A chip debug interface control apparatus for performing the method of any one of claims 1 to 7, supporting bulk access, characterized by The device includes: The serial-to-parallel conversion module is used to parse the access command frames sent by the host through the serial debugging interface to obtain the read / write flags, access mode, sequence mode, word count field, and address field. A state machine is used to parse the access command frame field by field. The state machine includes a bit counter. The bit counter is loaded with an initial value when the state machine enters each field parsing state. The initial value is the bit length corresponding to the current field. The bit counter is decremented in each working clock cycle of the serial debug interface. When the value of the bit counter is decremented to 0, the state machine jumps from the current field parsing state to the next field parsing state. The register unit is used to store the values ​​of the word count field, address field, word data, word count length, and wait field length parameters; The parallel-to-serial conversion module is used to perform read or write operations in batch access mode according to the address field, word count field and access mode, and to return the read word data to the host through the serial debugging interface during the read operation. The transmission control module is used to automatically generate the next address field based on the starting address in the continuous address batch access mode, and to perform read or write operations sequentially based on the multiple address fields sent by the host in the non-contiguous address batch access mode. An error information register is used to record the error type when a chip bulk access operation fails.

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