Data prefetching methods, devices and chips

Abstract

This application discloses a data prefetching method, apparatus, and chip. The method includes: in response to a prefetch request, determining a status register and a first counter corresponding to the prefetch request; in response to a status flag in the status register satisfying a first state, obtaining a judgment result from the target cache regarding whether the prefetch request has hit the target cache; if the judgment result is a cache miss, adjusting the count value of the first counter and sending the prefetch request to the next-level cache corresponding to the target cache. By using the above method, determining whether to send the prefetch request to the target cache for cache miss judgment based on the status flag in the status register, and performing the cache miss judgment based on the first counter, this method can reduce invalid filtering operations of prefetch requests while ensuring that prefetch requests are not duplicated and maintaining prefetch accuracy, thereby reducing power consumption and bandwidth.

Description

Technical Field

[0001] This application relates to the field of processor technology, and in particular to a data prefetching method, apparatus and chip. Background Technology

[0002] In processors, to improve the operating efficiency of the Central Processing Unit (CPU), a hardware prefetch mechanism is typically implemented within the processor's memory subsystem (such as the LSU (load-store unit)). This prefetch mechanism analyzes the data access sequences generated during thread execution to predict the data addresses that may be accessed in the future, and prefetches the relevant data into the processor's multi-level caches (such as L1 cache, L2 cache, etc.), thereby reducing data access latency and improving cache hit rate. The hardware prefetch module generally generates a prefetch request, including the prefetch address and prefetch target, based on historical access information and prefetch algorithms. The prefetch request is then sent to the processor's memory access pipeline for processing, such as address translation (e.g., mapping from virtual address to physical address) and cache coherence checks.

[0003] Currently, to avoid redundant prefetching, some solutions typically introduce a prefetch filtering mechanism, which checks whether the prefetched data already exists in the current cache list by querying cache tag information. If the data already exists, the prefetch request is filtered; otherwise, the prefetch request is forwarded to the downstream memory access subsystem. However, in this process, if the prefetch request is highly accurate, the filtering operation itself may become redundant overhead, leading to unnecessary power consumption. If the filtering operation is omitted, when the prefetch request is not accurate enough, a large number of redundant prefetch requests will be sent to the downstream memory access subsystem, exacerbating memory access bandwidth consumption and system power consumption.

[0004] There is currently no effective solution to the problem of not being able to reduce power consumption efficiency and bandwidth while ensuring prefetch accuracy. Summary of the Invention

[0005] The purpose of this application is to provide a data prefetching method, apparatus, and chip to solve the problem that existing solutions cannot reduce power consumption efficiency and bandwidth while ensuring prefetching accuracy.

[0006] The first aspect of this application provides a data prefetching method applied to a processor, comprising: In response to a prefetch request, the status flag of the status register corresponding to the prefetch request and the count value of the first counter are obtained; In response to the status identifier satisfying the first state, the determination result of whether the prefetch request hits the target cache is obtained. If the determination result is that the target cache is not hit, the count value of the first counter is adjusted, and the prefetch request is sent to the next level cache corresponding to the target cache.

[0007] In some embodiments of this specification, the method further includes: Obtain the first counting condition of the first counter; In response to the first count value satisfying the first counting condition and the status identifier satisfying the first state, the status identifier is adjusted to the second state, and the count value of the first counter is cleared to zero.

[0008] In some embodiments of this specification, the first count value satisfies at least one of the following first counting conditions: The first count value satisfies the first count threshold; The ratio of the first count value to the preset request number threshold satisfies the first ratio threshold. Within a first preset time period, the first count value satisfies the second count threshold; The ratio of the first count value to the number of prefetch requests within the first preset time period satisfies the second ratio threshold.

[0009] In some embodiments of this specification, the method further includes: In response to the status identifier satisfying the second state, the prefetch request is sent to the next level cache corresponding to the target cache.

[0010] In some embodiments of this specification, after sending the prefetch request to the next-level cache corresponding to the target cache in response to the state identifier satisfying the second state, the method further includes: Obtain the check result of the prefetch request, which is obtained by checking whether the prefetch request hits the target cache in the next level cache corresponding to the target cache; In response to the check result satisfying that the prefetch request hits the target cache, the count value of the second counter corresponding to the prefetch request is adjusted.

[0011] In some embodiments of this specification, the method further includes: Determine the second counter corresponding to the prefetch request; In response to the second count value of the second counter satisfying the second counting condition and the status identifier satisfying the second state, the status identifier is adjusted to the first state and the count value of the second counter is cleared to zero.

[0012] In some embodiments of this specification, the second count value satisfies at least one of the following second counting conditions: The second count value satisfies the third count threshold; The ratio of the second count value to the preset request number threshold satisfies the third ratio threshold; Within a second preset time period, the second count value satisfies the fourth count threshold; The ratio of the second count value to the number of prefetch requests within the second preset time period satisfies the fourth ratio threshold.

[0013] In some embodiments of this specification, the target cache includes at least one of the following: The processor's level 1 cache, historical request address cache, and missing status handling register cache.

[0014] In some embodiments of this specification, the processor includes a first counter, a second counter, and a status register, wherein the first counter, the second counter, and the status register are configured to correspond to any one of the following: The processor's hardware prefetch module, the processor's memory address range, the identifier of the prefetch stream corresponding to the prefetch request, the target cache corresponding to the prefetch request, the confidence level of the prefetch stream corresponding to the prefetch request, and the confidence level of the hardware prefetch module.

[0015] In some embodiments of this specification, before obtaining the status flag of the status register corresponding to the prefetch request and the count value of the first counter, the following steps are included: The target object through which the prefetch request passes is determined, and the target object includes at least one of the following: a hardware prefetch module, a target cache; The status register and the first counter set corresponding to the target object are used as the status register and the first counter corresponding to the prefetch request.

[0016] In some embodiments of this specification, after obtaining the determination result of whether the prefetch request hits the target cache corresponding to the target cache, the method further includes: If the determination result indicates that the target cache has been hit, the prefetch request is terminated.

[0017] In some embodiments of this specification, in response to the determination result being a hit of the target cache, the method further includes: Clear the count value of the first counter to zero.

[0018] A second aspect of this specification provides a data prefetching device applied to a processor, comprising: The acquisition module is used to acquire, in response to a prefetch request, the status identifier of the status register corresponding to the prefetch request and the count value of the first counter; The sending module is configured to, in response to the status identifier satisfying the first state, obtain the judgment result of whether the target cache corresponding to the prefetch request hits the target cache; if the judgment result is that the target cache is not hit, adjust the count value of the first counter and send the prefetch request to the next level cache corresponding to the target cache.

[0019] A third aspect of this specification provides a chip including a processing unit and a storage unit for storing instructions executable by the processing unit, wherein the processing unit performs the steps of the method described in the first aspect when executing the instructions.

[0020] A fourth aspect of this specification provides a computer storage medium storing computer program instructions that, when executed by a processor, implement the steps of the method described in the first aspect.

[0021] A fifth aspect of this specification provides a computer program product comprising a computer program that, when executed by a processor, implements the steps of the method described in the first aspect.

[0022] The data prefetching method, apparatus, and chip in the embodiments of this specification can, in response to a prefetching request, determine the status register and the first counter corresponding to the prefetching request; in response to the status flag of the status register satisfying the first state, obtain the judgment result of the target cache regarding whether the prefetching request has hit the target cache; if the judgment result is a miss, adjust the count value of the first counter and send the prefetching request to the next level cache corresponding to the target cache. By using the status register and the first counter, and determining whether to send the prefetching request to the target cache for a prefetching request hit based on the status flag of the status register, and performing the prefetching request hit judgment based on the first counter, it is possible to reduce invalid filtering operations of prefetching requests while ensuring that prefetching requests are not duplicated and maintaining prefetching accuracy, thereby reducing power consumption and bandwidth. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this application. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1The diagram shown is a schematic of a read / write unit provided in an embodiment of this specification. Figure 2 The diagram shown is a schematic representation of a prefetch request process provided in an embodiment of this specification. Figure 3 The diagram shown is a schematic representation of a data prefetching method provided in an embodiment of this specification. Figure 4 The diagram shown is a schematic of a counter and status register determination method provided in an embodiment of this specification; Figure 5 The diagram shown is a schematic representation of a second counter adjustment method provided in an embodiment of this specification. Figure 6 The diagram shown is a schematic representation of a data prefetching method provided in an embodiment of this specification. Figure 7 The diagram shown is a schematic representation of a state switching process provided in an embodiment of this specification. Figure 8 The diagram shown is a schematic of a data prefetching device provided in an embodiment of this specification; Figure 9 The diagram shown is a schematic of a chip provided in an embodiment of this specification. Detailed Implementation

[0025] To enable those skilled in the art to better understand the technical solutions in this application, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this application.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, apparatus, product, or device that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or devices.

[0027] This specification provides the operational steps of the methods described in the embodiments or flowcharts, but based on conventional or non-inventive labor, more or fewer operational steps may be included. The order of steps listed in the embodiments is merely one possible execution order among many and does not represent the only possible execution order. In actual system or device products, the methods shown in the embodiments or drawings can be executed sequentially or in parallel.

[0028] It should be noted that in the embodiments of this specification, certain software, components, models and other existing solutions in the industry may be mentioned. These should be regarded as exemplary and are only intended to illustrate the feasibility of implementing the technical solution of the present invention. However, they do not mean that the applicant has used or necessarily used such solutions.

[0029] Please refer to Figure 1 In the LSU module of the CPU, memory access instructions are handled, and the specific processing procedure is as follows.

[0030] The front end will load, store, and store information such as addresses (i.e.) Figure 1 The load / store operations (LD / st op, payld) are sent to the LSU, which saves the relevant information to the load-store queue (LSQ). The above operations can be arbitrated by an arbitrator before the data access pipeline can begin execution. On the pipeline, the load / store operation can perform virtual address to physical address translation by accessing the TLB (Translation Lookaside Buffer), and confirm whether the L1 cache has been hit by comparing the Tag array in the access tag.

[0031] For the load operation, if the L1 cache is hit, the corresponding data is read from the L1 cache's data cache and returned. If the L1 cache is not hit, a read request needs to be sent to the downstream L2 cache, and the request is stored in the Miss Status Handling Register (MSHR). When the downstream cache returns data to fill the L1 cache, the original load operation is woken up and re-pipelined, returning the corresponding data. For the store operation, if the L1 cache is hit and is in an exclusive state, the corresponding data can be written to the L1 cache's data cache. Otherwise, a read request to obtain a writable state needs to be sent to the downstream L2 cache, and the request is stored in the MSHR. When the downstream cache returns data to fill the L1 cache, the original store operation is woken up and re-pipelined, completing the writing of the corresponding data.

[0032] As can be seen, hitting the cache during the above process can greatly speed up the completion of load / store operations.

[0033] In scenarios where the processor performs data prefetching, a hardware prefetcher (HWPF) module can be set up in the LSU (Least Scale Unit) to move the data needed by the currently executing program flow into the data cache in advance, thereby improving the speed of data access. To achieve this, the hardware prefetch module needs to predict the addresses that may be accessed in the future based on the current address sequence of data access. In specific implementation, the hardware prefetch module can generate a prefetch request based on historical information and algorithms after training. This request includes the prefetch address and the prefetch target. The prefetch request can prefetch data into the L1 cache or the L2 cache. The prefetch request can reuse the LSU memory access pipeline. If the prefetch address is a virtual address, a virtual address to physical address (VA-PA) translation can be performed through the memory pipeline. When processing the prefetch request, the tag array can be compared to confirm whether the prefetch request has hit the tag, that is, whether the current cache line (CL) corresponding to the prefetch request is already in the cache. If a match is not found, the prefetch memory access request is sent to the downstream memory access subsystem. The process of comparing the tag queue to confirm whether a tag has been matched actually uses the tag queue as a prefetch filter to filter out redundant requests.

[0034] by Figure 1 Taking the LSU module as an example, an HWPF (Hardware-Wide Memory Buffer) is added to the LSU module for prefetching data. HWPF can capture load / store information from the pipeline as input, attempt to identify regular memory access address sequences, and perform training. After training, the hardware prefetch module can enter the "prefetch" state and begin generating and sending prefetch requests. Taking the address in the prefetch request as a virtual address and the prefetch target as the L1 cache as an example, the prefetch request is submitted to the memory pipeline after arbitration by the arbitrator, accesses the TLB for address translation, and accesses the L1 cache's tag queue to determine if the prefetch request hits the L1 cache. If it hits, no prefetching is needed, and the prefetch request is filtered. If it misses, a prefetch request needs to be sent to the downstream L2 cache and stored in the MSHR (Memory Management Buffer). The prefetch request is completed when the downstream returns data to fill the L1 cache. In the above prefetch request processing, if prefetch requests with the same address are pipelined, it will result in wasted power consumption and pipeline bandwidth.

[0035] The process of accessing the tag queue described above can be viewed as a prefetch filtering operation to filter redundant prefetch requests. Of course, prefetch requests generated during MSHR allocation or when other levels of caching are created can also be filtered in a similar way. Therefore, for a prefetch request, its processing flow can be as follows... Figure 2 As shown: In some implementations, prefetch filtering consists only of tag queue comparison, while in other implementations it consists of both tag queue and MSHR comparison; in other implementations, prefetch filtering also includes comparison of the historical request address table, and the comparison results can be output through the interface.

[0036] In some embodiments, a data prefetching method is proposed, in which a prefetching filter component is used to filter prefetching requests. This component records the prefetching requests that have been issued. When a new prefetching request is received, the prefetching filter component is checked first. If the prefetching request has already been issued, the same prefetching request will not be issued again, thus saving memory access bandwidth.

[0037] It is evident that existing data prefetching processes all require filtering of prefetch requests. However, if the hardware prefetching module itself is accurate, it will not generate prefetch requests for duplicate addresses, making the filtering of prefetch requests redundant and wasting power. If power and bandwidth are to be saved by completely skipping the comparison of the tag queue, then if the prefetch requests are not accurate enough, the generated prefetch memory access requests will be directly sent to the downstream memory access system, resulting in even greater waste of bandwidth and power.

[0038] To address the aforementioned issue of failing to reduce power consumption and bandwidth while maintaining prefetch accuracy, this embodiment of the specification uses counters (e.g., a first counter and a second counter) and a status register to record the number of consecutive hits on the cache and the number of misses on the cache generated by the hardware prefetch module. The status register is updated using the count values ​​of the two counters, thereby reducing invalid filtering operations on prefetch requests and lowering power consumption and bandwidth while ensuring that prefetch requests are not repeated and maintaining prefetch accuracy.

[0039] The data prefetching method in the embodiments of this specification will be described in detail below with reference to the accompanying drawings.

[0040] This specification provides a data prefetching method through its embodiments. Figure 3A flowchart of a data prefetching method according to one embodiment of this specification is shown. While this specification provides method operation steps or apparatus structures as illustrated in the following embodiments or figures, more or fewer operation steps or module units may be included in the method or apparatus based on conventional or non-inventive effort. In steps or structures where there is no logically necessary causal relationship, the execution order of these steps or the module structure of the apparatus is not limited to the execution order or module structure described in the embodiments and figures of this specification. When the method or module structure is applied in actual devices or terminal products, it can be executed sequentially or in parallel (e.g., in a parallel processor or multi-threaded processing environment, or even a distributed processing environment) according to the method or module structure shown in the embodiments or figures. Figure 3 As shown, the method may include: S301: In response to a prefetch request, obtain the status flag of the status register corresponding to the prefetch request and the count value of the first counter.

[0041] It is understood that prefetch requests can be generated by the processor's hardware prefetch module. A prefetch request may include a prefetch address and a prefetch target (i.e., the target cache). After the hardware prefetch module generates the prefetch request, it can be sent to the prefetch target for data prefetching. A status register can be used to record the status of the prefetch request generated by the hardware prefetch module. This status can characterize the precision of the prefetch request, and the status flag in the status register can be used to determine whether a filtering operation for the prefetch request is required. For example, the status register can include two states: one state indicating that no filtering operation for the prefetch request is required (e.g., represented as 1), and another state indicating that a filtering operation for the prefetch request is required (e.g., represented as 0). The filtering operation can be a determination of whether the prefetch request hits the target cache by passing the target cache that receives the prefetch request. A first counter can be used by the target cache to count the number of missed prefetch requests during the process of determining whether a prefetch request hits the target cache. The increment of the first counter's count value can occur when the status register indicates that a filtering operation for the prefetch request is required. Of course, it is understandable that prefetch requests can also be generated by other modules in the processor, such as requests generated by the L2 cache for prefetching data from other caches. This specification does not limit this, and the following description will use the hardware prefetch module as an example to illustrate the generation of prefetch requests.

[0042] It is understandable that different prefetch requests can correspond to different status registers and first counters. The determination of the status register and first counter corresponding to a prefetch request can be based on the setting rules of the status register and first counter. A prefetch request can include various information, such as the hardware prefetch module that generates the prefetch request, the prefetch stream corresponding to the prefetch request, the address space requested by the prefetch request, the target cache requested by the prefetch request, the confidence level of the hardware prefetch module that generates the prefetch request, and the confidence level of the prefetch stream corresponding to the prefetch request. Therefore, based on the above information included in the prefetch request, the communication connection objects of the status register and the first counter can be set, such as connecting to different hardware prefetch modules, prefetch streams, address spaces, caches, or hardware prefetch modules and prefetch streams with different confidence levels. Furthermore, upon receiving a prefetch request, the status flag of the status register corresponding to the prefetch request and the count value of the first counter can be obtained based on the current setting rules of the processor's status register and first counter.

[0043] S302: In response to the state identifier satisfying the first state, obtain the judgment result of whether the prefetch request hits the target cache corresponding to the prefetch request. If the judgment result is that the target cache is not hit, adjust the count value of the first counter and send the prefetch request to the next level cache corresponding to the target cache.

[0044] It is understandable that the first state is used to characterize the filtering operation required for prefetch requests. When the state identifier satisfies the first state, the result of the target cache's judgment on whether the prefetch request hits the target cache can be obtained. That is, when the state identifier represents the first state, the precision of the currently generated prefetch request is low, or the precision of the current prefetch request cannot be determined temporarily. Therefore, it is necessary to filter the prefetch request through the target cache and determine whether the current prefetch request hits the target cache through the target cache. For example, the target cache can store a tag queue. The target cache can obtain the tag of the data requested by the prefetch request and determine whether the tag hits the tag queue to determine whether the prefetch request hits the target cache.

[0045] It is understandable that an initial value can be set for the first counter. When the count value of the first counter is adjusted for the first time, it can be adjusted based on this initial value. Subsequent adjustments can be made based on the current count value of the first counter. When it is determined that the prefetch request has hit the target cache based on the judgment result, the count value of the first counter can be adjusted based on the judgment result. The adjustment can be, for example, increasing or decreasing the count value. The count value of the counter can be used to characterize the accuracy of the hardware prefetch module, and then it can be used to determine whether the status flag of the status register needs to be adjusted. For example, when it is determined that the prefetch request has hit the target cache, the count value of the first counter can be increased. If the current count value of the first counter is greater than a preset threshold, it indicates that the accuracy of the hardware prefetch module is high, and the status flag of the status register can be adjusted to switch the processing mode of the prefetch request; or when it is determined that the prefetch request has hit the target cache, the count value of the first counter can be decreased. If the current count value of the first counter is less than a preset threshold, it indicates that the accuracy of the hardware prefetch module is high, and the status flag of the status register can be adjusted to switch the processing mode of the prefetch request.

[0046] When it is determined that a prefetch request does not hit the target cache, it indicates that the prefetch request does not need to be filtered. The prefetch request can be sent to the next level cache after the target cache to execute. For example, if the target cache is L1cache, and L1cache determines that the prefetch request did not hit its cache, it can send the prefetch request to its downstream L2cache to execute. Of course, in some embodiments, the prefetch request may also fail to hit the next level cache after the target cache. In such cases, the prefetch request can be sent to the next downstream cache until the prefetch request is executed and the prefetched data is returned.

[0047] In practical implementation, taking L1cache as the target cache as an example, prefetch requests can be issued by the hardware prefetch module, arbitrated by an arbitrator, and then sent to the data storage pipeline. They can also be translated from virtual addresses to physical addresses via the TLB. In this case, it's necessary to check the status register's flag. If the flag is in the first state, the prefetch request can be sent to L1cache for filtering. Specifically, after receiving a prefetch request, L1cache can determine whether the tag of the prefetch request matches the L1cache's tag queue. If not, the prefetch request is sent to L2cache for execution, and the count value of the first counter is adjusted (e.g., incremented by 1).

[0048] In the embodiments of this specification, a status register and a first counter are used. The status of the status register determines whether a prefetch request needs to be sent to the target cache to determine whether the prefetch request hits the target cache. The determination of whether the prefetch request hits the target cache is based on the first counter. This can reduce the invalid filtering operation of prefetch requests while ensuring that the prefetch requests are not duplicated and the prefetch accuracy is maintained. This can reduce power consumption and bandwidth.

[0049] In some embodiments of this specification, the setting rules for the status register and the first counter can be based on specific application requirements. For example, they can be set to correspond to hardware prefetch modules, prefetch streams, address spaces, caches, prefetch streams with different confidence levels, or hardware prefetch modules with different confidence levels. Therefore, when obtaining the status identifier of the status register corresponding to the prefetch request and the count value of the first counter, the status register and the first counter corresponding to the prefetch request can be determined first.

[0050] For details, please refer to Figure 4 As shown, before obtaining the status identifier of the status register corresponding to the prefetch request and the count value of the first counter, the following may be included: S401: Determine the target object through which the prefetch request passes.

[0051] The target object includes at least one of the following: a hardware prefetch module and a target cache.

[0052] S402: The status register and the first counter set corresponding to the target object are used as the status register and the first counter corresponding to the prefetch request.

[0053] It is understood that the status register and the first counter can be configured to correspond to a hardware prefetch module, a prefetch stream, an address space, a cache, a prefetch stream with different confidence levels, or a hardware prefetch module with different confidence levels. Regardless of whether the configuration corresponds to a hardware prefetch module or a hardware prefetch module with different confidence levels, once the hardware prefetch module is determined, the corresponding status register and first counter can be determined based on that module. For configurations corresponding to address space, cache, prefetch stream, or prefetch streams with different confidence levels, different address ranges will have corresponding caches, and different prefetch streams will also have corresponding caches. Therefore, once the target cache is determined, the corresponding status register and first counter can be determined based on that target cache. In the embodiments of this specification, the different configuration rules for the status register and the first counter can improve the flexibility of prefetch request processing and data prefetching.

[0054] It is understandable that only one of the above-mentioned configuration methods can exist in a single read / write unit of the processor. Therefore, after identifying the target object, the status register and first counter corresponding to any object within the target object can be determined as the status register and first counter corresponding to the prefetch request. The correspondence between the target object and the registers and first counter can be achieved through their communication connection. That is, after determining the status register and first counter corresponding to the target object, the status register and first counter communicating with the target object can be determined.

[0055] Furthermore, after determining the status register and the first counter corresponding to the prefetch request, the status identifier of the status register and the count value of the first counter can be obtained.

[0056] Of course, in other embodiments, when designing the processor, the status register and the first counter to be used by the processor when processing the prefetch request can be directly specified. Then, when obtaining the status flag of the status register corresponding to the prefetch request and the count value of the first counter, the data stored in the specified status register and the first counter can be directly obtained.

[0057] In some embodiments of this specification, after obtaining the determination result of whether the prefetch request hits the target cache corresponding to the prefetch request, the method may further include: terminating the prefetch request in response to the determination result indicating a hit with the target cache. It can be understood that if the prefetch request hits the target cache, it indicates that the prefetch request is duplicated, and therefore the prefetch request needs to be filtered, i.e., the prefetch request should be terminated.

[0058] In some embodiments of this specification, in response to the determination result indicating a hit in the target cache, the method may further include: resetting the count value of the first counter to zero. It can be understood that in this embodiment, when it is determined that a prefetch request hits the target cache, it indicates that the precision of the prefetch request generated by the current hardware prefetch module is relatively low. Therefore, the count value of the first counter used to accumulate prefetch precision can be reset to zero upon a hit in the target cache. At this time, the information recorded by the first counter is the number of consecutive misses in the target cache.

[0059] The aforementioned method of resetting the first counter upon determining that a prefetch request has hit the target cache is overly sensitive. This could lead to situations where, despite high prefetch request precision, fluctuations in the count could still cause the first counter to be reset, preventing the status register from switching. Therefore, to avoid this issue, the first counter can be reset when the ratio of hits to the total number of prefetch requests meets a certain threshold, or when the ratio of hits to the total number of prefetch requests within a fixed time interval meets a certain threshold, or when the number of hits within a fixed time interval meets a certain threshold. This improves statistical timeliness and accuracy. The hit count or hit probability can be represented by the count value of the first counter. For example, using the hit probability within a fixed number of prefetch requests as an example, if the hit probability reaches 'a' within a fixed number of n prefetch requests, indicating low prefetch precision, the first counter's count value is reset to zero. Then, based on the first counter's count value x, its ratio to n can be calculated. If this ratio is less than 1-a, the first counter can be reset to zero and counting can restart.

[0060] In some embodiments of this specification, the above data prefetching method may further include: obtaining a first counting condition of the first counter; in response to the first count value satisfying the first counting condition and the state identifier satisfying the first state, adjusting the state identifier to a second state and clearing the count value of the first counter to zero.

[0061] It is understandable that determining whether the first count value meets the first counting condition can be triggered after each adjustment of the first counter's count value, or it can be triggered before determining whether the status flag meets the first state. This manual does not impose any restrictions on this.

[0062] It is understandable that after adjusting the status register to the second state, the first counter can be cleared. At this time, the processing of prefetch requests can be switched to another mode. That is, after obtaining a prefetch request and determining that the status is the second state, the prefetch request can be directly sent to the next level cache of the target cache without having to go through the judgment of the target cache, thus saving power consumption and bandwidth.

[0063] In some embodiments of this specification, the first count value satisfying the first counting condition may include at least one of the following: the first count value satisfies a first counting threshold; the ratio of the first count value to a preset request number threshold satisfies a first proportional threshold; the first count value satisfies a second counting threshold within a first preset time period; the ratio of the first count value to the number of prefetch requests within the first preset time period satisfies a second proportional threshold.

[0064] It is understood that the first counting condition can be any one of the aforementioned first counting threshold, first proportional threshold, second counting threshold, or second proportional threshold. Therefore, when determining whether the first count value satisfies the first counting condition, the corresponding judgment condition can be executed. The first counting condition can also include two or more of the aforementioned first counting threshold, first proportional threshold, second counting threshold, or second proportional threshold. In this case, if any one of the first counting conditions is satisfied, it can be determined that the first count value satisfies the first counting condition. Furthermore, the specific values ​​of the first counting threshold, first proportional threshold, second counting threshold, or second proportional threshold can be set based on the performance, power consumption, etc., of the specific data prefetching implementation.

[0065] In some embodiments of this specification, the above data prefetching method may further include: in response to the state identifier satisfying the second state, sending the prefetch request to the next level cache corresponding to the target cache.

[0066] It is understandable that when a prefetch request is received, the status register can be checked to see if the status flag meets the second state. If it does, it means that the prefetch request generated by the current hardware prefetch module is highly accurate and the possibility of duplicate prefetch requests is low. The filtering operation of the prefetch request can be skipped, and the prefetch request can be sent directly to the next level cache of the target cache for data prefetching. By using the status register, the power consumption caused by the comparison operation of invalid prefetch filtering can be reduced while ensuring that the prefetch request is not duplicated, thus saving memory bandwidth.

[0067] refer to Figure 5 As shown, in some embodiments of this specification, after sending the prefetch request to the next-level cache corresponding to the target cache in response to the state identifier satisfying the second state, the following may also be included: S501: Obtain the check result of the prefetch request, wherein the check result is obtained by checking whether the prefetch request hits the target cache in the next level cache corresponding to the target cache; S502: In response to the check result satisfying that the prefetch request hits the target cache, adjust the count value of the second counter corresponding to the prefetch request.

[0068] It's understandable that when the status is in the second state, there's no need to determine whether the prefetch request hits the target cache. However, the precision of the prefetch request generated by the hardware prefetch module isn't fixed. It's possible that the prefetch request has high precision while processing the current program flow, causing the status to be adjusted to the second state. But when entering the next program flow, the precision of the prefetch request might decrease, meaning the prefetch request might have already hit the target cache. Even when the prefetch request hits the target cache, normally there's no need to send it to the next-level cache or enter its internal execution flow. However, because the status is in the second state, it still enters the next-level cache and needs to be returned to the target cache. Therefore, the power consumption and bandwidth consumed by entering the next-level cache are additional costs. Considering that the next-level cache can store information about the target cache's cache lines, it can assist in verifying whether a prefetch request hits the target cache. Therefore, while the next-level cache executes the prefetch request, it can also check whether the prefetch request hits the target cache. To reduce the cost of prediction errors, a second counter is added to this embodiment. This second counter can be adjusted when the status is in the second state and the next-level cache determines that the prefetch request hits the target cache. When a prefetch request hits the target cache multiple times, the current historical information cannot guarantee that the prefetch request will not hit the target cache again. Therefore, the target cache is still needed to filter prefetch requests: if the prefetch request hits the cache, the prefetch request is canceled; otherwise, the prefetch request continues to be sent to the next-level cache.

[0069] It is understandable that the second counter can be configured similarly to the status register and the first counter, corresponding to a hardware prefetch module, a prefetch stream, an address space, a cache, a prefetch stream with different confidence levels, or a hardware prefetch module with different confidence levels. Furthermore, when configuring the second counter, the configuration rules for the second counter are the same as those for the status register and the first counter. For example, if the status register and the first counter are configured to correspond to a hardware prefetch module, the second counter is also configured to correspond to a hardware prefetch module.

[0070] In some embodiments of this specification, an initial value can be set for the second counter. When the count value of the second counter is initially adjusted, it can be adjusted based on this initial value. Subsequent adjustments can be made based on the current count value of the second counter. When the next-level cache determines that a prefetch request has hit the target cache, the count value of the second counter can be adjusted based on this determination result. The adjustment can be, for example, increasing or decreasing the count value. The count value of this counter can be used to characterize the accuracy of the hardware prefetch module, and then the count value of the first counter can be used to determine whether the status flag of the status register needs to be adjusted. For example, when it is determined that a prefetch request hits the target cache, the count value of the second counter can be increased. If the current count value of the second counter is greater than a preset threshold, it indicates that the accuracy of the hardware prefetch module is low, and the status flag of the status register needs to be adjusted to switch the processing mode of the prefetch request; or when it is determined that a prefetch request hits the target cache, the count value of the second counter can be decreased. If the current count value of the second counter is less than a preset threshold, it indicates that the accuracy of the hardware prefetch module is low, and the status flag of the status register can be adjusted to switch the processing mode of the prefetch request.

[0071] In some embodiments of this specification, the above data prefetching method may further include: determining a second counter corresponding to the prefetching request; in response to the second counter value satisfying a second counting condition and the status identifier satisfying a second state, adjusting the status identifier to a first state and clearing the count value of the second counter to zero.

[0072] It is understandable that the determination of whether the second count value meets the second count condition can be triggered after each adjustment of the second counter value, or it can be triggered before determining whether the status flag meets the second state. This manual does not impose any restrictions on this.

[0073] It is understandable that after adjusting the status register to the first state, the second counter can be cleared. At this time, the processing of prefetch requests can be switched to another mode. That is, after obtaining a prefetch request and determining that the status is the first state, the prefetch request needs to be sent to the target cache for filtering of prefetch requests to ensure that the prefetch requests are not duplicated.

[0074] In some embodiments of this specification, the second count value satisfying the second count condition may include at least one of the following: the second count value satisfies a third count threshold; the ratio of the second count value to a preset request number threshold satisfies a third proportional threshold; the second count value satisfies a fourth count threshold within a second preset time period; the ratio of the second count value to the number of prefetch requests within the second preset time period satisfies a fourth proportional threshold.

[0075] It is understood that the second counting condition can be any one of the aforementioned third counting threshold, third proportional threshold, fourth counting threshold, or fourth proportional threshold. Therefore, when determining whether the second count value satisfies the second counting condition, the corresponding judgment condition can be executed. The second counting condition can also include two or more of the aforementioned third counting threshold, third proportional threshold, fourth counting threshold, or fourth proportional threshold. In this case, if any one of the second counting conditions is met, it can be determined that the second count value satisfies the second counting condition. Furthermore, the specific values ​​of the third counting threshold, third proportional threshold, fourth counting threshold, or fourth proportional threshold can be set based on the performance, power consumption, etc., of the specific data prefetching implementation.

[0076] In some embodiments of this specification, the processor may include a first counter, a second counter, and a status register, wherein the first counter, the second counter, and the status register may be configured to correspond to any one of the following: the processor's hardware prefetch module, the address range of the processor's memory space, the identifier of the prefetch stream corresponding to the prefetch request, the target cache corresponding to the prefetch request, the confidence level of the prefetch stream, and the confidence level of the hardware prefetch module.

[0077] It is understandable that, in practical applications, any one of the above-mentioned setting rules for the first counter, the second counter, and the status register can be chosen to configure the counters and registers. The two counters and the status register can be located either within the processor or outside the processor. Regardless of whether they are located within the processor, in order to implement the functions of the counters and status registers, both counters and the status register need to establish a communication connection with the corresponding configured object. This allows the acquisition or adjustment of count values ​​and status indicators based on their connection relationship during data prefetching.

[0078] It is understandable that the processor's read / write unit can have multiple hardware prefetch modules. When the counter and status register are set to correspond with the hardware prefetch modules, different hardware prefetch modules can communicate with different counters and status registers. In addition, a confidence level can be set for each hardware prefetch module. This confidence level can be used to characterize the confidence level of the prefetch request generated by the corresponding hardware prefetch module. When the counter and status register are set to correspond with the confidence level of the hardware prefetch module, hardware prefetch modules with different confidence levels can communicate with different counters and status registers.

[0079] It is understandable that the hardware prefetch module can generate multiple prefetch streams, each consisting of multiple prefetch requests. Different prefetch streams can correspond to different identifiers. When the counters and status registers are set to correspond with the prefetch streams, different prefetch streams can communicate with different counters and status registers. Furthermore, a confidence level can be set for each prefetch stream, which can be used to characterize the confidence level of the hardware prefetch module in generating the corresponding prefetch stream. When the counters and status registers are set to correspond with the confidence levels of the prefetch streams, prefetch streams with different confidence levels can communicate with different counters and status registers.

[0080] It is understandable that a processor's memory structure can include multiple caches, such as L1 cache, L2 cache, L3 cache, historical request address cache, and missing status register cache. When counters and status registers are configured to correspond to target caches, different caches can communicate with different counters and status registers. The memory space corresponding to multiple caches in a processor can include multiple address spaces, which can be divided into multiple address ranges. When counters and status registers are configured to correspond to address ranges, different address ranges can communicate with different counters and status registers.

[0081] In some embodiments of this specification, the hardware prefetch module may also adjust the prefetch request generation process based on the values ​​of the first counter, the second counter, or the status register, to further improve the accuracy of the generated prefetch requests and reduce the probability of prefetch request duplication.

[0082] In some embodiments of this specification, the target cache may include at least one of the following: The processor's level 1 cache, historical request address cache, and missing status handling register cache.

[0083] The processor's cache levels can be, for example, L1 cache, L2 cache, L3 cache, etc. A subsequent cache level can be a downstream cache of a preceding cache level, and the relationship between them can be inclusive, non-inclusive, or mutually exclusive. For example, L2 cache is a downstream cache of L1 cache, and L2 cache can be an inclusive cache; in this case, all cache lines of L1 cache also exist in L2 cache.

[0084] It is understandable that the prefetch request generated by the hardware prefetch module can be used to prefetch data from any of the aforementioned caches. For example, if the prefetch request is for prefetching data from the Level 1 cache, then the prefetch request can be an L1Pf request; as another example, if the prefetch request is for prefetching data from the Level 2 cache, then the prefetch request can be an L2Pf request.

[0085] This specification also provides a data prefetching method. In this embodiment, the prefetching request generated by the hardware prefetching module for the first-level cache is taken as an example. Two counters are set and their initial states are set as follows: SkipCamHitCacheCnt=0; SkipCamMissCacheCnt=0. A status register is set and its initial state is set as SkipCam=0.

[0086] After the hardware prefetch module is trained, the data prefetching process can begin. (Refer to...) Figure 6 and Figure 7 As shown, where Figure 6 This includes the entire data prefetching process. Figure 7 This includes the state switching of counters and status registers. The process may include the following steps: S1. Initialization: SkipCamHitCacheCnt=0; SkipCamMissCacheCnt=0; SkipCam=0.

[0087] S2, The hardware prefetch module generates prefetch requests that flow into the data storage pipeline.

[0088] S3, SkipCam=0? If yes, proceed to step S4; otherwise, proceed to step S8.

[0089] S4, query the tag queue.

[0090] Specifically, you can query the L1cache tag queue. It's understandable that in the initial state, SkipCam is 0, so prefetch requests will still access the tag queue to check if the cache has been hit; if it has, the prefetch request is filtered out; if it hasn't, it's sent downstream.

[0091] S5. Did the tag match? If yes, proceed to step S6; otherwise, proceed to step S10.

[0092] Specifically, when a cache miss is detected, SkipCamMissCacheCnt is incremented by 1 and a prefetch request is sent downstream; if a cache hit is found, the prefetch request is filtered out.

[0093] S6. Clear SkipCamMissCacheCnt.

[0094] S7 increments SkipCamMissCacheCnt by 1 and sends the prefetch request downstream.

[0095] S8, SkipCamMissCacheCnt=n? If yes, proceed to step S9; otherwise, proceed to step S2.

[0096] Set S9 and SkipCam to 1, and clear SkipCamHitCacheCnt and SkipCamMissCacheCnt to zero.

[0097] When n consecutive cache misses are detected, the SkipCamMissCacheCnt count reaches the threshold n; at this time, SkipCam is set to 1, and subsequent prefetch requests skip the tag queue and directly send prefetch requests downstream.

[0098] S10. Send the prefetch request to the downstream, and the downstream returns the response result.

[0099] S11, The hardware prefetch module receives the response result.

[0100] S12. If the prefetch request hits L1dcache, then SkipCamHitCacheCnt is incremented by 1.

[0101] Specifically, the L2 cache records information about whether the cache line exists in the L1 cache's dcache (i.e., L1dcache). When SkipCam is 1, after a prefetch request is sent to the L2 cache, it can check whether the current request address is in the L1dcache based on the cache line status stored in the L2 cache. The check result is returned to the read / write unit along with the cache line backfill response. When the response indicates that the request address is in the L1dcache, SkipCamHitCacheCnt is incremented by 1.

[0102] S13, SkipCamHitCacheCnt=m? If yes, proceed to step S14; otherwise, proceed to step S2.

[0103] S14 and SkipCam are set to 0, and SkipCamHitCacheCnt and SkipCamMissCacheCnt are cleared to zero.

[0104] Specifically, when m hits are detected in L1dcache, the SkipCamHitCacheCnt count reaches the threshold m, at which point the system returns to its initial state.

[0105] The data prefetching method described in the embodiments of this specification adds two counters, SkipCamHitCacheCnt and SkipCamMissCacheCnt, and one status flag, SkipCam, to the hardware prefetcher. This can reduce the power consumption caused by the comparison operation of invalid prefetch filtering within the LSU while ensuring that the prefetch requests are not duplicated.

[0106] Based on the same inventive concept, this specification also provides a data prefetching device in its embodiments, as described in the following examples. Since the principle by which the data prefetching device solves the problem is similar to that of the data prefetching method, the implementation of the data prefetching system can refer to the implementation of the data prefetching method; repeated details will not be elaborated further. Reference Figure 8 As shown, the data prefetching device may include: The acquisition module 801 is used to acquire, in response to the prefetch request, the status identifier of the status register corresponding to the prefetch request and the count value of the first counter; The sending module 802 is configured to, in response to the status identifier satisfying the first state, obtain the judgment result of whether the target cache corresponding to the prefetch request hits the target cache; if the judgment result is that the target cache is not hit, adjust the count value of the first counter and send the prefetch request to the next level cache corresponding to the target cache.

[0107] In some embodiments of this specification, the above-described apparatus may further include a state switching module, which is configured to: obtain a first counting condition of the first counter; in response to the first count value satisfying the first counting condition and the state identifier satisfying the first state, adjust the state identifier to a second state and clear the count value of the first counter to zero.

[0108] In some embodiments of this specification, the first count value satisfies at least one of the following first counting conditions: The first count value satisfies the first count threshold; The ratio of the first count value to the preset request number threshold satisfies the first ratio threshold. Within a first preset time period, the first count value satisfies the second count threshold; The ratio of the first count value to the number of prefetch requests within the first preset time period satisfies the second ratio threshold.

[0109] In some embodiments of this specification, the sending module 802 may also be used to: in response to the state identifier satisfying the second state, send the prefetch request to the next level cache corresponding to the target cache.

[0110] In some embodiments of this specification, after the sending module sends the prefetch request to the next-level cache corresponding to the target cache in response to the status identifier satisfying the second state, it can also be used to: obtain the check result of the prefetch request, the check result being obtained by the next-level cache corresponding to the target cache checking whether the prefetch request hits the target cache; and adjust the count value of the second counter corresponding to the prefetch request in response to the check result satisfying that the prefetch request hits the target cache.

[0111] In some embodiments of this specification, the state switching module may also be used to: determine the second counter corresponding to the prefetch request; in response to the second count value of the second counter satisfying the second count condition and the state identifier satisfying the second state, adjust the state identifier to the first state and clear the count value of the second counter to zero.

[0112] In some embodiments of this specification, the second count value satisfies at least one of the following second counting conditions: The second count value satisfies the third count threshold; The ratio of the second count value to the preset request number threshold satisfies the third ratio threshold; Within a second preset time period, the second count value satisfies the fourth count threshold; The ratio of the second count value to the number of prefetch requests within the second preset time period satisfies the fourth ratio threshold.

[0113] In some embodiments of this specification, the target cache includes at least one of the following: any level cache of the processor, a history request address cache, and a missing state processing register cache.

[0114] In some embodiments of this specification, the processor includes a first counter, a second counter, and a status register, wherein the first counter, the second counter, and the status register are configured to correspond to any one of the following: the processor's hardware prefetch module, the address range of the processor's memory space, the identifier of the prefetch stream corresponding to the prefetch request, the target cache corresponding to the prefetch request, the confidence level of the prefetch stream, and the confidence level of the hardware prefetch module.

[0115] In some embodiments of this specification, before acquiring the status identifier of the status register corresponding to the prefetch request and the count value of the first counter, the acquisition module 801 may be used to: determine the target object through which the prefetch request passes, the target object including at least one of the following: a hardware prefetch module, a target cache; and use the status register and the first counter set corresponding to the target object as the status register and the first counter corresponding to the prefetch request.

[0116] In some embodiments of this specification, after obtaining the determination result of whether the target cache corresponding to the prefetch request hits the target cache, the sending module 802 can also be used to: terminate the prefetch request in response to the determination result being a hit of the target cache.

[0117] In some embodiments of this specification, after the sending module 802 responds to the determination result that the target cache has been hit, it can also be used to: clear the count value of the first counter to zero.

[0118] This specification also provides an embodiment of a chip, such as... Figure 9 As shown, the chip may include a processor 901 (or processing unit) and a memory 902 (or storage unit), wherein the processor 901 and the memory 902 can be connected via a bus or other means. Figure 9 Taking the example of a connection between China and Israel via a bus.

[0119] Processor 901 can be a central processing unit (CPU). Processor 901 can also be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or combinations of the above types of chips.

[0120] The memory 902, as a non-transitory computer-readable storage medium, can be used to store non-transitory software programs, non-transitory computer-executable programs, and modules, such as the program instructions / modules corresponding to the data prefetching method in the embodiments of the present invention. The processor 901 executes various functional applications and data processing of the processor by running the non-transitory software programs, instructions, and modules stored in the memory 902, thereby implementing the data prefetching method in the above method embodiments.

[0121] The memory 902 may include a program storage area and a data storage area. The program storage area may store the operating system and applications required for at least one function; the data storage area may store data created by the processor 901, etc. Furthermore, the memory 902 may include high-speed random access memory and may also include non-transitory memory, such as at least one disk storage device, flash memory device, or other non-transitory solid-state storage device. In some embodiments, the memory 902 may optionally include memory remotely located relative to the processor 901, and these remote memories may be connected to the processor 901 via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof.

[0122] The one or more modules are stored in the memory 902, and when executed by the processor 901, they perform the following: Figure 3 The data prefetching method shown.

[0123] For details regarding the chip, please refer to the relevant descriptions and effects in the above method embodiments; they will not be repeated here.

[0124] This specification also provides a computer storage medium storing computer program instructions that, when executed, implement the steps of the above-described data prefetching method.

[0125] This specification also provides a computer program product, which includes a computer program that, when executed, implements the steps of the method for determining the fracturing construction parameters described above.

[0126] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), random access memory (RAM), flash memory, hard disk drive (HDD), or solid-state drive (SSD), etc.; the storage medium can also include combinations of the above types of memory.

[0127] The various embodiments in this specification are described in a progressive manner. For the same or similar parts between the various embodiments, please refer to each other. The focus of each embodiment is to describe the differences from other embodiments.

[0128] The systems, devices, modules, or units described in the above embodiments can be implemented by computer chips or entities, or by products with certain functions.

[0129] For ease of description, the above devices are described separately by function as various units. Of course, in implementing this application, the functions of each unit can be implemented in one or more software and / or hardware.

[0130] As can be seen from the above description of the embodiments, those skilled in the art can clearly understand that this application can be implemented by means of software plus necessary general-purpose hardware platforms. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute certain parts of the methods of various embodiments of this application.

[0131] This application can be used in a wide variety of general-purpose or special-purpose computer system environments or configurations. For example: personal computers, server computers, handheld or portable devices, tablet devices, multiprocessor systems, microprocessor-based systems, set-top boxes, programmable consumer chips, network PCs, minicomputers, mainframe computers, distributed computing environments including any of the above systems or devices, etc.

[0132] This application can be described in the general context of computer-executable instructions, such as program modules, that are executed by a computer. Generally, program modules include routines, programs, objects, components, data structures, etc., that perform a specific task or implement a specific abstract data type. This application can also be practiced in distributed computing environments where tasks are performed by remote processing devices connected via a communication network. In distributed computing environments, program modules can reside in local and remote computer storage media, including storage devices.

[0133] The above description is merely a preferred embodiment of this specification and is not intended to limit this specification. Various modifications and variations can be made to the embodiments described herein by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this specification should be included within the scope of protection of this specification.

Claims

1. A data prefetching method, characterized in that, Applied to processors, including: In response to a prefetch request, the status identifier of the status register corresponding to the prefetch request and the count value of the first counter are obtained; In response to the status identifier satisfying the first state, the determination result of whether the prefetch request hits the target cache corresponding to the prefetch request is obtained. If the determination result is that the target cache is not hit, the count value of the first counter is adjusted, and the prefetch request is sent to the next level cache corresponding to the target cache. Obtain the first counting condition of the first counter; In response to the first count value of the first counter satisfying the first count condition and the status identifier satisfying the first state, the status identifier is adjusted to the second state and the count value of the first counter is cleared to zero; Determine the second counter corresponding to the prefetch request; In response to the second count value of the second counter satisfying the second counting condition and the status identifier satisfying the second state, the status identifier is adjusted to the first state and the count value of the second counter is cleared to zero.

2. The data prefetching method according to claim 1, characterized in that, The first count value satisfies at least one of the following first counting conditions: The first count value satisfies the first count threshold; The ratio of the first count value to the preset request number threshold satisfies the first ratio threshold; Within a first preset time period, the first count value satisfies the second count threshold; The ratio of the first count value to the number of prefetch requests within the first preset time period satisfies the second ratio threshold.

3. The data prefetching method according to claim 1, characterized in that, Also includes: In response to the status identifier satisfying the second state, the prefetch request is sent to the next level cache corresponding to the target cache.

4. The data prefetching method according to claim 3, characterized in that, After sending the prefetch request to the next-level cache corresponding to the target cache in response to the status identifier satisfying the second state, the method further includes: Obtain the check result of the prefetch request, which is obtained by checking whether the prefetch request hits the target cache in the next level cache corresponding to the target cache; In response to the check result satisfying that the prefetch request hits the target cache, the count value of the second counter corresponding to the prefetch request is adjusted.

5. The data prefetching method according to claim 1, characterized in that, The second count value satisfies at least one of the following second counting conditions: The second count value satisfies the third count threshold; The ratio of the second count value to the preset request number threshold satisfies the third ratio threshold; Within a second preset time period, the second count value satisfies the fourth count threshold; The ratio of the second count value to the number of prefetch requests within the second preset time period satisfies the fourth ratio threshold.

6. The data prefetching method according to claim 1, characterized in that, The target cache includes at least one of the following: The processor's level 1 cache, historical request address cache, and missing status handling register cache.

7. The data prefetching method according to claim 1, characterized in that, The processor includes a first counter, a second counter, and a status register, wherein the first counter, the second counter, and the status register are configured to correspond to any one of the following: The processor's hardware prefetch module, the processor's memory address range, the identifier of the prefetch stream corresponding to the prefetch request, the target cache corresponding to the prefetch request, the confidence level of the prefetch stream, and the confidence level of the hardware prefetch module.

8. The data prefetching method according to claim 1, characterized in that, Before obtaining the status flag of the status register corresponding to the prefetch request and the count value of the first counter, the process includes: The target object through which the prefetch request passes is determined, and the target object includes at least one of the following: a hardware prefetch module, a target cache; The status register and the first counter set corresponding to the target object are used as the status register and the first counter corresponding to the prefetch request.

9. The data prefetching method according to claim 1, characterized in that, After obtaining the result of determining whether the prefetch request hits the target cache corresponding to the prefetch request, the method further includes: If the determination result indicates that the target cache has been hit, the prefetch request is terminated.

10. The data prefetching method according to claim 9, characterized in that, Following the determination that the target cache has been hit, the method further includes: Clear the count value of the first counter to zero.

11. A data prefetching device, characterized in that, Applied to processors, including: The acquisition module is used to acquire, in response to a prefetch request, the status identifier of the status register corresponding to the prefetch request and the count value of the first counter; The sending module is configured to, in response to the status identifier satisfying the first state, obtain the judgment result of whether the target cache corresponding to the prefetch request hits the target cache; if the judgment result is that the target cache is not hit, adjust the count value of the first counter and send the prefetch request to the next level cache corresponding to the target cache. The state switching module is used for: Obtain the first counting condition of the first counter; In response to the first count value of the first counter satisfying the first count condition and the status identifier satisfying the first state, the status identifier is adjusted to the second state and the count value of the first counter is cleared to zero; Determine the second counter corresponding to the prefetch request; In response to the second count value of the second counter satisfying the second counting condition and the status identifier satisfying the second state, the status identifier is adjusted to the first state and the count value of the second counter is cleared to zero.

12. A chip, characterized in that, It includes a processing unit and a storage unit for storing instructions executable by the processing unit, wherein the processing unit, when executing the instructions, implements the steps of the method according to any one of claims 1 to 10.

13. A computer storage medium, characterized in that, The computer storage medium stores computer program instructions, which, when executed by a processor, implement the steps of the method according to any one of claims 1 to 10.

14. A computer program product, characterized in that, It includes a computer program that, when executed by a processor, implements the steps of the method according to any one of claims 1 to 10.

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