A quantum circuit compiling method and related apparatus

Abstract

The application discloses a quantum circuit compiling method and a related device, and belongs to the technical field of quantum computing. The method comprises the following steps: matching the structure of a quantum circuit to be compiled with the topological structure of a quantum chip, and determining a target layout; the determined target layout at least enables one two-bit logic gate to act on connected physical bits; all routing modes corresponding to the target layout are determined; based on the target score determined by the quantum logic gate on the target path and the distance between the physical bits acted on by the target two-bit logic gate, all obtained routing modes are evaluated, and a target routing mode is determined; and based on the target routing mode and the corresponding target layout, the quantum circuit is compiled. The application embodiment improves the reliability of the compiling result.

Description

Technical Field

[0001] This application belongs to the field of quantum computing technology, specifically a quantum circuit compilation method and related apparatus. Background Technology

[0002] Since the concept of quantum computing was proposed, researchers worldwide have been dedicated to advancing the practical applications of quantum computers, and significant progress has been made in the field in recent years. However, a significant gap remains between quantum circuits and actually executable quantum instructions. This is because quantum circuits are merely logical representations of quantum algorithms and do not take into account the various constraints imposed by quantum chips, such as the basic gate sets supported by the quantum chip and the connectivity between each physical bit. Under current technological conditions, it is difficult to achieve complete direct coupling of all physical bits on a quantum chip. While a two-bit logic gate in a quantum circuit can act on any two logic bits, the physical bits corresponding to the two logic bits may not be coupled. Therefore, applying quantum circuit designs to quantum computers often encounters certain obstacles. To solve these problems, it is necessary to compile the quantum circuits.

[0003] During compilation, multiple layouts are first randomly generated, representing the mapping between logical bits and physical bits. For each layout, different routing methods are determined, and these methods are evaluated. The evaluation results are then used to select the appropriate routing method. Based on the selected routing method, the corresponding layout, and the quantum circuit, the compiled quantum circuit is generated. The routing scheme uses a series of quantum swap gates to exchange the two physical bits acting on a two-bit logic gate into two directly coupled physical bits. In other words, a route can be established between the two physical bits mapped to by a two-bit logic gate through a series of quantum swap gates. The compilation result is significantly affected by the layout. Randomly generated layouts may introduce many quantum swap gates, resulting in a deep quantum circuit, which increases execution time. Excessive execution time introduces decoherence errors, leading to unreliable results and making it difficult to maintain high-quality compilation results. Summary of the Invention

[0004] The purpose of this application is to provide a quantum circuit compilation method and related apparatus, which aims to improve the reliability of the compilation results.

[0005] One embodiment of this application provides a quantum circuit compilation method, the method comprising:

[0006] The structure of the quantum circuit to be compiled is matched with the topology of the quantum chip to determine the target layout. The determined target layout ensures that at least one two-bit logic gate operates on the connected physical bits.

[0007] Determine all routing methods corresponding to the target layout;

[0008] Based on the target score determined by the quantum logic gates on the target path and the distance between the physical bits acting on the target two-bit logic gates, all obtained routing methods are evaluated to determine the target routing method. The target two-bit logic gates are selected from two-bit logic gates that have never acted on connected physical bits using the target layout. The target path is the path after applying the corresponding routing method on the path with the deepest line depth in the quantum circuit.

[0009] The quantum circuit is compiled based on the target routing method and the corresponding target layout.

[0010] Optionally, matching the structure of the quantum circuit to be compiled with the topology of the quantum chip includes:

[0011] By utilizing the topology of a quantum chip and the circuit structure of the quantum circuit to be compiled, which is determined by two-bit logic gates, a target maximum isomorphic subgraph is determined. The circuit structure is the connection graph corresponding to the quantum circuit. The nodes of the connection graph represent logic bits, and the edges represent the two-bit logic gates that act between the two nodes connected by the edges.

[0012] Determine the target layout corresponding to the target maximum isomorphic subgraph.

[0013] Optionally, the maximum isomorphic subgraph is obtained by matching the connection graph with the topology of the quantum chip according to the execution sequence of two-bit logic gates.

[0014] Optionally, determining the target layout corresponding to the target maximum isomorphic subgraph includes:

[0015] Determine the initial layout corresponding to the target maximum isomorphic subgraph, wherein the two logical bits of the two-bit logic gate in the initial layout are mapped to two connected physical bits;

[0016] For the initial layout, when a target logical bit exists, a physical bit not included in the initial layout is selected from the quantum chip as the target physical bit, and a mapping relationship between the target logical bit and the target physical bit is established to obtain the target layout. The target logical bit is a logical bit in the quantum circuit that is not included in the corresponding initial layout.

[0017] Optionally, the evaluation of all obtained routing methods based on the target score determined by quantum logic gates on the target path and the distance between the physical bits of the target two-bit logic gates, to determine the target routing method, includes:

[0018] Using the target score determined by the quantum logic gates on the target path, the distance between the physical bits of the target two-bit logic gate, and the target path depth, all obtained routing methods are evaluated to obtain the evaluation result of each obtained routing method. The target path depth is determined by the path depth corresponding to the first two-bit logic gate, and the target two-bit logic gate includes the first two-bit logic gate.

[0019] The routing method corresponding to the smallest evaluation result is determined as the target routing method.

[0020] Optionally, the target two-bit logic gate further includes a second two-bit logic gate. The first two-bit logic gate is the two-bit logic gate in the quantum circuit that is not applied to the connected physical bits and has the earliest execution time. The second two-bit logic gate is the two-bit logic gate whose execution time is second only to the first two-bit logic gate and has at least one common logic bit with the first two-bit logic gate.

[0021] The target line depth is the difference between the line depth before and after applying the corresponding routing method on the path containing the first two-bit logic gate.

[0022] The target score is obtained by calculating the score corresponding to the target path through pre-set scores for different types of two-bit logic gates and quantum swap gates.

[0023] Optionally, the evaluation result is obtained by summing the distance between the physical bits of the target two-bit logic gate, the target line depth, and the target score.

[0024] Optionally, the evaluation result is obtained using the following formula:

[0025]

[0026] Where H represents the evaluation result, F represents the first two-bit logic gate, |F| represents the number of the first two-bit logic gates, E represents the second two-bit logic gate, |E| represents the number of the second two-bit logic gates, k is a constant between 0 and 1, i and j represent different physical bits, dist(i,j) represents the topological distance between two physical bits, D is the weighting parameter, and Δ depth For the target line depth, r gate The target score is represented by α, which is a constant between 0 and 1.

[0027] Another embodiment of this application provides a quantum circuit compiler, the apparatus comprising:

[0028] The first determining module is used to match the structure of the quantum circuit to be compiled with the topology of the quantum chip to determine the target layout. The determined target layout ensures that at least one two-bit logic gate operates on the connected physical bits.

[0029] The second determination module is used to determine all routing methods corresponding to the target layout;

[0030] The third determining module is used to evaluate all obtained routing methods based on the target score determined by the quantum logic gates on the target path and the distance between the physical bits where the target two-bit logic gates are applied, and to determine the target routing method. The target two-bit logic gates are selected from two-bit logic gates that have never been applied to connected physical bits using the target layout. The target path is the path after applying the corresponding routing method on the path with the deepest line depth in the quantum circuit.

[0031] The compilation module is used to compile the quantum circuit based on the target routing method and the corresponding target layout.

[0032] Another embodiment of this application provides a computer device including a memory and a processor, wherein the memory stores a computer program, and the processor executes the computer program to implement the quantum circuit compilation method described in any of the above embodiments.

[0033] Another embodiment of this application provides a computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit compilation method in any of the above embodiments.

[0034] Compared with existing technologies, this application provides a quantum circuit compilation method. By matching the structure of the quantum circuit to be compiled with the topology of the quantum chip, a target layout is obtained. The layout is jointly determined by the structure and topology of the quantum circuit, which can reduce the large number of quantum switching gates caused by random generation. Furthermore, the target score determined by the quantum logic gates on the target path and the distance between the physical bits of the target two-bit logic gates are two indicators that have a significant impact on the reliability of the compilation result. By evaluating different routing methods, the circuit depth of the compiled quantum circuit can be further reduced, thereby improving the reliability of the compilation result. Attached Figure Description

[0035] Figure 1 A network block diagram of a quantum circuit compilation system provided in this application embodiment;

[0036] Figure 2 A flowchart of a quantum circuit compilation method provided in this application embodiment;

[0037] Figure 3 A schematic diagram of the topology of a quantum chip provided in an embodiment of this application;

[0038] Figure 4 A structural diagram of a quantum circuit compilation device provided in an embodiment of this application;

[0039] Figure 5 This is a schematic diagram of the structure of a computer device provided in an embodiment of this application. Detailed Implementation

[0040] The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain this application, and should not be construed as limiting this application.

[0041] Figure 1 This is a network block diagram of a quantum circuit compilation system provided in an embodiment of this application. The quantum circuit compilation system may include a network 110, a server 120, a wireless device 130, a client 140, storage 150, a classical computing unit 160, a quantum computing unit 170 (including target quantum hardware), and may also include additional memory, a classical processor, a quantum processor, and other devices not shown.

[0042] Network 110 is a medium used to provide communication links between various devices and computers connected together within a quantum circuit compilation system, including but not limited to the Internet, corporate intranets, local area networks, mobile communication networks, and combinations thereof. The connection method can be wired, wireless communication links, or fiber optic cables.

[0043] Server 120, wireless device 130, and client 140 are conventional data processing systems that may contain data and application programs or software tools that perform conventional computational processes. Client 140 may be a personal computer or a network computer, so the data may also be provided by server 120. Wireless device 130 may be a smartphone, tablet, laptop, smart wearable device, etc. Storage unit 150 may include database 151, which can be configured to store data such as qubit parameters, quantum logic gate parameters, quantum circuits, and quantum programs.

[0044] The classical computing unit 160 (quantum computing unit 170) may include a classical processor 161 (quantum processor 171) for processing classical data (quantum data) and a memory 162 (memory 172) for storing classical data (quantum data). The classical data (quantum data) may be a boot file, an operating system image, and an application program 163 (application program 173). The application program 163 (application program 173) may be used to implement a quantum algorithm compiled according to the quantum circuit compilation method provided in the embodiments of this application.

[0045] Any data or information stored or generated in the classical computing unit 160 (quantum computing unit 170) can also be configured to be stored or generated in another classical (quantum) processing system in a similar manner, and any application executed therein can also be configured to be executed in another classical (quantum) processing system in a similar manner.

[0046] It should be noted that a true quantum computing platform has a hybrid structure, which includes at least... Figure 1 The system consists of two main parts: the classical computing unit 160, which is responsible for performing classical calculations and control; and the quantum computing unit 170, which is responsible for running quantum programs to achieve quantum computing.

[0047] The aforementioned classical computing unit 160 and quantum computing unit 170 can be integrated into a single device or distributed across two different devices. For example, a first device including the classical computing unit 160 runs a classical computer operating system, providing quantum application development tools and services, as well as the storage and network services required for quantum applications. Users develop quantum programs using the quantum application development tools and services on the second device, and send these quantum programs to a second device including the quantum computing unit 170 via the network services. The second device runs a quantum computer operating system, which parses and compiles the quantum program's code into instructions that the quantum processor 170 can recognize and execute. The quantum processor 170 then implements the quantum algorithm corresponding to the quantum program based on these instructions.

[0048] The computing units of the classic processor 161 within the classic computing unit 160 are based on CMOS transistors on a silicon chip. These computing units are not limited by time or coherence; that is, they are available at any time without time constraints. Furthermore, the number of such computing units in a silicon chip is sufficient; currently, a single classic processor 161 contains tens of thousands of computing units. Given this sufficient number and the fixed selectable computing logic of the CMOS transistors (e.g., AND logic), computational performance is achieved by combining a large number of CMOS transistors with a limited set of logic functions during operation.

[0049] In the quantum computing unit 170, the basic computing unit of the quantum processor 171 is the qubit. The input of a qubit is limited by coherence and coherence time; that is, a qubit is limited by its available usage time and is not always readily available. Making full use of qubits within their available usage time is a key challenge in quantum computing. Furthermore, the number of qubits in a quantum computer is one of the representative indicators of its performance. Each qubit performs computational functions through on-demand configured logical functions. Given the limited number of qubits and the diverse logical functions available in quantum computing, such as Hadamard gates (H gates), Pauli-X gates (X gates), Pauli-Y gates (Y gates), Pauli-Z gates (Z gates), X gates, RY gates, RZ gates, CNOT gates, CR gates, iSWAP gates, Tofoli gates, etc., quantum computing requires combining a limited number of qubits with diverse logical function combinations to achieve computational effects.

[0050] Based on these differences, the design of classical logic functions applied to CMOS transistors and the design of quantum logic functions applied to qubits are significantly and fundamentally different. The design of classical logic functions applied to CMOS transistors does not need to consider the individuality of CMOS transistors. For example, the representation of a CMOS transistor in a silicon chip is its individual identifier, location, and usable time of each CMOS transistor. Therefore, classical algorithms composed of classical logic functions only express the operational relationship of the algorithm, not the algorithm's dependence on individual CMOS transistors.

[0051] Quantum logic functions applied to qubits need to consider the individuality of each qubit, such as its position within the quantum chip, its relationship with surrounding qubits, and the duration of its usable time. Therefore, quantum algorithms composed of quantum logic functions not only express the computational relationships within the algorithm but also its dependence on the individual qubits.

[0052] A quantum chip can include qubits and channels for controlling the qubits. Quantum logic gates are implemented using analog signals. Different combinations of analog signals are applied to physical bits through the channels controlling the physical bits, thereby realizing quantum circuits with different functions to process data. Therefore, the design of quantum logic functions in the qubits (including the design of whether qubits are used and the design of the efficiency of each qubit) is key to improving the computing performance of quantum computers and requires special design. This is the unique feature of quantum algorithms based on quantum logic functions, and it is fundamentally and significantly different from classical algorithms based on classical logic functions. The aforementioned design of qubits is a technical problem that ordinary computing devices do not need to consider or face. It should be noted that the qubits in the quantum chip mentioned here are the physical bits mentioned in the embodiments of this application.

[0053] See Figure 2 , Figure 2 A quantum circuit compilation method provided in this application includes the following steps:

[0054] S201: Match the structure of the quantum circuit to be compiled with the topology of the quantum chip to determine the target layout. The determined target layout ensures that at least one two-bit logic gate operates on the connected physical bits.

[0055] Quantum circuit compilation only considers two-qubit logic gates. If the original quantum circuit contains quantum logic gates operating on more than two qubits, these gates need to be split to obtain equivalent combinations of single-qubit and two-qubit logic gates, thus yielding the quantum circuit to be compiled. Two-qubit logic gates refer to quantum logic gates operating on two qubits, such as CNOT gates and controlled RZ gates. The topology of a quantum chip is determined by its hardware structure. The topology is defined by the connection or coupling relationships of the physical qubits within the quantum chip. Nodes in the topology represent physical qubits, and edges represent connections between two physical qubits.

[0056] In this embodiment, the target layout is determined based on the matching result between the structure of the quantum circuit and the topology of the quantum chip, ensuring that at least two physical bits are connected in the mapped physical bits. It is not randomly generated, which reduces the number of quantum swap gates after compilation. There are many ways to match the structure of the quantum circuit with the topology of the quantum chip. Different matching methods may yield different matching results and different target layouts. One matching method is to use the topology of the quantum chip and the circuit structure of the quantum circuit to be compiled, determined by two-bit logic gates, to determine the target maximum isomorphic subgraph. Here, the circuit structure is the connection graph corresponding to the quantum circuit, where nodes represent logic bits, and edges represent the two-bit logic gates acting between the two nodes connected by the edge; the target layout corresponding to the target maximum isomorphic subgraph is then determined.

[0057] The Maximum Common Subgraph (MCS) is the subgraph that is most common to two input graphs (called a graph pair), and this subgraph must be connected and isomorphic. Isomorphism means that there is a relationship between two graphs such that the vertex set and edge set of one graph can be mapped to the vertex set and edge set of the other graph in a corresponding way, while maintaining the original edge and vertex relationships.

[0058] The search for the maximum isomorphic subgraph utilizes algorithms such as Ullmann, VF2, CBWJ, or GADDI. Once the maximum isomorphic subgraph is found, the target layout can be determined based on it. The maximum isomorphic subgraph can be the global maximum isomorphic subgraph of the quantum circuit to be compiled, or it can be determined according to the execution timing. Specifically, it is obtained by matching the circuit structure with the topology of the quantum chip according to the execution timing of two-bit logic gates. That is, first, the subgraph corresponding to the earliest execution timing is determined. Then, the topology is searched for a structure identical to that subgraph. If one is found, the structure corresponding to the next execution timing is added to the current subgraph, and the search continues until no identical structure is found in the topology. The result of the previous search is then taken as the maximum isomorphic subgraph. The subgraph corresponding to the execution timing is determined by the circuit structure. Determining the maximum isomorphic subgraph according to the execution timing ensures that the beginning of the circuit satisfies the chip's topology, avoiding swap operations caused by random layout.

[0059] When there are multiple determined maximum isomorphic subgraphs, one can be randomly selected from the determined maximum isomorphic subgraphs as the target maximum isomorphic subgraph. The sum of the fidelity between the physical bits corresponding to each maximum isomorphic subgraph can be calculated, and the maximum isomorphic subgraph with the highest fidelity can be selected as the target maximum isomorphic subgraph. It should be noted that the fidelity mentioned here is the fidelity of a two-bit logic gate.

[0060] The target maximally isomorphic subgraph may not cover all logical bits of the quantum circuit. In this case, it is necessary to determine the target layout based on the maximally isomorphic subgraph. The determination can be done in the following ways:

[0061] Determine the initial layout corresponding to the target maximum isomorphic subgraph, wherein the two logical bits of the two-bit logic gate in the initial layout are mapped to two connected physical bits;

[0062] For the initial layout, when a target logical bit exists, a physical bit not included in the initial layout is selected from the quantum chip as the target physical bit, and a mapping relationship between the target logical bit and the target physical bit is established to obtain the target layout. The target logical bit is a logical bit in the quantum circuit that is not included in the corresponding initial layout.

[0063] The initial layout mapping is not random, but rather based on the connection relationships between logical bits and physical bits. The logical bit connections are determined by two-bit logic gates, while the physical bit connections are determined by the inherent properties of the quantum chip. Logical bits with connections in the initial layout are mapped to physical bits that also have connections.

[0064] When the initial layout does not include all logical bits, physical bits need to be allocated to the missing logical bits to establish a mapping relationship. When there are multiple target logical bits, a physical bit not included in the initial layout is selected from the quantum chip as the target physical bit, and a mapping relationship is established between the target logical bit and the target physical bit. Then, an unselected target logical bit is selected from the target logical bits, and another unselected physical bit not included in the initial layout is selected from the quantum chip as the target physical bit, and a mapping relationship is established between the target logical bit and the target physical bit. This process is repeated until all target logical bits are selected.

[0065] It should be noted that in the target layout, there are no cases where multiple logical bits map to the same physical bit, nor are there cases where multiple physical bits map to the same logical bit. The target physical bit can be selected randomly, based on topological distance, or based on fidelity. When selecting based on topological distance, first determine the logical bits connected to the target logical bit. Based on the physical bits mapped to these determined logical bits, select the unmapped physical bit with the smallest topological distance to the determined physical bit as the target physical bit. The same principle can be used to select based on fidelity.

[0066] S202: Determine all routing methods corresponding to the target layout.

[0067] Generally, in a target layout, logical bits with connections are mapped to physical bits that are not connected. To implement the functionality of a two-bit logic gate, routing is required across the two physical bits. There are many ways to route from one physical bit to another. For example, using... Figure 3 Taking the quantum chip topology shown as an example, a CNOT gate, after mapping, needs to act on Q2 and Q7. The corresponding routing methods are:

[0068] CNOT(2,7)→SWAP(4,7)+SWAP(2,5)+CNOT(4,5)

[0069] CNOT(2,7)→SWAP(4,7)+SWAP(4,1)+CNOT(2,1)

[0070] CNOT(2,7)→SWAP(8,7)+SWAP(2,5)+CNOT(5,8)

[0071]

[0072] In this embodiment of the application, it is necessary to generate all routing methods corresponding to the target layout. Specifically, all possible routing methods can be obtained by using a routing algorithm based on quantum lines, topology and target layout.

[0073] S203: Based on the target score determined by the quantum logic gates on the target path and the distance between the physical bits acting on the target two-bit logic gates, evaluate all obtained routing methods and determine the target routing method. The target two-bit logic gates are selected from two-bit logic gates that have never acted on connected physical bits using the target layout. The target path is the path after applying the corresponding routing method on the path with the deepest line depth in the quantum circuit.

[0074] The deepest path in a quantum circuit can be determined by constructing a directed graph with two-bit logic gates as nodes and logic bits as edges, and then searching for the deepest path within that graph. The target path is defined by inserting a quantum swapping gate at the corresponding position on that path. The number and position of the inserted quantum swapping gates are determined by the corresponding routing method.

[0075] The target score reflects the merits of different target paths because it is obtained by applying different routing methods on the path with the deepest route. Applying different routing methods may lead to varying degrees of increase in path depth. The greater the depth of the quantum path, the more problems it will bring:

[0076] Increased Risk of Quantum Decoherence: Quantum decoherence refers to the process by which a quantum system interacts with its environment, leading to a loss of coherence in its quantum states. In quantum circuits, as the circuit depth increases, the time for physical bits to interact with their environment lengthens. For example, physical bits may be affected by environmental factors such as surrounding electromagnetic fields and temperature fluctuations. Just as information is easily masked by noise in a noisy environment, in quantum computers, this interference can cause the quantum state of a physical bit to transition from special quantum states such as superposition or entanglement to classical states, leading to computational errors. For very deep quantum circuits, the cumulative effect of this decoherence is more significant, thereby reducing the accuracy of quantum computing.

[0077] Gate operation error accumulation: Quantum circuits are composed of a series of quantum logic gate operations. In actual operation, each quantum logic gate operation may have a certain degree of error. These errors may come from the imprecision of the hardware, such as the limited precision of the control pulses for qubits. As the depth of the quantum circuit increases, the number of quantum logic gate operations increases, and the errors accumulate. For example, assuming the error of each quantum logic gate operation is 1%, the total error may be relatively small for a quantum circuit with only 10 quantum logic gates; however, if the circuit depth reaches 1000 quantum gates, the accumulated errors will have a huge impact on the calculation results, causing the final calculation result to deviate from the expected result.

[0078] Significant resource consumption: From a time perspective, deep quantum circuits require more time for quantum logic gate operations. Since each quantum logic gate operation takes time to complete, increased circuit depth means the entire computation process takes longer. From a spatial perspective, it may require more physical bits to store intermediate results and perform complex calculations. For example, when executing quantum algorithms, to achieve complex function calculations or data processing, increasing circuit depth may require additional physical bits to maintain computational continuity, placing higher demands on the hardware resources of quantum computers (such as the number of physical bits).

[0079] In summary, the lower the target score, the shallower the route depth. This application uses the target score to weigh the route depth.

[0080] The distance between the physical bits of the target two-bit logic gate relates to the physical bits in quantum computing and the impact of the two-bit logic gate on them. This distance can be a topological distance, which affects the following properties:

[0081] (1) Quantum state transmission fidelity

[0082] Quantum state transmission is a crucial step in quantum information processing. When the topological distance between physical bits is large, the quantum state is more susceptible to environmental interference during transmission. For example, in a quantum computer based on superconducting qubits, when a quantum state is transmitted from one physical bit to another physical bit at a greater distance, the long transmission path may lead to interactions with more environmental factors, such as interference from external electromagnetic fields and micro-vibrations. These interferences can reduce the fidelity of the quantum state, meaning the similarity between the transmitted quantum state and the original quantum state decreases. This is analogous to transmitting a signal in a noisy communication channel; the greater the distance, the greater the noise interference and the lower the accuracy of the signal. In this embodiment, the topological distance between two physical bits is used to measure the distance between them. The topological distance can be the shortest distance between two physical bits in the topological structure.

[0083] (2) Quantum logic gate operation delay

[0084] Quantum logic gate operations are fundamental to quantum computing, and many involve multiple physical qubits. When the topological distance between these physical qubits is large, joint operations (such as two-qubit gate operations) become more difficult. This is because, physically, signals need to propagate over greater distances to control these qubits. For example, in an ion-trap quantum computer, to entangle two distant ions (physical qubits), the control pulses need to travel even further to reach the corresponding ions, increasing the latency of the quantum logic gate operations. This latency affects the speed and efficiency of quantum computing, especially in complex quantum algorithms that require a large number of fast quantum gate operations, where the cumulative effect of the latency is more pronounced.

[0085] (3) The generation and maintenance of quantum entanglement are difficult.

[0086] Quantum entanglement is a key resource for quantum computing and quantum communication. The large topological distance between physical bits makes generating quantum entanglement more difficult because the interaction between distant physical bits is relatively weak during the entanglement generation process. Moreover, even if an entangled state is successfully generated, maintaining it is much more challenging. For example, in quantum networks, when nodes (each node can be considered as a unit containing physical bits) are far apart, the quantum entangled state may decay rapidly due to environmental factors over long distances and imperfect entanglement management mechanisms.

[0087] Considering both the target score and the distance between physical bits, two key factors, an evaluation index system is used to assess each routing method. For example, a weighted evaluation function can be set, where the target score and the distance between physical bits each have a certain weight. The weights can be determined based on the actual situation. This application aims to find a routing method that minimizes the depth of the compiled quantum circuit and / or the number of quantum switching gates. However, compiling quantum circuits using different routing methods and comparing the compiled quantum circuits to determine the routing method in reverse is wasteful of resources, and since the quantum circuit has already been compiled, there is no need to determine the routing method. This approach is not practical. Therefore, different indexes are needed to measure the merits of the routing methods. This application uses the target score and the distance between physical bits for measurement. As mentioned above, these two indexes affect the depth of the circuit and the final execution result of the circuit, and can effectively measure the merits of the routing methods.

[0088] In this embodiment of the application, the specific evaluation method can be as follows: using the target score determined by the quantum logic gates on the target path, the distance between the physical bits of the target two-bit logic gate, and the target path depth, all obtained routing methods are evaluated to obtain the evaluation result of each obtained routing method, wherein the target path depth is determined by the path depth corresponding to the first two-bit logic gate, and the target two-bit logic gate includes the first two-bit logic gate; the routing method corresponding to the smallest evaluation result is determined as the target routing method.

[0089] The routing method corresponding to the minimum evaluation result is the optimal routing method under the comprehensive evaluation method of this application. Selecting the routing method with the minimum evaluation result can effectively reduce the depth of the line, reduce the number of SWAP gates, and improve the quality of line compilation.

[0090] In some embodiments of this application, the target two-bit logic gate further includes a second two-bit logic gate. The first two-bit logic gate is the two-bit logic gate in the quantum circuit that is not applied to the connected physical bits and has the earliest execution time. The second two-bit logic gate is the two-bit logic gate whose execution time is second only to the first two-bit logic gate and has at least one identical logic bit with the first two-bit logic gate.

[0091] The target line depth is the difference between the line depth before and after applying the corresponding routing method on the path containing the first two-bit logic gate.

[0092] The target score is obtained by calculating the score corresponding to the target path through pre-set scores for different types of two-bit logic gates and quantum swap gates.

[0093] In some embodiments of this application, the evaluation result is obtained by summing the distance between the physical bits of the target two-bit logic gate, the target line depth, and the target score.

[0094] In some embodiments of this application, the evaluation result is obtained using the following formula:

[0095]

[0096] Where H represents the evaluation result, F represents the first two-bit logic gate, |F| represents the number of the first two-bit logic gates, E represents the second two-bit logic gate, |E| represents the number of the second two-bit logic gates, k is a constant between 0 and 1, i and j represent different physical bits, dist(i,j) represents the topological distance between two physical bits, D is the weighting parameter, and Δ depth For the target line depth, r gate The target score is represented by α, which is a constant between 0 and 1.

[0097] S204: Compile the quantum circuit based on the target routing method and the corresponding target layout.

[0098] This application provides a quantum circuit compilation method. By matching the structure of the quantum circuit to be compiled with the topology of a quantum chip, a target layout is obtained. The layout is jointly determined by the structure and topology of the quantum circuit. This can reduce the large number of quantum switching gates caused by random generation. Furthermore, the target score determined by the quantum logic gates on the target path and the distance between the physical bits acting on the target two-bit logic gates are two indicators that have a significant impact on the reliability of the compilation result. By evaluating different routing methods, the circuit depth of the compiled quantum circuit can be further reduced, thereby improving the reliability of the compilation result.

[0099] See Figure 4 , Figure 4 A quantum circuit compilation apparatus provided in this application embodiment may include:

[0100] The first determining module 401 is used to match the structure of the quantum circuit to be compiled with the topology of the quantum chip to determine the target layout, wherein the determined target layout at least makes a two-bit logic gate operate on the connected physical bits.

[0101] The second determining module 402 is used to determine all routing methods corresponding to the target layout;

[0102] The third determining module 403 is used to evaluate all obtained routing methods based on the target score determined by the quantum logic gates on the target path and the distance between the physical bits where the target two-bit logic gates are applied, and to determine the target routing method. The target two-bit logic gates are selected from two-bit logic gates that have never been applied to connected physical bits using the target layout. The target path is the path after applying the corresponding routing method on the path with the deepest line depth in the quantum circuit.

[0103] Compilation module 404 is used to compile the quantum circuit based on the target routing method and the corresponding target layout.

[0104] The specific functions and effects of the aforementioned quantum circuit compilation device can be explained by referring to other embodiments of this application, and will not be repeated here. Each module in the quantum circuit compilation device can be implemented entirely or partially through software, hardware, or a combination thereof. Each module can be embedded in or independent of the processor in a computer device in hardware form, or stored in the memory of a computer device in software form, so that the processor can call and execute the operations corresponding to each module.

[0105] Please see Figure 5 This application also provides a computer device, including a memory and a processor. The memory stores a computer program, and the processor executes the computer program to implement the quantum circuit compilation method in any of the above embodiments. Please refer to [link to relevant documentation]. Figure 5 The computer device can be a classical computer or a quantum computer.

[0106] This application also provides a computer-readable storage medium storing a computer program thereon, which, when executed by a computer, causes the computer to perform the quantum circuit compilation method in any of the above embodiments.

[0107] This application also provides a computer program product containing instructions that, when executed by a computer, cause the computer to perform the quantum circuit compilation method in any of the above embodiments.

[0108] It is understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not limit the implementation process of the embodiments of this application in any way.

[0109] It is understood that the various implementation methods described in this application can be implemented individually or in combination, and the implementation methods in this application are not limited in this respect.

[0110] Unless otherwise stated, all technical and scientific terms used in the embodiments of this application have the same meaning as commonly understood by one of ordinary skill in the art. The terminology used in this application is for the purpose of describing particular embodiments only and is not intended to limit the scope of this application. The term "and / or" as used in this application includes any and all combinations of one or more of the associated listed items. The singular forms "a," "the," and "the" as used in the embodiments of this application and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0111] It is understood that the processor in the embodiments of this application can be an integrated circuit chip with signal processing capabilities. During implementation, each step of the above method embodiments can be completed by the integrated logic circuits in the processor's hardware or by instructions in software form. The processor can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. It can implement or execute the methods, steps, and logic block diagrams disclosed in the embodiments of this application. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the methods disclosed in the embodiments of this application can be directly embodied in the execution of a hardware decoding processor, or executed by a combination of hardware and software modules in the decoding processor. The software modules can be located in random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. This storage medium is located in memory; the processor reads information from the memory and, in conjunction with its hardware, completes the steps of the above method.

[0112] It is understood that the memory in the embodiments of this application may be volatile memory or non-volatile memory, or may include both volatile and non-volatile memory. Specifically, non-volatile memory may be read-only memory (ROM), programmable read-only memory (PROM), erasable programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), or flash memory. Volatile memory may be random access memory (RAM). It should be noted that the memory in the systems and methods described herein is intended to include, but is not limited to, these and any other suitable types of memory.

[0113] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0114] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the aforementioned method implementations, and will not be repeated here.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0116] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment, depending on actual needs.

[0117] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0118] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0119] The above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this application should be included within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A quantum circuit compilation method, characterized by, The method includes: The structure of the quantum circuit to be compiled is matched with the topology of the quantum chip to determine the target layout. The determined target layout ensures that at least one two-bit logic gate operates on the connected physical bits. Determine all routing methods corresponding to the target layout; Using the target score determined by the quantum logic gates on the target path, the distance between the physical bits acting on the target two-bit logic gates, and the target line depth, all obtained routing methods are evaluated to obtain the evaluation result of each obtained routing method. The routing method corresponding to the smallest evaluation result is determined as the target routing method. The target two-bit logic gates are selected from the two-bit logic gates that have never acted on the connected physical bits using the target layout. The target two-bit logic gates include a first two-bit logic gate, which is the two-bit logic gate with the earliest execution time among the target two-bit logic gates. The target path is the path after applying the corresponding routing method on the path with the deepest line depth in the quantum line. The target line depth is determined by the line depth corresponding to the first two-bit logic gate. The quantum circuit is compiled based on the target routing method and the corresponding target layout.

2. The method of claim 1, wherein, The process of matching the structure of the quantum circuit to be compiled with the topology of the quantum chip includes: By utilizing the topology of a quantum chip and the circuit structure of the quantum circuit to be compiled, which is determined by two-bit logic gates, a target maximum isomorphic subgraph is determined. The circuit structure is the connection graph corresponding to the quantum circuit. The nodes of the connection graph represent logic bits, and the edges represent the two-bit logic gates that act between the two nodes connected by the edges. Determine the target layout corresponding to the target maximum isomorphic subgraph.

3. The method of claim 2, wherein, The maximum isomorphic subgraph is obtained by matching the circuit structure with the topology of the quantum chip according to the execution sequence of two-bit logic gates.

4. The method of claim 2, wherein, Determining the target layout corresponding to the target maximum isomorphic subgraph includes: Determine the initial layout corresponding to the target maximum isomorphic subgraph, wherein the two logical bits of the two-bit logic gate in the initial layout are mapped to two connected physical bits; For the initial layout, when a target logical bit exists, a physical bit not included in the initial layout is selected from the quantum chip as the target physical bit, and a mapping relationship between the target logical bit and the target physical bit is established to obtain the target layout. The target logical bit is a logical bit in the quantum circuit that is not included in the corresponding initial layout.

5. The method according to any one of claims 1-4, characterized in that, The target two-bit logic gate further includes a second two-bit logic gate, which is a two-bit logic gate whose execution timing is second only to the first two-bit logic gate and has at least one logic bit in common with the first two-bit logic gate. The target line depth is the difference between the line depth before and after applying the corresponding routing method on the path containing the first two-bit logic gate. The target score is obtained by calculating the score corresponding to the target path through pre-set scores for different types of two-bit logic gates and quantum swap gates.

6. The method as described in claim 5, characterized in that, The evaluation result is obtained by summing the physical bit distance between the target two-bit logic gates, the target line depth, and the target score.

7. The method as described in claim 6, characterized in that, The evaluation result was obtained using the following formula: in, Indicates the evaluation results. This represents the first two-bit logic gate. This indicates the number of logic gates in the first two bits. For the second two-bit logic gate, Indicates the number of the second two-bit logic gates. A constant between 0 and 1 Each represents a different physical bit. This represents the topological distance between two physical bits. For weight parameters, For the target line depth, Indicates the target score. It is a constant between 0 and 1.

8. A quantum circuit compilation device, characterized in that, The device includes: The first determining module is used to match the structure of the quantum circuit to be compiled with the topology of the quantum chip to determine the target layout. The determined target layout ensures that at least one two-bit logic gate operates on the connected physical bits. The second determination module is used to determine all routing methods corresponding to the target layout; The third determining module is used to evaluate all obtained routing methods using the target score determined by the quantum logic gates on the target path, the distance between the physical bits acting on the target two-bit logic gates, and the target line depth, to obtain the evaluation result of each obtained routing method, and to determine the routing method corresponding to the smallest evaluation result as the target routing method. The target two-bit logic gates are selected from the two-bit logic gates that have never acted on the connected physical bits using the target layout, and the target two-bit logic gates include a first two-bit logic gate, which is the two-bit logic gate with the earliest execution time among the target two-bit logic gates. The target path is the path after applying the corresponding routing method on the path with the deepest line depth in the quantum line, and the target line depth is determined by the line depth corresponding to the first two-bit logic gate. The compilation module is used to compile the quantum circuit based on the target routing method and the corresponding target layout.

9. A computer device comprising a memory and a processor, the memory storing a computer program, the processor executing the computer program to implement the quantum circuit compilation method of any one of claims 1-7.

10. A computer-readable storage medium having a computer program stored thereon, which, when executed by a computer, causes the computer to perform the quantum circuit compilation method of any one of claims 1-7.

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