A sampling test method, device and medium of a flash memory chip

Abstract

The application discloses a sampling test method, equipment and medium for a flash memory chip, and the method comprises the following steps: determining the maximum error bit number of a unit code length and the maximum error code rate of a page; dividing a block into a plurality of same regions; for each region of all blocks, sorting the error bit number of the unit code length from large to small, selecting the first proportion of the error bit number of the unit code length and recording the page set; for the same region of all blocks, selecting the page with the number of occurrences exceeding the first threshold; merging all regions to obtain a block test page address combination; performing an erase-read-write operation on the block test page address combination of all blocks of the flash memory chip to obtain the maximum error bit number of the unit code length and the maximum error code rate of the page; and if the absolute values of the differences before and after are within a preset threshold, testing the flash memory chips of the same specification batch by using the block test page address combination. The application can effectively reduce the test time and cost while ensuring the reliability of the test result.

Description

Technical Field

[0001] This invention belongs to the field of flash memory testing technology, specifically relating to a sampling test method, equipment, and medium for flash memory chips. Background Technology

[0002] With the rise of AI intelligent applications and big data center cloud applications, the demand for data storage has increased significantly. Commercial, industrial, automotive, pharmaceutical, food, aerospace, and military fields have migrated data from the past magnetic recording to flash-based solid-state storage. This means that the security and stability of data storage will largely depend on the performance of flash memory chips. Therefore, conducting reliability testing on flash memory chips has great practical significance.

[0003] Testing is the primary means of ensuring that flash memory chips meet application requirements. Flash memory testing mainly focuses on basic functional verification and performance evaluation. With technological advancements, testing techniques have evolved from simple read / write tests to comprehensive evaluations of flash memory lifespan, reliability, durability, and data retention capabilities. In the 21st century, NAND flash memory became mainstream due to its high density and low cost, and the emergence of 3D NAND technology further propelled flash memory towards higher capacities and performance. Simultaneously, flash memory testing technology continues to upgrade to cope with increasingly complex storage structures and application scenarios.

[0004] To ensure reliable test results for flash memory chips, all memory blocks must be tested. NAND flash data is organized from smallest to largest as follows: Cell, Page, Block, Plane, Die, and Chip. A page is the basic unit for read / write operations, and a block is the smallest unit for erase operations. With the development of 3D NAND stacking technology, the capacity of a single flash memory chip is increasing. If full address testing is required, the testing time and cost will inevitably increase significantly. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a sampling test method, equipment, and medium for flash memory chips, solving the problems of long testing time and high testing cost caused by full address testing of flash memory chips.

[0006] According to a first aspect of the present invention, a sampling test method for a flash memory chip is provided, the method comprising: Perform erase, write, and read operations on all blocks of the flash memory chip to obtain the number of error bits per unit code length and the bit error rate of each page, and determine the maximum number of error bits per unit code length m0 and the maximum bit error rate per page n0 of the flash memory chip; where the unit code length is less than the page length. All blocks of the flash memory chip are divided into the same number of regions; For each region of all blocks, sort all the number of unit code length error bits in the region from largest to smallest, select the first proportion of unit code length error bits with the highest ranking and record the set of pages containing it; For the same region across all blocks, determine the set of all corresponding pages, count the occurrences of each page, and select the pages whose occurrences exceed the first threshold as the region test page address combinations. By merging all the region test page address combinations, the block test page address combination of the flash memory chip is obtained; Perform erase, write, and read operations on all blocks of the flash memory chip's block test page address combinations to reacquire the flash memory chip's maximum number of error bits per unit code length m1 and maximum page error rate n1; Determine the absolute values ​​of the differences between m1 and m0, and between n1 and n0. If the absolute values ​​of both differences are within the preset threshold, then use the block test page address combination to test the flash memory chips of the same specification batch.

[0007] In the above scheme, the method further includes: If at least one of the absolute values ​​of the two differences exceeds a preset threshold, then the first ratio is increased by the preset ratio or the first threshold is decreased by the preset number of times. If at least one of the absolute values ​​of the two differences still exceeds the preset threshold, the first ratio will continue to increase by the preset ratio or the first threshold will continue to decrease by the preset number of times until the absolute values ​​of the two differences are both within the preset threshold.

[0008] In the above scheme, the preset ratio is 1%-10%.

[0009] In the above plan, the first proportion is 5%-30%.

[0010] In the above scheme, the method further includes: All memory addresses of the flash memory chip are recorded and numbered in the controller's address module according to channel, chip enable, minimum control logic unit, minimum erase address block, and minimum write and read address unit page.

[0011] In the above scheme, the controller tests multiple flash memory chips in parallel, and at the same time tests multiple blocks of flash memory chips at once using multi-CE instructions.

[0012] In the above scheme, all blocks of the flash memory chip are divided into the same three regions according to their structural characteristics: the first segment region, the middle region, and the last segment region.

[0013] In the above scheme, the unit code length is 1KB, 2KB or 4KB.

[0014] According to a second aspect of the present invention, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the sampling test method for a flash memory chip according to any one of the first aspects.

[0015] According to a third aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of the sampling test method for a flash memory chip according to any one of the first aspects.

[0016] In summary, compared with the prior art, the above-described technical solutions conceived by this invention can achieve the following beneficial effects: This invention provides a sampling test method, device, and medium for flash memory chips, aiming to solve the problems of time-consuming and costly full-address testing under the surge in 3D NAND flash memory chip capacity, while ensuring test reliability. The method first performs erase, write, and read operations on all blocks of the flash memory chip to obtain the maximum number of error bits per unit code length (m0) and the maximum bit error rate (n0) per page as a benchmark. Then, all blocks of the flash memory chip are divided into several identical regions according to structural characteristics. The number of error bits per unit code length in each region is sorted, and high-error pages are selected and recorded as a set. Pages that appear more than a threshold across blocks are then selected to form region combinations, which are merged to obtain the block test page address combination. Subsequently, by performing erase, write, and read operations on this page address combination for all blocks, the maximum number of error bits per unit code length (m1) and the maximum bit error rate (n1) per page of the flash memory chip are obtained again. If the absolute value of the difference from the benchmark is within a preset threshold, the page address combination can be used for testing chips of the same specification batch, saving the writing and reading comparison time of pages not sampled. If the standard is not met, the sampling ratio or threshold is adjusted and repeatedly optimized. Compared to the industry practice of directly extracting a portion of blocks, the sampling test method of this invention has higher reliability and accuracy.

[0017] Furthermore, by combining the controller with address sequencing by channel, CE and other levels, as well as multi-die parallel testing and multi-CE instruction application, more testing time can be saved, thus reducing testing time and costs. Attached Figure Description

[0018] Figure 1 This is a schematic flowchart illustrating a sampling test method for a flash memory chip according to an embodiment of the present invention. Figure 2 This is a schematic diagram of the address module and its encoding according to an embodiment of the present invention; Figure 3 This is a schematic block diagram of an electronic device according to an embodiment of the present invention. Detailed Implementation

[0019] The following detailed description is merely exemplary in nature and is not intended to limit the disclosed technology or its application and use. Furthermore, it is not intended to be bound by any express or implied theory presented in the foregoing technical fields, background art, or the following detailed description.

[0020] In the following detailed description of the embodiments, numerous specific details are set forth in order to provide a more thorough understanding of the disclosed technology. However, it will be apparent to those skilled in the art that the disclosed technology can be practiced without these specific details. In other instances, well-known features have not been described in detail to avoid unnecessarily complicating the description.

[0021] Terms such as "comprising" and "including" indicate that, in addition to the units and steps that are directly and explicitly stated in the specification, the technical solution of the present invention does not exclude the presence of other units and steps that are not directly or explicitly stated. Terms such as "first" and "second" do not indicate the order of the units in terms of time, space, size, etc., but are merely used to distinguish the units.

[0022] Next, one or more embodiments of the present invention will be described in detail with reference to the accompanying drawings. Referring now to the drawings, Figure 1 This is a schematic flowchart of a sampling test method for a flash memory chip according to one or more embodiments of the present invention.

[0023] like Figure 1 As shown, based on the structural characteristics of flash memory chips, a sampling test method is proposed to ensure that each block is tested. This method specifies the number and range of pages for write and read comparisons according to the characteristics of each flash memory chip specification. Furthermore, it can also conform to and replace the results presented when all pages in each block are written and read compared. This method can shorten the write and read comparison time of unselected pages, thereby shortening the overall chip testing time and improving testing efficiency.

[0024] To ensure that all usable block addresses of the flash memory chip can be tested, the structure of all block addresses needs to be recorded in the controller, such as... Figure 2 As shown, according to the datasheet of the memory chip under test, all memory addresses of the memory chip are recorded in this address module according to channel, chip enable (CE), minimum control logic unit (LUN), minimum erase address block (Block), and minimum write and read address unit page (page), and numbered to ensure that no test is missed.

[0025] To test the data storage function of each storage unit, it is necessary to send an erase command to each block and confirm its success, and send write and read commands to each page to confirm the success of data writing and to determine the accuracy of the read data. The accuracy of the read data is generally expressed by parameters such as the maximum number of erroneous bits per unit code length (e.g., 1KB, 2KB, 4KB, etc., estimated data size) and the bit error rate.

[0026] The maximum number of error bits per unit code length is calculated by comparing read and write data within a set code length and recording the total number of error bits *m* within that code length. The maximum value *max(m)* is then output as the maximum error count. For the controller, if the maximum number of error bits *max(m)* in a block exceeds its error correction capability, that block is considered a bad block and can no longer be used. Therefore, the maximum number of error bits is a crucial parameter for determining the performance of a block.

[0027] Bit error rate (BER) = Total number of erroneous bits in the target page / Total number of written bits in the target page. The total number of erroneous bits in the BER is equal to the number of inconsistent bits found when comparing the read data (a string of bits) with the written data (a string of bits). Generally, a lower BER indicates a higher storage capacity for the memory unit.

[0028] This testing device uses a controller to send erase and write commands in parallel through multiple channels, serially reads data from the target page, and then uses a hardware comparison module to compare the read and written data to calculate the total number of error bits and directly calculate the bit error rate of the corresponding page.

[0029] To shorten testing time while ensuring testing accuracy, this invention proposes a sampling write and read mechanism, given a fixed testing device hardware. By writing and reading a small number of pages, the maximum number of error bits and the bit error rate can be obtained and predicted for all code lengths during full write and read operations.

[0030] The basic testing method is as follows: First, by batch testing all blocks of the same memory chip, the error bit distribution of each page is obtained and recorded. Then, by comparison, the distribution pattern of errors on each page under a set code length is found. The top 30% of pages with the highest error distribution in the block are selected as test samples. For these sampled pages in all blocks, erase, write, read, and read comparison operations are performed. The test results are compared with the results of all page erase, write, and read operations. If the maximum error bit error and the bit error rate error are within ±5%, it is considered a pass; otherwise, the number of sampled pages is increased and this process is repeated until the sampling test results meet the expected target.

[0031] This invention shortens the testing time of NAND flash memory chips by testing feature pages, effectively reducing testing time and cost by at least 30% while ensuring reliable test results. The method is designed based on chip error characteristics and is applicable to various models and capacities of NAND flash memory chips, improving testing efficiency without modifying the testing device hardware. The device tests multiple dies in parallel, and combined with multi-CE instructions, it can test multiple blocks of the chip at once, further improving the testing speed of high-capacity NAND chips.

[0032] Specifically, such as Figure 1 As shown, the sampling test method for flash memory chips in this embodiment includes the following steps: S1. Perform erase, write, and read operations on all blocks of the flash memory chip to obtain the number of error bits per unit code length and the bit error rate of each page, and determine the maximum number of error bits per unit code length m0 and the maximum bit error rate per page n0 of the flash memory chip; where the unit code length is less than the page.

[0033] In some embodiments, erase, write, and read operations are performed on all blocks of the flash memory chip to obtain the number of error bits per unit code length and the bit error rate of each page. Finally, the maximum number of error bits per unit code length and the page bit error rate are obtained, namely the maximum number of error bits per unit code length m0 and the maximum bit error rate of the page n0.

[0034] In this embodiment, the selected unit code length is 1KB, the page is 16KB, and a block consists of multiple pages.

[0035] S2. Divide all blocks of the flash memory chip into the same number of regions.

[0036] In some embodiments, the page number in each block of the flash memory chip die under test is divided into three or more regions according to structural characteristics, such as the first region M0, the middle region M1, and the last region M2.

[0037] S3. For each region of all blocks, sort all the number of unit code length error bits in the region from largest to smallest, select the first proportion of unit code length error bits in the ranking and record the page set where it is located.

[0038] In some embodiments, the pages where the largest error bits appear in the top 10% (or less, or more, depending on the test efficiency and accuracy requirements, such as 5%-30%) of each region Mx are recorded as t1, t2, t3...

[0039] This step selects three regions (front, middle, and back) based on the physical location of the block, and extracts address pages with overlapping large error distributions from each region. This is more detailed than the industry practice of directly extracting only a portion of the blocks, and better reflects the actual reliability performance of each memory block of the chip under test. Therefore, this sampling method is more accurate.

[0040] Furthermore, this invention combines the physical structure characteristics of NAND Flash with page-based sampling, ensuring that the sampled page number within each die remains consistent. This is because the controller can operate on multiple dies simultaneously when issuing test commands, resulting in higher execution efficiency using multi-CE commands and saving more test time.

[0041] S4. For the same region of all blocks, determine the set of all corresponding pages, count the number of times each page appears, and select the pages whose appearance count exceeds the first threshold as the combination of test page addresses for the region.

[0042] In some embodiments, from the set of page addresses where the largest error bits appear in the same region Mx of all blocks, a combination of page addresses with high overlap {t1,t2,t3...tn} is selected. The selection criterion is that the address capacity of this combination does not exceed 1 / 2 of the capacity of a single block. The sampled page number in each die must be consistent to improve testing efficiency.

[0043] Specifically, during the selection process, the frequency of each page can be counted, and a first threshold can be set in advance. When the frequency of a certain page in the same area of ​​all blocks exceeds the first threshold, that page is used as the area test page address for that area, and finally the combination of area test page addresses for that area is obtained, such as {t1,t3……tn}.

[0044] S5. Merge all region test page address combinations to obtain the block test page address combination of the flash memory chip.

[0045] In some embodiments, the test page addresses of the first region M0, the middle region M1, and the last region M2 are combined to obtain the test page address combination of the block.

[0046] S6. Perform erase, write, and read operations on the block test page address combinations of all blocks of the flash memory chip to reacquire the maximum number of error bits per unit code length m1 and the maximum page error rate n1 of the flash memory chip.

[0047] In some embodiments, each block of the flash memory chip is erased, and then a write-read-compare operation is performed on the block's test page address combination to obtain the new maximum number of error bits m1 and bit error rate n1. Verification is then performed by testing the same page address combination for each block (i.e., the block's test page address combination).

[0048] S7. Determine the absolute values ​​of the differences between m1 and m0, and n1 and n0. If the absolute values ​​of both differences are within a preset threshold, then test the flash memory chips of the same specification batch using the block test page address combination. If at least one of the absolute values ​​of the two differences exceeds the preset threshold, then the first ratio is increased by a preset ratio or the first threshold is decreased by a preset number of times. If at least one of the absolute values ​​of the two differences still exceeds the preset threshold, then the first ratio continues to increase by a preset ratio or the first threshold continues to decrease by a preset number of times, until the absolute values ​​of both differences are within the preset threshold.

[0049] In some embodiments, the difference between m1 and n1 and m0 and n0 is compared. If the ± error is less than 5% (or another target value), the process stops. If it is greater than the target value, the process returns to step S3 or S4 and repeats, changing the sampling method. For example, in step S3, the sampling ratio is increased by 10% (1%-10% is acceptable, or other values ​​are also acceptable), or in step S4, the first threshold is reduced by a preset number of times until the ± error is less than 5%. The maximum number of error bits per unit code length, m0 and m1, can be converted into errors, i.e., m1 minus m0 and then divided by m0; the preset number of times can be set according to actual conditions.

[0050] Finally, the set of test addresses that meet the target is written into the test script, which can be directly called when batch testing memory chips of the same specification. Each block can save the writing and reading comparison time of pages that have not been sampled.

[0051] The feasibility of this invention's method stems from the fact that NAND Flash production materials, equipment, and process control are consistent across batches of the same specification, resulting in similar error distributions. Industry practice dictates that if the maximum error value at any location within a block exceeds the controller's error correction range, the block is defined as a newly added bad block and no longer used. Therefore, the sampling criteria determined using this method are universal and applicable, and this sampling testing method can be applied to the vast majority of non-volatile memory solutions.

[0052] This test optimization method is designed based on chip error characteristics. Compared with the existing method of increasing test efficiency by adding test channels, the sampling test method proposed in this invention can improve test speed without increasing the cost of test equipment.

[0053] Figure 3 This is a schematic block diagram of an electronic device according to one or more embodiments of the present invention. The electronic device 200 includes a memory 210, a processor 220, and a computer program 230 stored on the memory 210 and executable on the processor 220. Execution of the computer program 230 causes a sampling test method for a flash memory chip as described in the above method embodiments to be performed. Exemplarily, the electronic device 200 may be a controller or a computer.

[0054] Alternatively, the present invention can also be implemented as a computer-readable storage medium storing a program for causing a computer to execute the sampling test method for a flash memory chip according to the above-described method embodiments. Here, various types of computer-readable storage media can be used, such as disks (e.g., magnetic disks, optical disks, etc.), cards (e.g., memory cards, optical cards, etc.), semiconductor memories (e.g., ROM, non-volatile memory, etc.), and tapes (e.g., magnetic tape, cassette tape, etc.).

[0055] Where applicable, the various embodiments provided by the present invention may be implemented using hardware, software, or a combination of hardware and software. Furthermore, where applicable, without departing from the scope of the invention, the various hardware and / or software components described herein may be combined into composite components comprising software, hardware, and / or both. Where applicable, without departing from the scope of the invention, the various hardware and / or software components described herein may be divided into sub-components comprising software, hardware, or both. Additionally, where applicable, it is contemplated that software components may be implemented as hardware components, and vice versa.

[0056] Software (such as program code and / or data) according to the invention can be stored on one or more computer-readable storage media. It is also contemplated that the software identified herein can be implemented using one or more networked and / or otherwise general-purpose or special-purpose computers and / or computer systems. Where applicable, the order of the various steps described herein can be changed, combined into compound steps, and / or divided into sub-steps to provide the features described herein.

[0057] The embodiments and examples presented herein are provided to best illustrate embodiments of the invention and its particular applications, thereby enabling those skilled in the art to practice and use the invention. However, those skilled in the art will understand that the above description and examples are provided merely for ease of illustration and example. The descriptions presented are not intended to cover all aspects of the invention or to limit the invention to the precise forms disclosed.

Claims

1. A sampling test method for flash memory chips, characterized in that, The method includes: Perform erase, write, and read operations on all blocks of the flash memory chip to obtain the number of error bits per unit code length and the bit error rate of each page, and determine the maximum number of error bits per unit code length m0 and the maximum bit error rate per page n0 of the flash memory chip; where the unit code length is less than the page length. All blocks of the flash memory chip are divided into the same number of regions; For each region of all blocks, sort all the number of unit code length error bits in the region from largest to smallest, select the first proportion of unit code length error bits with the highest ranking and record the set of pages containing it; For the same region across all blocks, determine the set of all corresponding pages, count the occurrences of each page, and select the pages whose occurrences exceed the first threshold as the region test page address combinations. By merging all the region test page address combinations, the block test page address combination of the flash memory chip is obtained; Perform erase, write, and read operations on all blocks of the flash memory chip's block test page address combinations to reacquire the flash memory chip's maximum number of error bits per unit code length m1 and maximum page error rate n1; Determine the absolute values ​​of the differences between m1 and m0, and between n1 and n0. If the absolute values ​​of both differences are within the preset threshold, then use the block test page address combination to test the flash memory chips of the same specification batch.

2. The sampling test method for flash memory chips according to claim 1, characterized in that, The method also includes: If at least one of the absolute values ​​of the two differences exceeds a preset threshold, then the first ratio is increased by the preset ratio or the first threshold is decreased by the preset number of times. If at least one of the absolute values ​​of the two differences still exceeds the preset threshold, the first ratio will continue to increase by the preset ratio or the first threshold will continue to decrease by the preset number of times until the absolute values ​​of the two differences are both within the preset threshold.

3. The sampling test method for flash memory chips according to claim 2, characterized in that, The preset ratio is 1%-10%.

4. The sampling test method for flash memory chips according to any one of claims 1 to 3, characterized in that, The first proportion is 5%-30%.

5. The sampling test method for flash memory chips according to claim 1, characterized in that, The method also includes: All memory addresses of the flash memory chip are recorded and numbered in the controller's address module according to channel, chip enable, minimum control logic unit, minimum erase address block, and minimum write and read address unit page.

6. The sampling test method for flash memory chips according to claim 5, characterized in that, The controller tests multiple flash memory chips in parallel, and simultaneously tests multiple blocks of flash memory chips at once using multi-CE instructions.

7. The sampling test method for flash memory chips according to claim 1, characterized in that, All blocks of the flash memory chip are divided into the same three regions according to their structural characteristics: the first region, the middle region, and the last region.

8. The sampling test method for flash memory chips according to claim 1, characterized in that, The unit code length is 1KB, 2KB, or 4KB.

9. An electronic device, characterized in that, The method includes a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the steps of the sampling test method for the flash memory chip according to any one of claims 1 to 8.

10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the sampling test method for the flash memory chip according to any one of claims 1 to 8.

Images