Multi-port low-voltage flexible interconnect topology and modulation control and analysis methods

Abstract

This invention provides a multi-port low-voltage flexible interconnect topology and a modulation control and analysis method. The modulation control method includes: obtaining the operational logic of three-port switch pairs in the multi-port low-voltage flexible interconnect topology; classifying all switches in the multi-port low-voltage flexible interconnect topology into multiplexed switches and independent switches, and designing switching states for the multiplexed switches and independent switches based on the operational logic of the three-port switch pairs; switching current sharing and smoothing of the switches using undetermined zero states; and, based on the switching current sharing and smoothing of the switches using undetermined zero states, finally obtaining the operational logic of the multi-port switch pairs, and designing a switching sequence that considers the direct conduction of independent switches in undetermined zero states to achieve modulation control of the multi-port low-voltage flexible interconnect topology.

Description

Technical Field

[0001] This invention relates to the fields of flexible interconnection of low-voltage distribution networks and power electronics technology, specifically to a multi-AC port low-voltage flexible interconnection topology and modulation control and analysis method. Background Technology

[0002] In recent years, with the continuous development of new power sources and loads, traditional radial distribution networks have encountered problems such as poor operational flexibility and uneven feeder loads. Meanwhile, urban development does not allow for rapid capacity expansion and upgrades. To avoid the negative impacts of high costs, wasted capacity, and frequent planned power outages associated with capacity expansion, and to meet the higher performance requirements of the distribution network in the new era, the concept of interconnection and mutual support between different power supply areas has been introduced into low-voltage distribution networks. Flexible interconnection technology enables interconnection and mutual supply between multiple transformer substations with complementary spatiotemporal load characteristics, breaking through the limitation of traditional distribution networks that can only operate in an open-loop manner.

[0003] However, this novel multi-port low-voltage flexible interconnection topology typically presents the following technical problems when used to interconnect and supply power to multiple transformer substations with complementary spatiotemporal load characteristics:

[0004] 1. Lack of a basis for determining a good operating range based on actual operating conditions.

[0005] 2. When the number of ports increases, the modulation scheme needs to be redesigned, which is cumbersome and lacks a unified modulation method for multiple ports. Summary of the Invention

[0006] To address the aforementioned shortcomings in the prior art, this invention provides a multi-AC port low-voltage flexible interconnect topology and a modulation control and analysis method.

[0007] According to one aspect of the present invention, a multi-AC port low-voltage flexible interconnect topology is provided, comprising: an ANPC three-level converter and a plurality of output half-bridge modules; wherein: the plurality of output half-bridge modules are connected in parallel between the upper and lower transistors of the ANPC three-level converter to form a plurality of AC output ports.

[0008] According to another aspect of the present invention, a modulation control method for a multi-AC port low-voltage flexible interconnect topology is provided, comprising:

[0009] The operational logic for acquiring three-port switch pairs in a multi-AC port low-voltage flexible interconnect topology;

[0010] All switches in a multi-port low-voltage flexible interconnect topology are classified as multiplexed switches. and independent switching transistors for each port Based on the operational logic of the three-port switch pair, the switching states of the multiplexed switch and the independent switch are designed respectively.

[0011] Based on the switching states of the multiplexed switch and the independent switch, when there are different signs at the port output, the current sharing and smoothing of the switch are switched using the undetermined O state.

[0012] Based on the current sharing and smooth switching of the switching transistors using the undetermined O state, the operation logic of the multi-port switch pair is finally obtained, and a switching sequence considering the independent switching transistors in the undetermined O state is designed to realize the modulation control of the multi-AC port low-voltage flexible interconnection topology.

[0013] Preferably, the computational logic for acquiring the three-port switch pair of the multi-AC port low-voltage flexible interconnect topology includes:

[0014] The port level is defined as P when the voltage output is positive relative to the DC midpoint; N when the voltage output is negative relative to the DC midpoint; and O when the voltage output is zero relative to the DC midpoint.

[0015] When the port level is P, the corresponding switch state is: and Simultaneous conduction, represented as When the port level is 0, the corresponding switch state is: and Simultaneous conduction, or, and Simultaneous conduction, represented as When the port level is N, the corresponding switch state is: and Simultaneous conduction, represented as ;

[0016] Will Defined as , Defined as The activation logic of the switch pair is summarized, and the operation logic of the three-port switch pair is obtained based on the activation logic of the switch pair.

[0017] Preferably, the activation logic of the switch pair includes:

[0018] The on / off state of a multiplexed switch depends on the state of all ports, while the on / off state of an independent switch depends only on the state of its corresponding port. Therefore, the activation logic for each switch includes:

[0019] When at least one of the ports has a P signal, the switch S 1. Turn on;

[0020] When at least one of the ports has a O+ signal, the switch S 2. Enable;

[0021] When at least one of the ports has an O- signal, the switch S 3. Enable;

[0022] When at least one of the ports has an N signal, the switch S 4. Turn on;

[0023] When switch When the corresponding port has both P and O+ signals, the corresponding switch Turn on;

[0024] When switch When both N and O- signals are present at the corresponding ports, the corresponding switches Start.

[0025] Preferably, the operational logic of the three-port switch pair includes:

[0026] When at least one of the ports has a P signal, perform an OR operation on the P signals of all ports; extract all modulated waves. The maximum value in and the upper triangular carrier Comparison, then the switch sequence signal D 1. D 3 and D At least one of the five ports is enabled; when at least one of the ports has an N signal, perform an OR operation on the N signals of all ports; take all modulated waves. The minimum value in the middle and the lower triangular carrier Comparison, then the switch sequence signal D 2. D 4 and D 6. When all are closed, it is equivalent to being open;

[0027] When switch and switch corresponding port i When both P and O+ signals are present, for the specified port i The P and O+ signals are ANDed; the corresponding switch is activated under the following conditions:

[0028] ;

[0029] ;

[0030] ;

[0031] In the formula, This indicates a bitwise AND operation between the two operations; express The NOT operation; in each group of two conduction conditions, if one of them is met, the circuit is turned on.

[0032] Preferably, the switch ,switch and switches Designed as complementary switch pairs, denoted as , indicating switch Switch state and switch The switching states correspond to complementary states.

[0033] Preferably, the step of switching the current sharing and smoothing of the switching transistor using an undetermined 0 state when there are different signals at the port output includes:

[0034] Acquiring three-port modulated waves The symbols ++ and - represent the port and switch status, respectively;

[0035] Based on the three ports The symbols ++ and - represent the port and switch state, respectively. In the undetermined state, the upper transistor of the independent switch is turned on first. At this time, the voltage across the lower transistor of the independent switch is clamped to 0. Then, the switch is turned on to realize the soft switching of the independent switch and complete the current sharing of the switch.

[0036] Based on the three ports The symbols ++ and - represent the port and switch state, respectively. By utilizing the different dead time, the multiplexed switch is first turned on to enter the undetermined 0 state, and then the independent switch is turned on to achieve soft switching, thus completing the smooth switching of the switch.

[0037] Preferably, the design considers a switch sequence where independent switches in an undetermined zero state are directly connected. After logical operations, the switch drive signal for each multiplexed switch pair is represented as follows:

[0038] ;

[0039] ;

[0040] ;

[0041] ;

[0042] in, Indicates will As The driving signals have the same meaning as the others, and will not be repeated here.

[0043] The switching drive signal for each individual switching transistor at each port is represented as follows:

[0044] ;

[0045] ;

[0046] In the case of adding dead time to the multiplexed switching transistor, the dead time of the independent switching transistor needs to be staggered from the dead time of the multiplexed switching transistor.

[0047] According to a third aspect of the present invention, a method for analyzing the operating range of a multi-AC port low-voltage flexible interconnect topology is provided, comprising:

[0048] First, the output characteristics of each port in different sectors and sub-regions are analyzed using SVPWM equivalent analysis.

[0049] Then, based on the output characteristics, the relationship between the duration of P and N levels and the modulation and angle is analyzed to establish an operating range model;

[0050] Finally, based on the aforementioned operating range model, during transient processes, ports that exceed the range are restricted to the operating boundary, ensuring safe operation while providing maximum output capacity.

[0051] Preferably, the step of using SVPWM equivalent analysis to analyze the output characteristics of each port in different sectors and sub-regions includes:

[0052] Based on in-phase stacked dual-carrier modulation and SVPWM, the maximum operating range within each phase is obtained as follows:

[0053] ;

[0054] When the range of all modulated waves is greater than 1, the PN output of the port will overlap, causing the withstand voltage of the independent switching transistor to exceed the set threshold.

[0055] If the operating range of the three phases is equivalent to a superimposed dual-carrier SPWM with different zero-sequence harmonic components, then the calculated action time of each vector of the modulated wave in each sub-region of each sector and the output waveform of the three-phase ports, constrained by the ports, are expressed as follows:

[0056] ;

[0057] In the formula, Let P and N represent the durations of the level at the i-th port, respectively. For switching cycles;

[0058] when When in the upper region, within one switching cycle, the sub-regions of the upper region are all P output in the middle and N output at both ends; the outputs of the three phases ABC are P, P, and N respectively;

[0059] when When in the lower half region, within one switching cycle, the sub-regions of the lower half region are all P output in the middle and N output at both ends; the outputs of the three phases ABC are P, N, and N respectively.

[0060] Preferably, the step of analyzing the relationship between the duration of P and N levels and the modulation and angle based on the output characteristics, and establishing an operating range model, includes:

[0061] Based on the aforementioned output characteristics, for sub-regions 3, 4, 5, and 6 within a sector, the duration of the PN level is related to the modulation depth m and angle θ, specifically the percentage of time in the N state within sub-regions 5 and 3. The percentage of time spent in state P in subregions 6 and 4 ,but:

[0062] In sub-region 5, The range of m is , The range is ;

[0063] In sub-region 3 The range of m is , The range is ;

[0064] In sub-region 4 The range of m is , The range is ;

[0065] In sub-region 6, The range of m is , The range is ;

[0066] Among them, 3 and 5 are sub-regions in the lower half of the region, and 4 and 6 are sub-regions in the upper half of the region;

[0067] In two adjustment systems m 1 and m 2. With the modulation of the two ports... The difference yields the corresponding maximum. This is the operating range, and the corresponding critical phase difference can be obtained according to different voltage magnitudes in actual application scenarios.

[0068] The solution is obtained by traversal method. and Based on the relationship, an operational range model is constructed.

[0069] Preferably, the step of restricting ports that exceed the operating range to the operating boundary during transient processes, based on the operating range model, includes:

[0070] During the transient process, there exists a range of the modulated waves at each port. ;

[0071] Ports outside the operating range The output is limited to the operating boundary to achieve maximum output; other ports output normally.

[0072] By adopting the above technical solution, the present invention has at least one of the following beneficial effects compared with the prior art:

[0073] This invention analyzes the detailed relationship between the operating range and actual working conditions, allowing the maximum operating range to be understood based on actual working conditions, thus providing a reference for initial design.

[0074] This invention designs a novel multi-port unified modulation method for a multi-port low-voltage flexible interconnect topology, which allows for convenient and quick design of modulation schemes even when the number of ports increases.

[0075] This invention analyzes the unified modulation method and operating range of multi-port ANPC topology, and utilizes the undetermined O state to perform current sharing and smooth switching of the switching transistors, thereby realizing the unified design of multi-port modulation methods; it obtains the quantitative relationship between the two-port modulation degree and the critical phase difference, and can obtain the corresponding operating range for different application scenarios. Attached Figure Description

[0076] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort. Wherein:

[0077] Figure 1 For multi-port ANPC topology;

[0078] Figure 2 This is a three-port in-phase dual-carrier modulation waveform (with the modulated waves having different signs).

[0079] Figure 3 To unify modulation logic;

[0080] Figure 4 It is a dual-modulation wave in-phase dual-carrier modulation waveform;

[0081] Figure 5 Vector diagram of three-level SVPWM;

[0082] Figure 6 This is the SVPWM vector diagram for sector 1;

[0083] Figure 7 This is the output level sequence for the upper half of sector 1;

[0084] Figure 8 This is the output level sequence for the lower half of sector 1;

[0085] Figure 9 The modulation wave range of the equipment in a low-voltage distribution network under normal conditions;

[0086] Figure 10 The operating range for multi-port ANPC topologies;

[0087] Figure 11 Diagram of a three-port ANPC simulation model;

[0088] Figure 12 The waveforms at the AC output terminals of the three ports of phase A;

[0089] Figure 13 The withstand voltage of the independent switch transistor in phase A and the overall waveform of the switch;

[0090] Figure 14 This shows the withstand voltage of the independent switch tube in phase A and the waveform details at a certain time during switching. Detailed Implementation

[0091] The embodiments of the present invention are described in detail below: These embodiments are implemented based on the technical solution of the present invention, and provide detailed implementation methods and specific operation processes. It should be noted that those skilled in the art can make several modifications and improvements without departing from the concept of the present invention, and these all fall within the protection scope of the present invention.

[0092] Existing multi-port ANPC (Active Neutral-Point Clamped) topologies have several problems, such as the lack of a good operating range to determine based on actual operating conditions, the need to redesign modulation schemes when the number of ports increases, which is cumbersome, and the lack of a unified modulation method for multiple ports.

[0093] To address the aforementioned issues, the present invention provides a multi-AC port low-voltage flexible interconnect topology and a modulation control and analysis method. By analyzing the detailed relationship between the operating range and actual operating conditions, the maximum operating range can be understood based on actual operating conditions, providing a reference for initial design. A novel multi-port unified modulation method for the multi-AC port low-voltage flexible interconnect topology is designed, enabling convenient and rapid design of modulation schemes even with an increasing number of ports. Through analysis of the unified modulation method and operating range of the multi-port ANPC topology, current sharing and smooth switching of the switching transistors are performed using the undetermined zero state, enabling a unified design of the multi-port modulation method. The quantitative relationship between the two-port modulation degree and the critical phase difference is obtained, allowing for the determination of the corresponding operating range for different application scenarios.

[0094] like Figure 1 As shown, the multi-AC port low-voltage flexible interconnect topology provided in this embodiment may include: an ANPC three-level converter and multiple output half-bridge modules.

[0095] Specifically, in Figure 1 In this circuit, multiple output half-bridge modules are connected in parallel between the upper and lower transistors of the ANPC three-level converter, forming multiple AC output ports. Each port outputs independently. The left side of the circuit is the DC section, containing two DC capacitors. C dc1 and C dc2 They are connected in series, with the intermediate node being the DC-side neutral point. The switching multiplexing section is composed of... Four switching transistors form a basic switching unit (phase A unit, and so on for other units), realizing the multiplexing function of the switching transistors. The port expansion section, based on the switching transistor multiplexing module, uses multiple sets of switching transistors (such as...) Expanding upon (etc.) to form multiple sub-units (such as...) This allows for port expansion. The right side of the circuit contains AC ports, divided into... n One AC port (port 1 to port 2) n Each AC port contains three-phase (A, B, C phase) output terminals, for example, port 1. V 1A 、V 1B 、V 1C Port 2 V 2A 、V 2B 、V 2C until the port n of V nA 、VnB 、V nC These ports are connected to the corresponding phase expansion sub-units to achieve multi-port AC output.

[0096] The aforementioned multi-AC port low-voltage flexible interconnect topology adds multiple output half-bridge modules to the traditional ANPC three-level converter topology, providing multiple AC ports and one DC port.

[0097] Based on the multi-AC port low-voltage flexible interconnect topology provided in the above embodiments of the present invention, an embodiment of the present invention also provides a modulation control method for the multi-AC port low-voltage flexible interconnect topology.

[0098] Specifically, the modulation control method for the multi-AC port low-voltage flexible interconnect topology provided in this embodiment may include:

[0099] The operational logic for acquiring three-port switch pairs in a multi-AC port low-voltage flexible interconnect topology;

[0100] All switches in a multi-port low-voltage flexible interconnect topology are classified as multiplexed switches. and independent switching transistors for each port Since the three-phase structure is symmetrical, the phase markings are omitted and they are referred to as multiplexed switching transistors. and independent switching transistors for each port Based on the operational logic of three-port switch pairs, the switching states of multiplexed and independent switches are designed separately.

[0101] Based on the switching states of the multiplexed and independent switching transistors, when there are different signs at the port output, the current sharing and smoothing of the switching transistors are switched using the undetermined O state.

[0102] Based on the current sharing and smooth switching of the switching transistors using the undetermined O state, the operation logic of the multi-port switch pair is finally obtained, and a switching sequence considering the independent switching transistors in the undetermined O state is designed to realize the modulation control of the multi-AC port low-voltage flexible interconnection topology.

[0103] like Figure 1 The multi-AC port low-voltage flexible interconnect topology shown will require a large number of switches when there are multiple AC ports, necessitating the search for a unified modulation method suitable for all ports. The port level is defined as P when the output voltage relative to the DC midpoint is positive; N when the output voltage relative to the DC midpoint is negative; and O when the output voltage relative to the DC midpoint is 0. The relationship between the switching state and output level of the i-th port is shown in Table 1. This refers to the switching state of the corresponding switching transistor. This represents the switching state of the two independent switches corresponding to the i-th port.

[0104] Table 1. Relationship between the switching state of the i-th port and the output level.

[0105]

[0106] In Table 1, Defined as , Defined as .

[0107] Depend on Figure 1 Table 2 can be obtained by analyzing and summarizing Table 1.

[0108] Table 2 Activation Logic of Switch Pairs

[0109]

[0110] The following is a topology analysis.

[0111] For the modulated wave of each port within each phase, They are upper and lower triangular carrier waves, respectively. They are respectively Figure 2 The switching sequence signal after comparing each modulated wave with the carrier wave.

[0112] Table 3

[0113]

[0114] 1. All switching transistors are mainly divided into two categories: multiplexed switching transistors: related to the state of all ports. Independent switching transistors: related only to the state of their own port. This refers to a multiplexed switching transistor. These are the independent switching transistors for each port.

[0115] 2. There is redundancy in the 0 state, so PN is prioritized for output. , Activation takes precedence over .

[0116] 3. Also, since P and O+, and N and O- cannot be output simultaneously, They cannot be turned on at the same time, so they can complement each other perfectly.

[0117] 4. For independent switching transistors, complementary design is not always required (we will first design based on complementary design).

[0118] Based on this, the waveform of three-port in-phase dual-carrier modulation can be obtained as follows: Figure 2 As shown.

[0119] Based on Table 2 and previous experience, the operational logic of the three-port switch pair shown in Table 3 can be derived.

[0120] Furthermore, a three-port array is obtained. The symbols ++ and - represent the port and switch states, as shown in Table 4. Note that this raises the following two issues:

[0121] 1. When the port is "O", the corresponding table is represented as O state and it is impossible to determine whether it is O+ or O-. When entering or leaving the undetermined O state, multiple switches will operate simultaneously.

[0122] 2. If the circuit operates twice within a single switching cycle, a hard interruption would increase losses.

[0123] Table 4 Three-port The symbols ++ and - represent the states of the port and switch, respectively.

[0124]

[0125] Regarding question 1, forcibly defining the undetermined O state as O+ or O- will not help solve this problem, namely, how to achieve smooth switching of the switching transistor in the undetermined O state.

[0126] Regarding question 2, multiple actions of the switching transistor do not necessarily mean increased losses. The key is to see whether the action is "soft".

[0127] The reason why the undetermined O state is "undetermined" is due to the intermediate clamping tube. Simultaneous conduction ensures that the output is in a zero state regardless of which independent switch is conducting. Furthermore, if both independent switches are conducting simultaneously, they can be connected in parallel, sharing current and reducing stress on the switches; this state should be prolonged as much as possible. Therefore, if the upper switch of an independent switch is conducting in an undetermined zero state, the voltage across the lower switch is clamped to 0. This conduction at this point is considered "soft," causing no additional losses and thus solving problem 2.

[0128] Regarding question 1, the difference in dead time can be used to make the multiplexed switch first turn on and enter the undetermined O state, and then turn on the independent switch to achieve soft switching.

[0129] Therefore, the final multi-port modulation logic is shown in Tables 5 and 6. To unify the representation of each port, here... for The switching sequence compared with the upcarrier, for A switching sequence compared to the download wave. For example... Corresponding to Table 3 and , like Corresponding to Table 3 and .

[0130] Table 5 Multi-port switch operation logic

[0131]

[0132] Table 6 Switching sequences considering independent switches with undetermined zero state shoot-through

[0133]

[0134] In the table, + and These represent logical OR and logical AND operations, respectively. If true, it indicates that the current state is undetermined (O state). The values ​​are 0 and 1 respectively, and all independent switching transistors are set to 1, indicating the on state.

[0135] If a multiplexed switching transistor requires a dead time (e.g., 1µs), then the dead time of an independent switching transistor needs to be staggered (e.g., extended to 2µs).

[0136] Based on the multi-AC port low-voltage flexible interconnect topology provided in the above embodiments of the present invention, an embodiment of the present invention also provides a method for analyzing the operating range of the multi-AC port low-voltage flexible interconnect topology.

[0137] Specifically, the operating range analysis method for the multi-AC port low-voltage flexible interconnection topology provided in this embodiment may include:

[0138] First, the output characteristics of each port in different sectors and sub-regions are analyzed using SVPWM equivalent analysis.

[0139] Then, based on the output characteristics, the relationship between the duration of P and N levels and the modulation and angle is analyzed to establish an operating range model;

[0140] Finally, based on the operating range model, during transient processes, ports that exceed the range are restricted to the operating boundary to ensure safe operation while providing maximum output capacity.

[0141] The operating range analysis method for a multi-AC port low-voltage flexible interconnection topology provided in this embodiment addresses the amplitude and phase differences in voltages at the ends of multiple feeders in a low-voltage distribution network flexible interconnection scenario. It also notes that to maintain the three-level characteristics of this topology, P and N cannot be simultaneously output on all ports of the same phase, which is clearly related to the phase and amplitude of the modulation wave. The operating range analysis method provided in this embodiment aims to explore the conditions under which P and N will not be simultaneously output on all ports of the same phase, i.e., the operating range, and to find the relationship between the maximum phase difference and amplitude of multiple feeders.

[0142] The operating range is primarily related to the modulation method. The unified modulation method described above uses in-phase stacked dual-carrier modulation. Other methods, such as in-phase stacked dual-carrier modulation, have the P and N phases of the carrier phase-shifting modulation overlapping exactly within one switching cycle, while in-phase stacked dual-carrier modulation has them staggered exactly within one switching cycle. Figure 4 As shown, this is the only feasible carrier comparison modulation method; and the in-phase stacked dual-carrier stacking and SVPWM (space vector pulse width modulation, such as...) Figure 5 As shown, there is also a corresponding relationship, which can be studied in conjunction with SVPWM. The maximum operating range within each phase can be simply obtained as:

[0143] ;

[0144] When the range of all modulated waves is greater than 1, the PN output of the port will inevitably have an overlap time, which will result in the independent switching transistor having an excessively high withstand voltage.

[0145] To study the operating range of the three phases, we start with SVPWM, which can be equivalent to in-phase stacked dual-carrier SPWM (sine pulse width modulation) with different zero-sequence component harmonics superimposed.

[0146] It is sufficient to study the situation within sector I, such as Figure 6 .

[0147] Then the action time of each vector of the modulated wave at each port in each sub-region 1, 2, 3, 4, 5, 6 and the output waveform of the three-phase ports can be calculated, based on the port constraints:

[0148] ;

[0149] In the formula, Let P and N represent the durations of the level at the i-th port, respectively. for.

[0150] Analysis of each region shows that when When in the upper half region 2, 4, and 6, the output levels of the three ports are as follows: Figure 7 As shown, note that within one switching cycle, sub-regions 2, 4, and 6 all output P in the middle and N at both ends; and phases ABC output P, ​​P, and N respectively.

[0151] In the lower half of the region, 1, 3, and 5, the output levels of the three ports are as follows: Figure 8 As shown, note that sub-region 135 can still maintain P output in the middle and N output at both ends; however, the outputs of phases ABC become P, N, N; this means that when the modulated waves of all ports are in the same half-region, they will not exceed the port constraints, but when they are in different half-regions, there may be a partial overlap of PN on phase B, and an operating range will be obtained by the port constraints, such as... Figure 9 As shown.

[0152] Considering that in a practical 380V distribution network, the voltage range can be -7% to +7%; the DC bus voltage is ±375V, ±5%; therefore, the regulation system... The range is 0.668~0.768. That is, within the 3rd, 4th, 5th, and 6th sub-regions, the relationship between the duration of the PN level and the modulation depth m and angle θ is shown in Table 7.

[0153] Table 7. Duration of PN level in subregions 3, 4, 5, and 6

[0154]

[0155] Under the two modulation systems, as The difference can yield the corresponding maximum. This refers to the operating range, which allows us to determine the critical phase difference based on different voltage levels in actual application scenarios.

[0156] This involves trigonometric functions, which are solved using a traversal method. The result is... and Relationship such as Figure 10 As shown, even when traversing sub-regions 3, 4, 5, and 6, the minimum critical phase difference is approximately 27°. In practical multi-terminal low-voltage flexible interconnects, the phase difference is smaller (<15°). Therefore, this topology can basically meet the application scenario, and thus all switching transistors are adopted. Its high-voltage design significantly reduces the cost of switching transistors.

[0157] The above operating range analysis is based on the steady-state operating range. During transient processes, there may be brief periods when the operating range is exceeded, i.e., the range of the modulated waves at each port changes. This needs to be restricted.

[0158] Considering that the out-of-range operation occurs during a transient process, to ensure the largest possible port output, the ports exceeding the operating range should be... Limit the output to the operating boundary to achieve maximum output; other ports should output normally.

[0159] The technical solution provided by the above embodiments of the present invention will be further described in detail below with reference to a simulation example.

[0160] like Figure 1 As shown, this is a multi-AC port low-voltage flexible interconnection topology provided in the above embodiment of the present invention. Based on this topology, the modulated wave can be amplified to the AC port through reasonable switching actions.

[0161] This simulation example demonstrates... Figure 1The topology shown, along with its corresponding adjustment control method and operating range analysis method, will be further explained. The system will then be simulated and verified using MATLAB / Simulink 2024a software.

[0162] Combination Figure 1 and Figure 3 This simulation example demonstrates how to perform unified modulation on a three-port ANPC topology.

[0163] like Figure 11 As shown, the AC input port of the topology is connected to a 380V three-phase feeder on the power supply side. The equipment operation is maintained by controlling the DC side voltage stability and setting the power transfer values ​​for the three ports. Simulation results are as follows... Figure 12 , Figure 13 and Figure 14 As shown, the unified modulation control method provided by the above embodiments of the present invention can output a square wave sequence with a duty cycle varying according to the modulation wave magnitude at the AC port. Simultaneously, the maximum withstand voltage of all switching transistors is half the DC voltage of 80V, maintaining the original three-level characteristics. Furthermore, due to the addition of a shoot-through time, smooth switching of independent switching transistors can be achieved.

[0164] It is important to note that the constructions and arrangements of this application shown in several different exemplary embodiments are merely illustrative. Although only a few embodiments are described in detail in this disclosure, those who consult this disclosure will readily understand that many modifications are possible (e.g., changes in the size, dimensions, structure, shape, and proportions of various elements, as well as parameter values ​​(e.g., temperature, pressure, etc.), mounting arrangements, use of materials, color, orientation, etc.) without substantially departing from the novel teachings and advantages of the subject matter described in this application). For example, an element shown as integrally formed may be composed of multiple parts or elements, the position of elements may be inverted or otherwise altered, and the nature or number or position of discrete elements may be changed or altered. Therefore, all such modifications are intended to be included within the scope of the invention. The order or sequence of any process or method steps may be changed or rearranged according to alternative embodiments. In the claims, any "device plus function" clause is intended to cover the structure performing the function described herein, and not only structural equivalents but also equivalent structures. Other substitutions, modifications, alterations, and omissions may be made in the design, operation, and arrangement of the exemplary embodiments without departing from the scope of the invention. Therefore, the present invention is not limited to the specific embodiments, but extends to various modifications that still fall within the scope of the appended claims.

[0165] The multi-port low-voltage flexible interconnect topology and its modulation control method provided in the above embodiments of the present invention utilize the undetermined O state to perform current sharing and smooth switching of the switching transistors, which can realize the unified design of multi-port modulation methods; and obtain the quantitative relationship between the two-port modulation degree and the critical phase difference, so as to obtain the corresponding operating range for different application scenarios.

[0166] Any matters not covered in the above embodiments of the present invention are well-known in the art.

[0167] The specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various modifications or variations within the scope of the claims, which do not affect the essence of the present invention.

Claims

1. A method for analyzing the operating range of a multi-AC port low-voltage flexible interconnection topology, wherein the multi-AC port low-voltage flexible interconnection topology is a multi-port multiplexing topology based on an ANPC three-level converter, including an ANPC three-level converter and multiple output half-bridge modules; each phase of the ANPC three-level converter includes four main switching transistors connected in series between the positive and negative terminals of the DC bus, and multiple output half-bridge modules are connected in parallel between the two middle main switching transistors of the same phase of the ANPC three-level converter to form multiple AC output ports, each output half-bridge module containing two independent switching transistors; characterized in that, The operating range analysis method includes: First, based on the equivalent of in-phase stacked dual-carrier modulation and SVPWM, the output characteristics of each port in different sectors and sub-regions divided according to the phase angle θ of the reference voltage vector are analyzed, and the maximum operating range within each phase is obtained as follows: ； In the formula, , The modulation wave of each AC output port within each phase; And determine the port constraints as follows: ； In the formula, These represent the durations of the P-level and N-level signals at the i-th port, respectively. For switching cycles; Specifically, when the voltage of the port output relative to the DC midpoint is positive, the port level is P; when the voltage of the port output relative to the DC midpoint is negative, the port level is N. When the range of all modulated waves is greater than 1, the P level and N level of the port output will overlap for a period of time, causing the withstand voltage of the independent switching transistor to exceed the set threshold. Then, based on the output characteristics, the relationship between the duration of the P level and N level and the modulation intensity m and phase angle θ is analyzed, and an operating range model is established, including: For sub-regions 3, 4, 5, and 6 within sector I of SVPWM, where sub-regions 3 and 5 belong to the lower half of the region, the time percentage of the N-level in these sub-regions is as follows: Subregions 4 and 6 belong to the upper half of the region, and the time percentage of the P-level in these subregions is... ,but: In sub-region 5, , where the range of m is , The range is ; In sub-region 3 , where the range of m is , The range is ; In sub-region 4, , where the range of m is , The range is ; In sub-region 6, , where the range of m is , The range is ; Under two-port modulation, with the two-port modulated wave The difference yields the corresponding maximum. This is the operating range, and the corresponding critical phase difference is obtained accordingly. The solution is obtained by traversal method. and Based on the relationship, a runtime model is constructed; Finally, based on the aforementioned operating range model, during the transient process, the maximum and minimum values ​​of the port modulation wave that exceed the operating range are limited to the operating boundary, ensuring safe operation while providing maximum output capability, and other ports output normally.

2. The method for analyzing the operating range of a multi-AC port low-voltage flexible interconnect topology according to claim 1, characterized in that, when When in the upper region, within one switching cycle, the sub-regions of the upper region are all P output in the middle and N output at both ends; the outputs of the three phases ABC are P, P, and N respectively; when When in the lower half region, within one switching cycle, the sub-regions of the lower half region are all P output in the middle and N output at both ends; the outputs of the three phases ABC are P, N, and N respectively.

3. The method for analyzing the operating range of a multi-AC port low-voltage flexible interconnect topology according to claim 1, characterized in that, The method of limiting the maximum and minimum values ​​of the port modulation wave that exceed the operating range to the operating boundary during the transient process includes: During the transient process, there exists a range of the modulated waves at each port. ; The maximum and minimum values ​​of the port modulation wave that are outside the operating range are limited to the operating boundary in order to achieve maximum output.

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