Phase delay circuit and clock generator

Abstract

The application provides a phase delay circuit and a clock generator, which comprises at least two delay modules, the delay modules are connected in cascade, an input end of a first delay module of the cascade connection is connected with a signal to be delayed, a first output end is connected with an input end of a next delay module, second output ends of each delay module are connected with an output end of the phase delay circuit and a first end of a preset common load resistor in parallel, a delay setting module decodes a delay setting signal to obtain two control signals with multiple bits, a first control end and a second control end of a last delay module of the cascade connection are grounded, the first control end of the rest delay modules is connected with a control bit of a first control signal respectively, and the second control end is connected with a control bit of a second control signal respectively, the circuit can effectively improve the phase delay precision, and can conveniently adjust and control the total delay, i.e. the sum of the delay of each delay module.

Description

Technical Field

[0001] This application relates to the field of integrated circuit technology, and in particular to a phase delay circuit and a clock generator. Background Technology

[0002] In modern electronic systems, the clock generator serves as the core of synchronization and timing control, and its performance directly determines the stability and processing power of the entire system. The phase delay circuit, as a key module in the clock generator, bears the important responsibility of accurately modulating the phase and controlling the delay of the clock signal. Therefore, the accuracy, stability, and reliability of the phase delay circuit are crucial indicators for evaluating the overall performance of the clock generator. Depending on the different requirements of modern electronic systems, the requirements for phase delay accuracy and total delay of clock signals at different frequencies also vary.

[0003] Currently common phase delay circuits suffer from low phase delay accuracy and difficulty in adjusting and controlling the total delay, thus failing to adequately meet the high-precision requirements of modern electronic systems. Summary of the Invention

[0004] This application provides a phase delay circuit and a clock generator to solve the technical problems of low phase delay accuracy and difficulty in adjusting and controlling the total delay in existing phase delay circuits.

[0005] This application provides a phase delay circuit, the circuit comprising: at least two delay modules, each delay module including an input terminal, a first output terminal, a second output terminal, a first control terminal, and a second control terminal, the delay modules being cascaded, the input terminal of the first cascaded delay module being connected to the signal to be delayed, the first output terminal being connected to the input terminal of the next stage delay module, the second output terminals of each delay module being connected in parallel and respectively connected to the output terminal of the phase delay circuit and the first terminal of a preset common load resistor, the second terminal of the common load resistor being connected to the power supply voltage; The delay setting module receives a delay setting signal and decodes the delay setting signal to obtain two multi-bit width control signals for controlling the delay amount of the delay module. The first control terminal and the second control terminal of the last cascaded delay module are both grounded. The first control terminal of the remaining delay modules are connected to the corresponding control bit in the first control signal, and the second control terminal is connected to the corresponding control bit in the second control signal.

[0006] In one embodiment of this application, the delay module includes: A normally open two-stage amplifier circuit is connected to the signal to be delayed, and the signal to be delayed is delayed once to obtain a first delayed signal. The amount of the first delay is adjustable. The target amplifier circuit receives the first delayed signal and, based on the control signals received at its first and second control terminals, performs a second delay on the first delayed signal to obtain and output the second delayed signal.

[0007] In one embodiment of this application, the signal to be delayed is a differential signal, the differential signal includes a first signal and a second signal with opposite polarities, the first output terminal includes a first differential output positive terminal and a first differential output negative terminal, and the normally open two-stage amplifier circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor; The bases of the first, fourth, and sixth transistors are all connected to a preset reference voltage. The emitters of the first, fourth, and sixth transistors are all grounded. The collector of the first transistor is connected to the emitters of the second and third transistors, respectively. The base of the second transistor is connected to the first signal input port of the current delay module, which is used to input the first signal. The base of the third transistor is connected to the second signal input port of the current delay module, which is used to input the second signal. The collector of the second transistor... The collector of the third transistor is connected to the power supply voltage, the first terminal of the first capacitor, and the base of the seventh transistor, respectively. The collector of the third transistor is connected to the power supply voltage, the first terminal of the first capacitor, and the base of the fifth transistor, respectively. The second terminal of the second capacitor and the second terminal of the first capacitor are grounded, respectively. The collectors of the fifth transistor and the seventh transistor are connected to the power supply voltage, respectively. The emitter of the fifth transistor is connected to the collector of the fourth transistor and the positive terminal of the first differential output of the current delay module, respectively. The emitter of the seventh transistor is connected to the collector of the sixth transistor and the negative terminal of the first differential output of the current delay module, respectively.

[0008] In one embodiment of this application, the delay of the normally open secondary amplifier circuit is adjusted by adjusting at least one of the collector current of the first transistor, the collector current of the fourth transistor, the collector current of the sixth transistor, the capacitance of the first capacitor, and the capacitance of the second capacitor.

[0009] In one embodiment of this application, the normally open secondary amplifier circuit further includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The emitter of the first transistor is grounded through the first resistor, the emitter of the fourth transistor is grounded through the fourth resistor, the emitter of the sixth transistor is grounded through the fifth resistor, the collector of the second transistor is connected to the power supply voltage through the second resistor, and the collector of the third transistor is connected to the power supply voltage through the third resistor. The first resistor, the fourth resistor, and the fifth resistor are all used for current regulation, and the second resistor and the third resistor are both used for signal swing regulation.

[0010] In one embodiment of this application, the second output terminal includes a second differential output positive terminal and a second differential output negative terminal, and the target amplifier circuit includes: an eighth transistor, a ninth transistor, a thirteenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first switch, and a second switch; The first terminal of the first switch is connected to the first control terminal of the current delay module, and the second terminal of the first switch is connected to the base of the eighth transistor. The emitter of the eighth transistor is grounded. The bases of the ninth transistor and the twelfth transistor are respectively connected to the positive terminal of the first differential output. The bases of the thirteenth transistor and the twelfth transistor are respectively connected to the negative terminal of the first differential output. The collectors of the thirteenth transistor and the twelfth transistor are respectively connected to the positive terminal of the second differential output. The collectors of the ninth transistor and the twelfth transistor are respectively connected to the positive terminal of the second differential output. The 12th transistor is connected to the negative terminal of the second differential output. The emitters of the 9th and 13th transistors are connected to the collectors of the 8th transistor. The first terminal of the second switch is connected to the second control terminal of the current delay module. The second terminal of the second switch is connected to the base of the 11th transistor. The emitter of the 11th transistor is grounded. The collector of the 11th transistor is connected to the emitters of the 12th and 13th transistors. Both the first and second switches close when a high level is received.

[0011] In one embodiment of this application, the first switch includes: a first inverter, a first NMOS transistor, and a second NMOS transistor; the second switch includes: a second inverter, a third NMOS transistor, and a fourth NMOS transistor. The input terminal of the first inverter is connected to the first control terminal of the current delay module. The output terminal of the first inverter is connected to the gate of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor and the base of the eighth transistor. The gate of the first NMOS transistor is connected to the first control terminal of the current delay module. The source of the first NMOS transistor is connected to the reference voltage and the source of the third NMOS transistor. The gate of the third NMOS transistor and the input terminal of the second inverter are connected to the second control terminal of the current delay module. The output terminal of the second inverter is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor and the base of the eleventh transistor.

[0012] In one embodiment of this application, the delay of the target amplifier circuit is determined based on the control signal input to the first control terminal and the control signal input to the second control terminal of the delay module in which it is located, as well as the target current difference, wherein the target current difference is the difference between the collector current of the eighth transistor and the collector current of the eleventh transistor.

[0013] In one embodiment of this application, the target amplifier circuit further includes a sixth resistor and a seventh resistor; The emitter of the eighth transistor is grounded through the sixth resistor, and the emitter of the eleventh transistor is grounded through the seventh resistor. Both the sixth and seventh resistors are adjustable resistors used for current regulation.

[0014] This application also provides a clock generator, including: a phase delay circuit as described in any of the preceding claims.

[0015] The beneficial effects of this application are as follows: The phase delay circuit and clock generator proposed in this application include: at least two delay modules, each including an input terminal, a first output terminal, a second output terminal, a first control terminal, and a second control terminal. The delay modules are cascaded together. The input terminal of the first cascaded delay module is connected to the signal to be delayed, and the first output terminal is connected to the input terminal of the next stage delay module. The second output terminals of each delay module are connected in parallel and then connected to the output terminal of the phase delay circuit and the first terminal of a preset common load resistor, with the second terminal of the common load resistor connected to the power supply voltage. A delay setting module receives a delay setting signal and decodes it to obtain two multi-bit width control signals for controlling the delay amount of the delay modules. The first and second control terminals of the last cascaded delay module are both grounded. The first control terminals of the remaining delay modules are connected to the corresponding control bits in the first control signal, and the second control terminals are connected to the corresponding control bits in the second control signal. This circuit can effectively improve the phase delay accuracy and facilitate the adjustment and control of the total delay amount, i.e., the sum of the delay amounts of each delay module. It is highly feasible and has a low cost. Attached Figure Description

[0016] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0017] In the attached diagram: Figure 1 This is a schematic diagram of the phase delay circuit provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the delay module in a phase delay circuit provided in one embodiment of this application; Figure 3 The transient curve of the differential output difference signal (the difference between the first differential output signal OUTP and the second differential output signal OUTN with opposite polarities output by the phase delay circuit) when the delay setting signal is set to the range of 0 to 6 in one embodiment of this application is provided. Figure 4 The characteristic curves of the delay step size and delay setting signal of the phase delay circuit provided in one embodiment of this application within a temperature range of -55℃ to 125℃ are shown (n=9, number of delay modules = n+1, when n=9, the number of delay modules is 10). Figure 5In one embodiment of this application, the total delay of the phase delay circuit versus the characteristic curve of the delay setting signal within a temperature range of -55℃ to 125℃ is provided (n=9). Detailed Implementation

[0018] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. In the absence of conflict, the following embodiments and features in the embodiments can be combined with each other.

[0019] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. The drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0020] In the following description, numerous details are explored to provide a more thorough explanation of embodiments of the present application. However, it will be apparent to those skilled in the art that embodiments of the present application may be practiced without these specific details. In other embodiments, well-known structures and devices are shown in block diagram form rather than in detail to avoid obscuring embodiments of the present application.

[0021] Please see Figure 1 , Figure 1 This is a schematic diagram of the phase delay circuit provided in an embodiment of this application, as shown below. Figure 1As shown, the circuit includes at least two delay modules. Each delay module includes an input terminal (including a differential positive input terminal (I terminal) and a differential negative input terminal (IN terminal)), a first output terminal (including a first differential positive output terminal (Z0 terminal) and a first differential negative output terminal (ZN0 terminal)), a second output terminal (including a second differential positive output terminal (Z1 terminal) and a second differential negative output terminal (ZN1 terminal)), a first control terminal S1, and a second control terminal S2. The delay modules are cascaded, and the input terminal (I terminal and IN terminal) of the first cascaded delay module is connected to the signal to be delayed. The circuit includes a first signal INP and a second signal INN with opposite polarities. The first output terminal (Z0 terminal and ZN0 terminal) is connected to the input terminal (I terminal and IN terminal) of the next stage delay module. The second output terminals (Z1 terminal and ZN1 terminal) of each delay module are connected in parallel and then connected to the output terminal of the phase delay circuit (used to output delayed output signals, which include a first differential output signal OUTP and a second differential output signal OUTN with opposite polarities) and the first terminal of a preset common load resistor. The second terminal of the common load resistor is connected to the power supply voltage VCC. The delay setting module receives a delay setting signal D[m:0] (D[m:0] can be any decimal value). It decodes the delay setting signal to obtain two multi-bit width control signals for controlling the delay amount of the delay modules (including a first multi-bit width control signal S1[n-1:0], which includes n control bits, and a second multi-bit width control signal S2[n-1:0], which also includes n control bits, each with its own independent line). The first control terminal S1 and the second control terminal S2 of the last cascaded delay module are both grounded. The first control terminal S1 of the remaining delay modules is connected to the corresponding control bit in the first control signal, and the second control terminal S2 is connected to the corresponding control bit in the second control signal.

[0022] In some examples of this embodiment, the number of delay modules can be n+1, where n≥1.

[0023] In some examples of this embodiment, the delay module also includes a VB (reference voltage) terminal for connecting to the reference voltage VB.

[0024] In some examples of this embodiment, the first signal INP is connected to the differential input positive terminal (I terminal) of the delay module, and the second signal INN is connected to the differential input negative terminal (IN terminal) of the delay module.

[0025] In some examples of this embodiment, when the input and output of the entire circuit are differential signals, the common load resistor includes a first common load resistor RG1 and a second common load resistor RG2. The Z1 terminals of each delay module are connected in parallel and then connected to the power supply voltage VCC through the first common load resistor RG1. The ZN1 terminals of each delay module are connected in parallel and then connected to the power supply voltage VCC through the second common load resistor RG2.

[0026] In some examples of this embodiment, the first multi-bit wide control signal S1[n-1:0] is connected from low to high bits (including the n control bits S1[0] to S1[n-1]) to the S1 terminal of the corresponding delay module (the multiple control bits of the first multi-bit wide control signal S1[n-1:0] correspond one-to-one with the delay module). The second multi-bit wide control signal S2[n-1:0] is connected from low to high bits (including the n control bits S2[0] to S2[n-1]) to the S2 terminal of the corresponding delay module (the multiple control bits of the second multi-bit wide control signal S2[n-1:0] correspond one-to-one with the delay module).

[0027] In some examples of this embodiment, the first output (Z0 and ZN0) of the last stage delay module is left floating.

[0028] Understandably, by setting multiple delay modules, the scalable delay range of the phase delay circuit can be effectively broadened, and computational complexity can be reduced. Furthermore, by setting the aforementioned delay setting modules and designing the aforementioned connection methods, delay control accuracy can be improved, and the total delay, i.e., the sum of the delays of each delay module, can be easily adjusted and controlled. For example, the total delay can be adjusted by setting different delay setting signals.

[0029] In some examples of this embodiment, the delay setting module can be a decoder, etc. Table 1 below provides an exemplary truth table for the decoder: Table 1. Examples of decoder truth representations

[0030] like Figure 1As shown in Table 1 above, the delay setting signal D[m:0] is decoded by the decoder to output control signals (S1[n-1:0], S2[n-1:0]), which are used to control the specific working state of each delay module. For any setting value of the delay setting signal (D[m:0]), the output control signals (S1[n-1:0], S2[n-1:0]) have exactly one bit (control bit) that is 1. Furthermore, only two adjacent delay modules can work simultaneously, such as the first and second delay modules working simultaneously, or the second and third delay modules working simultaneously; there is no situation where non-adjacent delay modules, such as the first and third delay modules, work simultaneously. The decimal representation of the delay setting signal (D[m:0]) is the number of delay steps.

[0031] In some embodiments, the delay module includes: A normally open two-stage amplifier circuit is connected to the signal to be delayed, and the signal to be delayed is delayed once to obtain a first delayed signal. The amount of the first delay is adjustable. The target amplifier circuit receives the first delayed signal and, based on the control signals received at its first control terminal S1 and second control terminal S2, performs a second delay on the first delayed signal to obtain and output the second delayed signal.

[0032] It should be noted that by setting up the normally open secondary amplifier circuit and the target amplifier circuit described above, delay control can be easily performed, and the flexibility is high.

[0033] Please refer to Figure 2 In some embodiments, the normally open secondary amplifier circuit includes: a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, a first capacitor C1, and a second capacitor C2. The bases of the first transistor Q1, the fourth transistor Q4, and the sixth transistor Q6 are all connected to a preset reference voltage. The emitters of the first transistor Q1, the fourth transistor Q4, and the sixth transistor Q6 are all grounded. The collector of the first transistor Q1 is connected to the emitters of the second transistor Q2 and the third transistor Q3, respectively. The base of the second transistor Q2 is connected to the first signal input port of the current delay module, which is used to input the first signal. The base of the third transistor Q3 is connected to the second signal input port of the current delay module, which is used to input the second signal. The collector of the second transistor Q2 is connected to the... The source voltage, the first terminal of the second capacitor C2, and the base of the seventh transistor Q7 are connected to the power supply voltage, the first terminal of the first capacitor C1, and the base of the fifth transistor Q5, respectively. The second terminal of the second capacitor C2 and the second terminal of the first capacitor C1 are grounded. The collectors of the fifth transistor Q5 and the seventh transistor Q7 are connected to the power supply voltage. The emitter of the fifth transistor Q5 is connected to the collector of the fourth transistor Q4 and the first differential output positive terminal (Z0 terminal) of the current delay module, respectively. The emitter of the seventh transistor Q7 is connected to the collector of the sixth transistor Q6 and the first differential output negative terminal (ZN0 terminal) of the current delay module.

[0034] It should be noted that the above settings can effectively achieve a one-time delay of the input signal to be delayed, and the controllability is relatively strong.

[0035] In some embodiments, the delay of the normally open secondary amplifier circuit is adjusted by adjusting at least one of the collector current of the first transistor Q1, the collector current of the fourth transistor Q4, the collector current of the sixth transistor Q6, the capacitance of the first capacitor C1, and the capacitance of the second capacitor C2.

[0036] Understandably, the above method can effectively adjust the delay of the normally open two-stage amplifier circuit.

[0037] In some embodiments, the normally open secondary amplifier circuit further includes: a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, and a fifth resistor R5; The emitter of the first transistor Q1 is grounded through the first resistor R1, the emitter of the fourth transistor Q4 is grounded through the fourth resistor R4, the emitter of the sixth transistor Q6 is grounded through the fifth resistor R5, the collector of the second transistor Q2 is connected to the power supply voltage through the second resistor R2, and the collector of the third transistor Q3 is connected to the power supply voltage through the third resistor R3. The first resistor R1, the fourth resistor R4, and the fifth resistor R5 are all used for current regulation, and the second resistor R2 and the third resistor R3 are both used for signal swing regulation.

[0038] It should be noted that by setting the first resistor R1, the fourth resistor R4, and the fifth resistor R5, the current can be easily adjusted by changing the resistance values. Similarly, by setting the second resistor R2 and the third resistor R3, the signal swing can be easily adjusted by changing the resistance values.

[0039] In some embodiments, the target amplifier circuit includes: an eighth transistor Q8, a ninth transistor Q9, a thirteenth transistor Q10, an eleventh transistor Q11, a twelfth transistor Q12, a thirteenth transistor Q13, a first switch, and a second switch; The first terminal of the first switch is connected to the first control terminal S1 of the current delay module. The second terminal of the first switch is connected to the base of the eighth transistor Q8. The emitter of the eighth transistor Q8 is grounded. The bases of the ninth transistor Q9 and the twelfth transistor Q12 are respectively connected to the positive terminal (Z0) of the first differential output. The bases of the thirteenth transistor Q10 and the thirteenth transistor Q13 are respectively connected to the negative terminal (ZN0) of the first differential output. The collectors of the thirteenth transistor Q10 and the thirteenth transistor Q13 are respectively connected to the positive terminal (Z1) of the second differential output. The collector of the ninth transistor Q9... The twelfth transistor Q12 is connected to the negative terminal (ZN1 terminal) of the second differential output, the emitter of the ninth transistor Q9 and the emitter of the thirteenth transistor Q10 are connected to the collector of the eighth transistor Q8, the first terminal of the second switch is connected to the second control terminal S2 of the current delay module, the second terminal of the second switch is connected to the base of the eleventh transistor Q11, the emitter of the eleventh transistor Q11 is grounded, and the collector of the eleventh transistor Q11 is connected to the emitter of the twelfth transistor Q12 and the emitter of the thirteenth transistor Q13, respectively. Both the first switch and the second switch are closed when a high level is received.

[0040] It should be noted that the above settings can effectively achieve a second delay of the signal after the first delay, and the controllability is relatively strong.

[0041] In some embodiments, the first switch includes: a first inverter INV1, a first NMOS (N-Metal-Oxide-Semiconductor) transistor NM1, and a second NMOS transistor NM2; the second switch includes: a second inverter INV2, a third NMOS transistor NM3, and a fourth NMOS transistor NM4. The input terminal of the first inverter INV1 is connected to the first control terminal S1 of the current delay module. The output terminal of the first inverter INV1 is connected to the gate of the second NMOS transistor NM2. The source of the second NMOS transistor NM2 is grounded. The drain of the second NMOS transistor NM2 is connected to the drain of the first NMOS transistor NM1 and the base of the eighth transistor Q8. The gate of the first NMOS transistor NM1 is connected to the first control terminal S1 of the current delay module. The source of the first NMOS transistor NM1 is connected to the reference voltage and the source of the third NMOS transistor NM3. The gate of the third NMOS transistor NM3 and the input terminal of the second inverter INV2 are connected to the second control terminal S2 of the current delay module. The output terminal of the second inverter INV2 is connected to the gate of the fourth NMOS transistor NM4. The source of the fourth NMOS transistor NM4 is grounded. The drain of the fourth NMOS transistor NM4 is connected to the drain of the third NMOS transistor NM3 and the base of the eleventh transistor Q11.

[0042] It should be noted that by adopting the above-mentioned switch structure, switch control can be easily achieved at a low cost.

[0043] In some embodiments, the delay of the target amplifier circuit is determined based on the control signal input to the first control terminal S1 and the control signal input to the second control terminal S2 of the delay module in which it is located, as well as the target current difference, wherein the target current difference is the difference between the collector current of the eighth transistor Q8 and the collector current of the eleventh transistor Q11.

[0044] In some examples of this embodiment, assuming that the collector current of the eighth transistor Q8 is Ic, the collector current of the eleventh transistor Q11 can be 2Ic, etc.

[0045] It should be noted that the above method can effectively control the delay of the target amplifier circuit.

[0046] In some embodiments, the target amplifier circuit further includes a sixth resistor R6 and a seventh resistor R7; The emitter of the eighth transistor Q8 is grounded through the sixth resistor R6, and the emitter of the eleventh transistor Q11 is grounded through the seventh resistor R7. Both the sixth resistor R6 and the seventh resistor R7 are adjustable resistors used for current regulation.

[0047] It should be noted that by setting the sixth resistor R6 and the seventh resistor R7, it is easy to adjust the collector current of the eighth transistor Q8 and the collector current of the eleventh transistor Q11.

[0048] Figure 3 For the transient curve of the differential output signal of the phase delay circuit when the delay setting signal D[m:0] is set to the range of 0~6 in one embodiment of this application, please refer to [link to relevant documentation]. Figure 3 , Figure 3 The input frequency is 2 GHz (gigahertz). Figure 3 The horizontal axis represents time, in nanoseconds (ns), and the vertical axis represents the amplitude of the differential output signal (OUTP-OUTN), in volts (V). Figure 3 The curves in the figure show that, at an input frequency of 2 GHz, the waveform of the differential output differential signal has uniform delay step characteristics without significant distortion.

[0049] Figure 4 For the characteristic curves of the delay step size and delay setting signal of the phase delay circuit in the temperature range of -55℃ to 125℃ provided in one embodiment of this application (n=9, number of delay modules = n+1, when n=9, the number of delay modules is 10), please refer to... Figure 4 , Figure 4 The horizontal axis in the figure represents the delay setting signal D[m:0] ( Figure 4 The abbreviation is D[m:0], where the vertical axis is the delay step size, and the unit is ps (picoseconds). Figure 4 The paper provides illustrative examples of the characteristic curves of the delay step size and delay setting signal for a phase delay circuit at temperatures of -55℃, 25℃, and 125℃. For example... Figure 4 As shown, the three characteristic curves cover a total of 24 delay steps. Each delay step is less than 25 ps in the temperature range of -55℃ to 125℃, and each delay step fluctuates by less than 4 ps with temperature.

[0050] Figure 5 In one embodiment of this application, a characteristic curve (n=9) of the total delay versus the delay setting signal for a phase delay circuit within a temperature range of -55℃ to 125℃ is provided. Please refer to... Figure 5 , Figure 5 The horizontal axis in the image represents the delay setting signal D[m:0]. Figure 5The abbreviation is D[m:0], where the vertical axis represents the total delay in ps. Figure 5 The paper provides illustrative examples of the total delay versus the characteristic curves of the delay setting signal for phase delay circuits at temperatures of -55℃, 25℃, and 125℃. Figure 5 As shown, the total delay of the phase delay machine circuit is linearly related to the delay setting signal within the temperature range of -55℃ to 125℃. When the delay setting signal D[m:0] is 24, the total delay is 617.2ps to 678ps.

[0051] based on Figures 3 to 5 The experimental results show that the phase delay circuit in the above embodiments has the characteristics of wide operating frequency range, high phase delay accuracy, good temperature characteristics, and scalable delay range. It can be used in systems such as high-precision clock generators, with low cost and strong feasibility.

[0052] This embodiment also provides a clock generator, including a phase delay circuit as described in any of the preceding embodiments. The clock generator in this embodiment achieves the technical effects of the phase delay circuit in the above embodiments, which will not be elaborated further here.

[0053] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.

Claims

1. A phase delay circuit, characterized in that, include: At least two delay modules are provided. Each delay module includes an input terminal, a first output terminal, a second output terminal, a first control terminal, and a second control terminal. The delay modules are cascaded together. The input terminal of the first cascaded delay module is connected to the signal to be delayed. The first output terminal is connected to the input terminal of the next stage delay module. The second output terminals of each delay module are connected in parallel and then connected to the output terminal of the phase delay circuit and the first terminal of a preset common load resistor. The second terminal of the common load resistor is connected to the power supply voltage. The delay setting module receives a delay setting signal and decodes the delay setting signal to obtain two multi-bit width control signals for controlling the delay amount of the delay module. The first control terminal and the second control terminal of the last cascaded delay module are both grounded. The first control terminal of the remaining delay modules are connected to the corresponding control bit in the first control signal, and the second control terminal is connected to the corresponding control bit in the second control signal.

2. The phase delay circuit according to claim 1, characterized in that, The delay module includes: A normally open two-stage amplifier circuit is connected to the signal to be delayed, and the signal to be delayed is delayed once to obtain a first delayed signal. The amount of the first delay is adjustable. The target amplifier circuit receives the first delayed signal and, based on the control signals received at its first and second control terminals, performs a second delay on the first delayed signal to obtain and output the second delayed signal.

3. The phase delay circuit according to claim 2, characterized in that, The signal to be delayed is a differential signal, which includes a first signal and a second signal with opposite polarities. The first output terminal includes a first differential output positive terminal and a first differential output negative terminal. The normally open two-stage amplifier circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, and a second capacitor. The bases of the first, fourth, and sixth transistors are all connected to a preset reference voltage. The emitters of the first, fourth, and sixth transistors are all grounded. The collector of the first transistor is connected to the emitters of the second and third transistors, respectively. The base of the second transistor is connected to the first signal input port of the current delay module, which is used to input the first signal. The base of the third transistor is connected to the second signal input port of the current delay module, which is used to input the second signal. The collector of the second transistor... The collector of the third transistor is connected to the power supply voltage, the first terminal of the first capacitor, and the base of the seventh transistor, respectively. The collector of the third transistor is connected to the power supply voltage, the first terminal of the first capacitor, and the base of the fifth transistor, respectively. The second terminal of the second capacitor and the second terminal of the first capacitor are grounded, respectively. The collectors of the fifth transistor and the seventh transistor are connected to the power supply voltage, respectively. The emitter of the fifth transistor is connected to the collector of the fourth transistor and the positive terminal of the first differential output of the current delay module, respectively. The emitter of the seventh transistor is connected to the collector of the sixth transistor and the negative terminal of the first differential output of the current delay module, respectively.

4. The phase delay circuit according to claim 3, characterized in that, The delay of the normally open secondary amplifier circuit can be adjusted by adjusting at least one of the collector current of the first transistor, the collector current of the fourth transistor, the collector current of the sixth transistor, the capacitance of the first capacitor, and the capacitance of the second capacitor.

5. The phase delay circuit according to claim 3 or 4, characterized in that, The normally open secondary amplifier circuit further includes: a first resistor, a second resistor, a third resistor, a fourth resistor, and a fifth resistor; The emitter of the first transistor is grounded through the first resistor, the emitter of the fourth transistor is grounded through the fourth resistor, the emitter of the sixth transistor is grounded through the fifth resistor, the collector of the second transistor is connected to the power supply voltage through the second resistor, and the collector of the third transistor is connected to the power supply voltage through the third resistor. The first resistor, the fourth resistor, and the fifth resistor are all used for current regulation, and the second resistor and the third resistor are both used for signal swing regulation.

6. The phase delay circuit according to claim 3, characterized in that, The second output terminal includes a second differential output positive terminal and a second differential output negative terminal. The target amplifier circuit includes: an eighth transistor, a ninth transistor, a thirteenth transistor, an eleventh transistor, a twelfth transistor, a thirteenth transistor, a first switch, and a second switch. The first terminal of the first switch is connected to the first control terminal of the current delay module, and the second terminal of the first switch is connected to the base of the eighth transistor. The emitter of the eighth transistor is grounded. The bases of the ninth transistor and the twelfth transistor are respectively connected to the positive terminal of the first differential output. The bases of the thirteenth transistor and the twelfth transistor are respectively connected to the negative terminal of the first differential output. The collectors of the thirteenth transistor and the twelfth transistor are respectively connected to the positive terminal of the second differential output. The collectors of the ninth transistor and the twelfth transistor are respectively connected to the positive terminal of the second differential output. The 12th transistor is connected to the negative terminal of the second differential output. The emitters of the 9th and 13th transistors are connected to the collectors of the 8th transistor. The first terminal of the second switch is connected to the second control terminal of the current delay module. The second terminal of the second switch is connected to the base of the 11th transistor. The emitter of the 11th transistor is grounded. The collector of the 11th transistor is connected to the emitters of the 12th and 13th transistors. Both the first and second switches close when a high level is received.

7. The phase delay circuit according to claim 6, characterized in that, The first switch includes: a first inverter, a first NMOS transistor, and a second NMOS transistor; the second switch includes: a second inverter, a third NMOS transistor, and a fourth NMOS transistor. The input terminal of the first inverter is connected to the first control terminal of the current delay module. The output terminal of the first inverter is connected to the gate of the second NMOS transistor. The source of the second NMOS transistor is grounded. The drain of the second NMOS transistor is connected to the drain of the first NMOS transistor and the base of the eighth transistor. The gate of the first NMOS transistor is connected to the first control terminal of the current delay module. The source of the first NMOS transistor is connected to the reference voltage and the source of the third NMOS transistor. The gate of the third NMOS transistor and the input terminal of the second inverter are connected to the second control terminal of the current delay module. The output terminal of the second inverter is connected to the gate of the fourth NMOS transistor. The source of the fourth NMOS transistor is grounded. The drain of the fourth NMOS transistor is connected to the drain of the third NMOS transistor and the base of the eleventh transistor.

8. The phase delay circuit according to claim 6, characterized in that, The delay of the target amplifier circuit is determined based on the control signal input to the first control terminal and the control signal input to the second control terminal of the delay module in which it is located, as well as the target current difference, which is the difference between the collector current of the eighth transistor and the collector current of the eleventh transistor.

9. The phase delay circuit according to any one of claims 6 to 8, characterized in that, The target amplifier circuit also includes a sixth resistor and a seventh resistor; The emitter of the eighth transistor is grounded through the sixth resistor, and the emitter of the eleventh transistor is grounded through the seventh resistor. Both the sixth and seventh resistors are adjustable resistors used for current regulation.

10. A clock generator, characterized in that, include: The phase delay circuit as described in any one of claims 1 to 9.

Images