A silicon carbide superjunction MOSFET device

Abstract

This invention discloses a silicon carbide superjunction MOSFET device in the field of semiconductor power device technology, comprising an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, and an oxide dielectric layer. A drain electrode is disposed below the N-type substrate. The first N-type epitaxial layer is grown above the N-type substrate, with a P-pillar region formed by doping at the center of the first N-type epitaxial layer and symmetrical P-type regions formed on both sides of the first N-type epitaxial layer. The second N-type epitaxial layer is grown above the first N-type epitaxial layer, with a gate trench oxide located in the middle of the second N-type epitaxial layer. This invention reduces the device saturation current and improves the device's short-circuit withstand capability by forming floating or short-circuited P-type regions on both sides of the doped P-pillar region. This is beneficial to the long-term reliability of the gate oxide dielectric and the device, avoids thermal runaway caused by device temperature rise, and effectively reduces the risk of device short-circuit failure.

Description

Technical Field

[0001] This invention relates to the field of semiconductor power device technology, specifically a silicon carbide superjunction MOSFET device. Background Technology

[0002] As core components of power conversion systems, the performance of power semiconductor devices directly determines energy conversion efficiency, system size, and cost. In recent years, third-generation wide-bandgap semiconductors, represented by silicon carbide (SiC), have gradually become a research hotspot in power devices due to their superior material properties. Compared with traditional silicon (Si) materials, silicon carbide has a higher critical breakdown electric field, a wider bandgap, and higher thermal conductivity. These characteristics enable silicon carbide devices to operate at higher voltages, higher frequencies, and higher temperatures while achieving lower power losses.

[0003] However, with the increasing demands for power density and efficiency in power electronic systems, the inherent contradiction between the on-resistance (Rds(on)) and blocking voltage (BV) of traditional silicon carbide devices means that their performance can no longer meet current application requirements. Especially in medium- and high-voltage applications such as traction inverters for new energy vehicles, photovoltaics, energy storage, smart grids, and rail transit, how to further reduce device conduction losses while maintaining high blocking voltage has become a key challenge for technological development.

[0004] To overcome this limitation, a superjunction structure can be introduced into traditional silicon carbide devices. The alternating P-pillars and N-pillars in the drift region can completely deplete each other in the blocking state, forming an approximately rectangular electric field distribution, significantly improving the device's breakdown voltage. Simultaneously, in the conducting state, current can flow through the highly doped N-pillar region, reducing the device's on-resistance, thus breaking through the theoretical limits of silicon carbide materials. However, the introduction of the superjunction structure also brings related reliability issues to silicon carbide devices. On the one hand, for trench silicon carbide MOSFETs, the introduction of the superjunction structure introduces a transverse electric field within the device. This field, combined with the longitudinal electric field, enhances the electric field at the trench corners and bottom, which is detrimental to the long-term reliability of the gate oxide and the device. On the other hand, while reducing on-resistance, silicon carbide superjunction devices also present new challenges to short-circuit reliability under high bus voltages. The root of this challenge lies in the high internal electric field and large current. In silicon carbide superjunction devices, the current is confined within the narrow N-pillar channel, resulting in extremely high current density. Furthermore, the electric field at the bottom of the P-pillar is highly concentrated. The simultaneous presence of extremely high current density and electric field strength creates a heat source within the device, causing the device temperature to rise until thermal runaway occurs. The deeper the pillar region, the greater the electric field strength at the bottom, and the higher the risk of short-circuit failure. Summary of the Invention

[0005] The purpose of this invention is to provide a silicon carbide superjunction MOSFET device, which reduces the device saturation current and improves the device's short-circuit withstand capability by forming floating or short-circuited P-type regions on both sides of the doped P-pillar region. This is beneficial to the long-term reliability of the gate oxide dielectric and the device, avoids thermal runaway caused by device temperature rise, and thus effectively reduces the risk of device short-circuit failure.

[0006] To achieve the above objectives, the present invention provides the following technical solution:

[0007] A silicon carbide superjunction MOSFET device includes an N-type substrate, a first N-type epitaxial layer, a second N-type epitaxial layer, and an oxide dielectric layer. The second N-type epitaxial layer, the P-body region, the N+ source region, and the P+ contact region constitute a selective P-type semi-enclosed structure. By setting the selective P-type semi-enclosed structure, the doped P-pillar region at the bottom of the trench is shorted to the source. On the one hand, the selective semi-enclosed short-circuit structure can further increase the effective conduction area of ​​the device and reduce the on-resistance; on the other hand, the semi-enclosed short-circuit region short-circuits the doped P-pillar region to the source, which can convert most of the gate-drain capacitance (i.e., Miller capacitance) of the device into drain-source capacitance, thereby improving the switching speed and reducing switching losses. A drain electrode is set below the N-type substrate. The first N-type epitaxial layer is grown on top of the N-type substrate. A P-pillar region is formed by doping in the center of the first N-type epitaxial layer, and symmetrical P-type regions are formed on both sides of the first N-type epitaxial layer. By forming floating or short-circuited P-type regions on both sides of the doped P-pillar region, the saturation current of the device is reduced and the short-circuit current of the device is improved. Endurance: The second N-type epitaxial layer is grown above the first N-type epitaxial layer. A gate trench oxide is located in the middle of the second N-type epitaxial layer, simultaneously above the doped P-pillar region. A P-body region is formed on the trench side of the gate trench oxide. By placing the P-pillars below the trench, the arrangement of the P-pillars and N-pillars is optimized. On the one hand, this effectively shields the influence of the superposition of the lateral electric field introduced by the superjunction and the longitudinal electric field of the device on the bottom of the trench, suppressing the electric field at the bottom of the trench to a low level and improving the gate oxide reliability of the device. On the other hand, the device cell size can be made extremely small with the current process capability, significantly reducing the on-resistance of the device while maintaining a high blocking voltage. An N+ source region is formed above the P-body region, and a P+ contact region is formed on the side of the N+ source region. The interior of the gate trench oxide is etched to form a polysilicon gate. An oxide dielectric layer is formed above the polysilicon gate, and a source electrode is disposed above the oxide dielectric layer. The P+ contact region and the N+ source region are shorted through the source electrode.

[0008] As a further aspect of the present invention, the method for forming the doped P-pillar region includes multiple epitaxy and multiple ion implantation, or trench filling.

[0009] As a further aspect of the present invention: the P-type region is located on both sides of the top of the first N-type epitaxial layer, and the doping concentration of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer. By setting a floating P-type region in the superjunction structure, the local conduction current of the device can be limited to a narrow region, thereby reducing the device saturation current and improving the device's short-circuit withstand capability.

[0010] As a further aspect of the present invention: the P-type region and the doped P-pillar region are respectively shorted to the source electrode through the P+ contact region. The P+ contact region is located above the P-type region, and the P-body region is located above the second N-type epitaxial layer. Since the P-type regions on both sides of the doped P-pillar region are not shorted to the source electrode, the depletion region between the P-type region and the doped P-pillar region is not easily pinched off. This is beneficial to reduce the device cell size to the smallest possible value to optimize the figure of merit (FOM) of the blocking voltage and on-resistance, further improving device performance. It can effectively suppress the electric field strength at the bottom of the device trench, reduce the device Miller capacitance, improve the device switching speed, reduce the device switching loss, reduce the device saturation current, and enhance the device short-circuit withstand capability.

[0011] As a further aspect of the present invention: the P+ contact region is located above the second N-type epitaxial layer.

[0012] As a further aspect of the present invention: the P-type region is located on the side of the first N-type epitaxial layer. The P-type region includes a first P-type region and a second P-type region. By adjusting the position of the short-circuited or floating P-type region, it is beneficial to improve the figure of merit (FOM) between the device breakdown voltage and on-resistance, thereby enhancing the device performance and enabling the proposed silicon carbide superjunction device to simultaneously possess high performance and high reliability.

[0013] As a further aspect of the present invention: the first P-type region is located on the top surface of the first N-type epitaxial layer, and the second P-type region is located at the center of the side surface of the first N-type epitaxial layer. The doped P-pillar region is shorted to the source electrode through a selective P-type semi-enclosed structure. As a further aspect of the present invention: the P-type region is located on both sides of the top of the doped P-pillar region. By moving the floating P-type regions on both sides of the doped P-pillar region to the center of the superjunction structure, the P-type region no longer affects the expansion of the conduction current. This is beneficial to reduce the resistance of the device expansion region, further optimize the figure of merit (FOM) of the device blocking voltage and conduction resistance, and improve device performance. This can further provide a feasible technical path for silicon carbide superjunction devices. Since the deeper the device pillar region, the greater the bottom electric field strength and the worse the short-circuit withstand capability of the device, a bottom auxiliary layer can be added above the N-type substrate of the device to form a semi-superjunction structure, thereby reducing the difficulty and cost of device manufacturing process and further improving the reliability of the device.

[0014] As a further aspect of the present invention, the doped P-pillar region is shorted to the source electrode through a selective P-type semi-enclosed structure.

[0015] As a further aspect of the present invention: the second P-type region is located on both sides of the center of the doped P-pillar region, connecting the P-type region with the doped P-pillar region. On the one hand, this can better suppress the electric field strength at the bottom of the device trench, improve the long-term reliability of the gate oxide dielectric and the device. On the other hand, after the device is turned on, the current needs to flow through the P-body and the P-type region as well as the narrow area between the two P-type regions, which can minimize the device saturation current and improve the device's short-circuit withstand capability.

[0016] As a further aspect of the present invention, the silicon carbide MOSFET device has a superjunction structure, which can provide a feasible technical path for the commercial application of silicon carbide superjunction devices.

[0017] As a further aspect of the present invention, a bottom auxiliary layer is added above the N-type substrate of the device to form a semi-superjunction structure, which can reduce the risk of premature breakdown due to increased on-resistance in the drift region. At the same time, the deeper the device pillar region, the greater the bottom electric field strength, and the worse the short-circuit withstand capability of the device. Therefore, the manufacturing process difficulty and cost of the device can be further reduced, and the reliability of the device can be improved.

[0018] As a further aspect of the present invention, the P-type region connected to the P-pillar region is moved to the center of the superjunction structure, which eliminates the narrow region of the P-body and the P-type region, reduces the on-resistance of the device, and also reduces the Miller capacitance of the device, increases the switching speed of the device, reduces the switching loss of the device, reduces the saturation current of the device, and enhances the short-circuit withstand capability of the device.

[0019] Compared with the prior art, the beneficial effects of the present invention are:

[0020] 1. This invention optimizes the arrangement of P-pillars and N-pillars, placing the P-pillars below the trench. On the one hand, this effectively shields the superposition of the transverse electric field introduced by the superjunction and the longitudinal electric field of the device on the bottom of the trench, suppressing the electric field at the bottom of the trench to a low level and improving the gate oxide reliability of the device. On the other hand, the device cell size can be made extremely small with the current process capability, significantly reducing the on-resistance of the device while maintaining a high blocking voltage.

[0021] 2. This invention sets up a selective P-type semi-enclosed structure to short-circuit the doped P-pillar region at the bottom of the trench with the source. On the one hand, the selective semi-enclosed short-circuit structure can further increase the effective conduction area of ​​the device and reduce the on-resistance of the device. On the other hand, the semi-enclosed short-circuit region short-circuits the doped P-pillar region with the source, which can convert most of the gate-drain capacitance (i.e., Miller capacitance) of the device into drain-source capacitance, thereby improving the switching speed of the device and reducing switching losses.

[0022] 3. This invention limits the local on-current of the device to a narrow area by setting a short-circuited or floating P-type region in the superjunction structure, thereby reducing the saturation current of the device and improving the short-circuit withstand capability of the device. Furthermore, by adjusting the position of the short-circuited or floating P-type region, the figure of merit (FOM) between the breakdown voltage and on-resistance of the device is improved, thereby enhancing the device performance. As a result, the proposed silicon carbide superjunction device has both high performance and high reliability.

[0023] 4. By moving the P-type region connected to the P-pillar region to the center of the superjunction structure, this invention eliminates the narrow regions of the P-body and P-type region, reduces the on-resistance of the device, and also reduces the Miller capacitance of the device. This can effectively improve the switching speed of the device, reduce the switching loss of the device, reduce the saturation current of the device, and enhance the short-circuit withstand capability of the device.

[0024] 5. This invention addresses the shortcomings of silicon carbide superjunction MOSFETs in terms of device performance, structural design, and reliability by innovatively proposing a high-performance, high-reliability silicon carbide MOSFET device with a superjunction structure, providing a feasible technical path for the commercial application of silicon carbide superjunction devices. Attached Figure Description

[0025] Figure 1A This is a schematic diagram of the cell structure of Embodiment 1 of the present invention;

[0026] Figure 1B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure of Embodiment 1 of the present invention;

[0027] Figure 2A This is a schematic diagram of the cell structure of Embodiment 2 of the present invention;

[0028] Figure 2B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure in Embodiment 2 of the present invention;

[0029] Figure 3A This is a schematic diagram of the cell structure of Embodiment 3 of the present invention;

[0030] Figure 3B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure in Embodiment 3 of the present invention;

[0031] Figure 4A This is a schematic diagram of the cell structure of Embodiment 4 of the present invention;

[0032] Figure 4B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure in Embodiment 4 of the present invention;

[0033] Figure 5A This is a schematic diagram of the cell structure of Embodiment 5 of the present invention;

[0034] Figure 5B This is a schematic diagram of the P-type semi-enclosed short-circuit region structure in Embodiment 5 of the present invention.

[0035] In the figure: 101, N-type substrate; 102, first N-type epitaxial layer; 103, doped P-pillar region; 104, P-type region; 1041, first P-type region; 1042, second P-type region; 105, second N-type epitaxial layer; 106, P-body region; 107, N+ source region; 108, P+ contact region; 109, gate trench oxide; 110, polysilicon gate; 111, oxide dielectric layer; 112, source electrode; 113, drain electrode. Detailed Implementation

[0036] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0037] Example 1:

[0038] Please see Figures 1A-1B This invention provides a high-performance, high-reliability silicon carbide MOSFET device with a short-circuited P-type region, comprising an N-type substrate 101, a first N-type epitaxial layer 102, a second N-type epitaxial layer 105, and an oxide dielectric layer 111. The second N-type epitaxial layer 105, the P-body region 106, the N+ source region 107, and the P+ contact region 108 constitute a selective P-type semi-enclosed structure. A drain electrode 113 is disposed below the N-type substrate 101. The first N-type epitaxial layer 102 is grown above the N-type substrate 101, and a doped P-pillar region 103 is formed at the center of the first N-type epitaxial layer 102. The formation method of the doped P-pillar region 103 includes multiple epitaxy and multiple ion implantation, or trench filling.

[0039] Symmetrical P-type regions 104 are formed on both sides of the first N-type epitaxial layer 102. The P-type regions 104 are located on the top two sides of the first N-type epitaxial layer 102. The doping concentration of the second N-type epitaxial layer 105 is higher than that of the first N-type epitaxial layer 102. The second N-type epitaxial layer 105 is grown above the first N-type epitaxial layer 102. A gate trench oxide 109 is disposed in the middle of the second N-type epitaxial layer 105 and is located above the doped P-pillar region 103. A P-body region 106 is formed on the trench side of the gate trench oxide 109. An N+ source region 107 is formed above the P-body region 106. A P+ contact region 108 is formed on the side of the N+ source region 107. A polysilicon gate 110 is formed by etching inside the gate trench oxide 109.

[0040] An oxide dielectric layer 111 is formed above the polysilicon gate 110. A source electrode 112 is disposed above the oxide dielectric layer 111. The P+ contact region 108 and the N+ source region 107 are shorted through the source electrode 112. The P-type region 104 and the doped P-pillar region 103 are shorted to the source electrode 112 through the P+ contact region 108. The P+ contact region 108 is located above the P-type region 104. The P-body region 106 is located above the second N-type epitaxial layer 105. By optimizing the arrangement of the P-pillars and N-pillars, the P-pillars are placed below the trench and shorted to the source through a selective semi-enclosed structure. This effectively suppresses the electric field at the bottom of the trench, significantly reduces the on-resistance of the device while maintaining a high blocking voltage, and simultaneously reduces the gate-drain capacitance of the device. This effectively improves the switching speed of the device, reduces the switching loss of the device, and improves the reliability of the device.

[0041] The second N-type epitaxial layer 105 has a higher doping concentration to further optimize the on-resistance of the top cell. In this embodiment, the N-type substrate 101, the first N-type epitaxial layer 102, the second N-type epitaxial layer 105, the P-body region 106, the N+ source region 107, the source electrode 112, and the drain electrode 113 are used for conduction.

[0042] This embodiment effectively suppresses the electric field strength at the bottom of the trench by placing the P-pillars in the superjunction structure below the trench. Simultaneously, this structure minimizes the cell size of the trench superjunction silicon carbide, significantly reducing the on-resistance while maintaining a high blocking voltage. Furthermore, the selective P-type semi-enclosed structure shorts the doped P-pillar region to the source, converting most of the gate-drain capacitance into drain-source capacitance, reducing Miller capacitance, increasing switching speed, and decreasing switching losses. On the other hand, by placing P-type regions on both sides of the doped P-pillar region and shorting them to the source via P+ contacts, the current after the device is turned on is compressed into an extremely narrow region by the P-type and doped P-pillar regions, thereby reducing the saturation current and enhancing the short-circuit withstand capability. The high-performance, high-reliability silicon carbide MOSFET device with a superjunction structure proposed in this invention provides a feasible technical path for the commercial application of silicon carbide superjunction devices. Manufacturing a full superjunction structure for silicon carbide MOSFET high-voltage devices, which spans the entire drift region, is challenging and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing on-resistance and increasing the risk of premature breakdown. Additionally, the deeper the device pillar, the stronger the bottom electric field, leading to poorer short-circuit withstand capability. Therefore, adding a bottom auxiliary layer above the N-type substrate 101 to form a semi-superjunction structure can reduce manufacturing difficulty and cost, and further improve device reliability.

[0043] Example 2:

[0044] In the first type of silicon carbide superjunction device described above, the P-type regions on both sides of the P-pillar region are shorted to the source via P+ contact regions. This significantly limits the reduction of device cell size. At small sizes, the depletion regions between the P-type and P-pillar regions are pinched off, making it difficult for the device to conduct. To address this problem, this invention provides a second type of silicon carbide superjunction device structure:

[0045] like Figure 2A-2B As shown, a high-performance, high-reliability silicon carbide MOSFET device with a top-floating P-type region includes an N-type substrate 101, a first N-type epitaxial layer 102, a second N-type epitaxial layer 105, and an oxide dielectric layer 111. The second N-type epitaxial layer 105, the P-body region 106, the N+ source region 107, and the P+ contact region 108 constitute a selective P-type semi-enclosed structure. A drain electrode 113 is disposed below the N-type substrate 101. The first N-type epitaxial layer 102 is grown above the N-type substrate 101. A doped P-pillar region 103 is formed at the center of the first N-type epitaxial layer 102, and symmetrical P-type regions 104 are formed on both sides of the first N-type epitaxial layer 102. The second N-type epitaxial layer 105 is grown from the first N-type epitaxial layer 102. Above the second N-type epitaxial layer 105, a gate trench oxide 109 is disposed in the middle and simultaneously located above the doped P-pillar region 103. A P-body region 106 is formed on the trench side of the gate trench oxide 109, an N+ source region 107 is formed above the P-body region 106, and a P+ contact region 108 is formed on the side of the N+ source region 107. The P+ contact region 108 is located above the second N-type epitaxial layer 105. A polysilicon gate 110 is formed by etching inside the gate trench oxide 109. An oxide dielectric layer 111 is formed above the polysilicon gate 110, and a source electrode 112 is disposed above the oxide dielectric layer 111. The P+ contact region 108 and the N+ source region 107 are shorted through the source electrode 112.

[0046] Compared to the structure of Embodiment 1, the P-type regions on both sides of the doped P-pillar region in Embodiment 2 of this invention are not short-circuited to the source electrode. Therefore, the depletion region between the P-type region and the doped P-pillar region is less likely to be pinched off. This is beneficial for minimizing the device cell size to optimize the figure of merit (FOM) of the blocking voltage and on-resistance, further improving device performance. Simultaneously, the structure of Embodiment 2 also possesses the same advantages as the structure of Embodiment 1, namely, effectively suppressing the electric field strength at the bottom of the device trench, reducing the device Miller capacitance, increasing the device switching speed, reducing the device switching losses, reducing the device saturation current, and enhancing the device's short-circuit withstand capability.

[0047] The high-performance, high-reliability silicon carbide MOSFET device with a floating P-type region proposed in this invention can provide a feasible technical path for the commercial application of silicon carbide superjunction devices. However, the manufacturing process of a full superjunction structure for high-voltage silicon carbide MOSFETs spanning the entire drift region is difficult and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing the device's on-resistance and increasing the risk of premature breakdown. Additionally, the deeper the device pillar region, the greater the bottom electric field strength, and the worse the device's short-circuit withstand capability. Therefore, a bottom auxiliary layer can be added above the N-type substrate 101 to form a semi-superjunction structure, reducing the difficulty and cost of device manufacturing and further improving device reliability.

[0048] Example 3:

[0049] In the silicon carbide superjunction device of Embodiment 2 above, the P-type region is located at the top of the superjunction structure. After the device is turned on, the P-type region restricts the current from spreading to the N-pillar region, resulting in a large current spread region resistance. To reduce the current spread region resistance in the second type of silicon carbide superjunction device, this invention provides a third type of silicon carbide superjunction device structure:

[0050] like Figures 3A-3B As shown, a high-performance, high-reliability silicon carbide MOSFET device with a central floating P-type region is disclosed, including an N-type substrate 101, a first N-type epitaxial layer 102, a second N-type epitaxial layer 105, and an oxide dielectric layer 111. The second N-type epitaxial layer 105, the P-body region 106, the N+ source region 107, and the P+ contact region 108 constitute a selective P-type semi-enclosed structure. A drain electrode 113 is disposed below the N-type substrate 101. The first N-type epitaxial layer 102 is grown above the N-type substrate 101. A doped P-pillar region 103 is formed at the center of the first N-type epitaxial layer 102. Symmetrical P-type regions 104 are formed on both sides of the first N-type epitaxial layer 102. The P-type regions 104 are located on the sides of the first N-type epitaxial layer 102. The P-type regions 104 include a first P-type region 1041 and a second P-type region 1042.

[0051] The first P-type region 1041 is located on the top surface of the first N-type epitaxial layer 102, and the second P-type region 1042 is located at the center of the side surface of the first N-type epitaxial layer 102. The doped P-pillar region 103 is shorted to the source electrode 112 through a selective P-type half-enclosure structure. The second N-type epitaxial layer 105 is grown above the first N-type epitaxial layer 102. A gate trench oxide 109 is disposed in the middle of the second N-type epitaxial layer 105 and is also located above the doped P-pillar region 103. A P-body region 106 is formed on the trench side of 9, an N+ source region 107 is formed above the P-body region 106, a P+ contact region 108 is formed on the side of the N+ source region 107, and a polysilicon gate 110 is formed by etching inside the gate trench oxide 109; an oxide dielectric layer 111 is formed above the polysilicon gate 110, and a source electrode 112 is disposed above the oxide dielectric layer 111. The P+ contact region 108 and the N+ source region 107 are shorted through the source electrode 112.

[0052] Compared to the structure of Example 2, the structure of Embodiment 3 proposed in this invention moves the floating P-type regions on both sides of the doped P-pillar region to the center of the superjunction structure. Therefore, the P-type regions no longer affect the expansion of the conduction current, which helps reduce the resistance of the device's expansion region, further optimizes the figure of merit (FOM) of the device's blocking voltage and on-resistance, and improves device performance. Simultaneously, the structure of Embodiment 3 also shares the same advantages as the structures of Examples 1 and 2, namely, effectively suppressing the electric field strength at the bottom of the device trench, reducing the device's Miller capacitance, improving the device's switching speed, reducing the device's switching losses, reducing the device's saturation current, and enhancing the device's short-circuit withstand capability. The high-performance, high-reliability silicon carbide MOSFET device with a central floating P-type region proposed in this invention can provide a feasible technical path for the commercial application of silicon carbide superjunction devices. Similarly, the manufacturing process of a full superjunction structure for silicon carbide MOSFET high-voltage devices that spans the entire drift region is difficult and costly, and substrate defects can extend into the epitaxially grown drift region, posing a risk of increased on-resistance and premature breakdown. Furthermore, the deeper the pillar region of the device, the greater the electric field strength at the bottom, and the worse the short-circuit withstand capability of the device. Therefore, a bottom auxiliary layer can be added above the N-type substrate of the device to form a semi-superjunction structure, thereby reducing the difficulty and cost of device manufacturing process and further improving the reliability of the device.

[0053] Example 4:

[0054] In the silicon carbide superjunction device of Embodiment 1 above, the P-type region is shorted to the source electrode through the P+ contact region. Following the same working principle, the P-type region can be connected to the P-pillar region, and then shorted to the source electrode through a P-type semi-enclosed structure. Therefore, this invention provides a fourth silicon carbide superjunction device structure:

[0055] like Figures 4A-4BAs shown, a high-performance, high-reliability silicon carbide MOSFET device with a top-protruding P-pillar region includes an N-type substrate 101, a first N-type epitaxial layer 102, a second N-type epitaxial layer 105, and an oxide dielectric layer 111. The second N-type epitaxial layer 105, a P-body region 106, an N+ source region 107, and a P+ contact region 108 constitute a selective P-type semi-enclosed structure. A drain electrode 113 is disposed below the N-type substrate 101. The first N-type epitaxial layer 102 is grown above the N-type substrate 101. A doped P-pillar region 103 is formed at the center of the first N-type epitaxial layer 102, and symmetrical P-type regions 104 are formed on both sides of the first N-type epitaxial layer 102. The P-type regions 104 are located on both sides of the top of the doped P-pillar region 103. The second N-type epitaxial layer 105 is grown on the first N-type substrate 101, a first N-type epitaxial layer 102, a second N-type epitaxial layer 105, and an oxide dielectric layer 111. Above an N-type epitaxial layer 102, a gate trench oxide 109 is disposed in the middle of a second N-type epitaxial layer 105, which is also located above a doped P-pillar region 103. A P-body region 106 is formed on the trench side of the gate trench oxide 109, an N+ source region 107 is formed above the P-body region 106, and a P+ contact region 108 is formed on the side of the N+ source region 107. A polysilicon gate 110 is formed by etching inside the gate trench oxide 109. An oxide dielectric layer 111 is formed above the polysilicon gate 110, and a source electrode 112 is disposed above the oxide dielectric layer 111. The P+ contact region 108 and the N+ source region 107 are shorted through the source electrode 112, and the doped P-pillar region 103 is shorted to the source electrode 112 through a selective P-type half-enclosed structure.

[0056] Compared to the structure of Example 1, the structure of Embodiment 4 proposed in this invention connects the P-type region with the doped P-pillar region. This better suppresses the electric field strength at the bottom of the device trench, improving the long-term reliability of the gate oxide and the device. Furthermore, since the current needs to flow through the P-body, the P-type region, and the narrow region between the two P-type regions after the device is turned on, this minimizes the device's saturation current and enhances its short-circuit withstand capability. Simultaneously, the structure of Embodiment 4 also reduces the device's Miller capacitance, increases the device's switching speed, reduces switching losses, reduces saturation current, and enhances its short-circuit withstand capability. The high-performance, high-reliability silicon carbide MOSFET device with a top-protruding doped P-pillar region proposed in this invention can provide a feasible technical path for the commercial application of silicon carbide superjunction devices. Similarly, the manufacturing process of a full superjunction structure for silicon carbide MOSFET high-voltage devices that spans the entire drift region is difficult and costly. Substrate defects can extend into the epitaxially grown drift region, increasing the device's on-resistance and posing a risk of premature breakdown. Furthermore, the deeper the pillar region of the device, the greater the electric field strength at the bottom, and the worse the short-circuit withstand capability of the device. Therefore, a bottom auxiliary layer can be added above the N-type substrate of the device to form a semi-superjunction structure, thereby reducing the difficulty and cost of device manufacturing process and further improving the reliability of the device.

[0057] Example 5:

[0058] In the silicon carbide superjunction device of Embodiment 4 above, the P-type region connected to the P-pillar region is located at the top of the superjunction structure and is shorted to the source electrode through a P-type semi-enclosed structure. After the device is turned on, the current flows through the P-body, the P-type region, and the narrow region between the two P-type regions. Although this can minimize the device's saturation current and improve its short-circuit withstand capability, it also increases the device's on-resistance. To solve the above problems, this invention provides a fifth silicon carbide superjunction device structure:

[0059] like Figures 5A-5B As shown, a high-performance, high-reliability silicon carbide MOSFET device with a centrally protruding P-pillar region includes an N-type substrate 101, a first N-type epitaxial layer 102, a second N-type epitaxial layer 105, and an oxide dielectric layer 111. The second N-type epitaxial layer 105, the P-body region 106, the N+ source region 107, and the P+ contact region 108 constitute a selective P-type semi-enclosed structure. A drain electrode 113 is disposed below the N-type substrate 101. The first N-type epitaxial layer 102 is grown above the N-type substrate 101. A doped P-pillar region 103 is formed at the center of the first N-type epitaxial layer 102. Symmetrical P-type regions 104 are formed on both sides of the first N-type epitaxial layer 102. The P-type regions 104 are located on the sides of the first N-type epitaxial layer 102. The P-type regions 104 include a first P-type region 1041 and a second P-type region 1042.

[0060] The second P-type region 1042 is located on both sides of the center of the doped P-pillar region 103. The second N-type epitaxial layer 105 is grown above the first N-type epitaxial layer 102. A gate trench oxide 109 is disposed in the middle of the second N-type epitaxial layer 105 and is also located above the doped P-pillar region 103. A P-body region 106 is formed on the trench side of the gate trench oxide 109. An N+ source region 107 is formed above the P-body region 106. A P+ contact region 108 is formed on the side of the N+ source region 107. A polysilicon gate 110 is formed by etching inside the gate trench oxide 109. An oxide dielectric layer 111 is formed above the polysilicon gate 110. A source electrode 112 is disposed above the oxide dielectric layer 111. The P+ contact region 108 and the N+ source region 107 are shorted through the source electrode 112.

[0061] Compared to the structure of Embodiment 4, the structure of Embodiment 5 proposed in this invention moves the P-type region connected to the P-pillar region to the center of the superjunction structure, eliminating the narrow regions of the P-body and P-type intervals and reducing the on-resistance of the device. Simultaneously, the structure of Embodiment 5 also reduces the Miller capacitance, improves the switching speed, reduces switching losses, reduces saturation current, and enhances short-circuit withstand capability. The high-performance, high-reliability silicon carbide MOSFET device with a centrally protruding P-pillar region proposed in this invention can provide a feasible technical path for the commercial application of silicon carbide superjunction devices. Similarly, the manufacturing process of a full superjunction structure for high-voltage silicon carbide MOSFETs spanning the entire drift region is difficult and costly. Furthermore, substrate defects can extend into the epitaxially grown drift region, increasing the on-resistance and increasing the risk of premature breakdown. The deeper the pillar region, the greater the bottom electric field strength, and the worse the short-circuit withstand capability. Therefore, a bottom auxiliary layer can be added to the N-type substrate to form a semi-superjunction structure, reducing the manufacturing process difficulty and cost, and further improving the device's reliability.

[0062] The above are merely preferred embodiments of the present invention, but the scope of protection of the present invention is not limited thereto. Any equivalent substitutions or modifications made by those skilled in the art within the scope of the technology disclosed in the present invention, based on the technical solution and inventive concept of the present invention, should be covered within the scope of protection of the present invention.

Claims

1. A silicon carbide superjunction MOSFET device, characterized in that... ,include: An N-type substrate is used, with a drain electrode disposed beneath the N-type substrate. The first N-type epitaxial layer is grown on top of the N-type substrate. A P-pillar region is formed in the center of the first N-type epitaxial layer, and symmetrical P-type regions are formed on both sides of the first N-type epitaxial layer. The second N-type epitaxial layer is grown above the first N-type epitaxial layer. A gate trench oxide is disposed in the middle of the second N-type epitaxial layer and is located above the doped P-pillar region. A P-body region is formed on the trench side of the gate trench oxide. An N+ source region is formed above the P-body region. A P+ contact region is formed on the side of the N+ source region. A polysilicon gate is formed by etching inside the gate trench oxide. An oxide dielectric layer is formed above the polysilicon gate, and a source electrode is disposed above the oxide dielectric layer. The P+ contact region and the N+ source region are shorted through the source electrode. The second N-type epitaxial layer, the P-body region, the N+ source region, and the P+ contact region constitute a selective P-type semi-enclosed structure.

2. The silicon carbide superjunction MOSFET device according to claim 1, characterized in that: Methods for forming doped P-pillar regions include multiple epitaxial growths and multiple ion implantations, or trench filling.

3. The silicon carbide superjunction MOSFET device according to claim 2, characterized in that: The P-type regions are located on both sides of the top of the first N-type epitaxial layer, and the doping concentration of the second N-type epitaxial layer is higher than that of the first N-type epitaxial layer.

4. The silicon carbide superjunction MOSFET device according to claim 3, characterized in that: The P-type region and the doped P-body region are shorted to the source electrode through the P+ contact region. The P+ contact region is located above the P-type region, and the P-body region is located above the second N-type epitaxial layer.

5. The silicon carbide superjunction MOSFET device according to claim 3, characterized in that: The P+ contact region is located above the second N-type epitaxial layer.

6. The silicon carbide superjunction MOSFET device according to claim 3, characterized in that: The P-type region is located on the side of the first N-type epitaxial layer, and the P-type region includes the first P-type region and the second P-type region.

7. The silicon carbide superjunction MOSFET device according to claim 6, characterized in that: The first P-type region is located on the top surface of the first N-type epitaxial layer, and the second P-type region is located at the center of the side surface of the first N-type epitaxial layer. The doped P-pillar region is shorted to the source electrode through a selective P-type semi-enclosed structure.

8. The silicon carbide superjunction MOSFET device according to claim 7, characterized in that: The P-type regions are located on both sides of the top of the doped P-pillar region.

9. The silicon carbide superjunction MOSFET device according to claim 3, characterized in that: The doped P-pillar region is shorted to the source electrode through a selective P-type semi-enclosed structure.

10. The silicon carbide superjunction MOSFET device according to claim 6, characterized in that: The second P-type region is located on both sides of the center of the doped P-pillar region.

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