Improved UVID TOPCon cell fabrication method and TOPCon cell

Abstract

This application relates to a method for fabricating a TOPCon cell with improved UVID and the TOPCon cell itself. The method involves depositing a first tunneling oxide layer and a barrier polycrystalline silicon layer on the back side of a treated silicon substrate, followed by depositing a second tunneling oxide layer and a doped polycrystalline silicon layer on the deposited barrier polycrystalline silicon layer. A silicon dioxide masking film is formed on the back side of the silicon substrate, and backside phosphorus diffusion is performed. Atomic layer deposition is performed on the front side of the silicon substrate to form an aluminum oxide layer, which is then passivated. PECVD deposition is performed on both the front and back sides of the silicon substrate to form thin films, which are then passivated. Main and sub-gate lines are screen-printed on the front and back sides of the silicon substrate, respectively. The thin film on the front side comprises a seven-layer structure stacked sequentially. By optimizing the refractive index of the silicon nitride layer and adjusting the formation of Si-H covalent bonds, the light absorption capacity is reduced, resulting in a significant improvement in UVID and a reduction in the UVID amplitude of the TOPCon cell.

Description

Technical Field

[0001] This application relates to the field of battery fabrication technology, and in particular to a method for fabricating TOPCon batteries with improved UVID and TOPCon batteries. Background Technology

[0002] TOPCon (Tunnel Oxide Passivated Contact) cells, due to the lack of a thick silicon oxide layer on the front side, have relatively weak UV light blocking capabilities. After exposure to sunlight, UVID (ultraviolet-induced degradation) occurs, resulting in significant power loss. Traditional TOPCon cell fabrication methods introduce a large amount of hydrogen (H) elements during the front film process to form Si-H covalent bonds on the silicon substrate, filling the unsaturated dangling bonds of Si atoms on the substrate surface. However, Si-H covalent bonds have poor stability and low bond energy, making them highly susceptible to breakage under external energy (sunlight). This forms charged regions on the cell surface, trapping electrons for optical recombination, reducing minority carrier lifetime, and impacting the cell's power generation capacity. Therefore, reducing the UVID amplitude of TOPCon cells is a pressing issue that needs to be addressed. Summary of the Invention

[0003] Therefore, it is necessary to provide a method for preparing TOPCon cells and a TOPCon cell that improves UVID in response to the above problems.

[0004] The first aspect of this application provides a method for fabricating TOPCon cells with improved UVID, comprising: A first tunneling oxide layer and a barrier polysilicon layer are deposited on the back side of the processed silicon substrate. A second tunneling oxide layer and a doped polysilicon layer are then deposited on the deposited barrier polysilicon layer. A silicon dioxide masking film is formed on the back side of the silicon substrate, and back-side phosphorus diffusion is performed; Atomic layer deposition is performed on the front side of the silicon substrate to form an aluminum oxide layer, which is then passivated. Thin films are formed by PECVD deposition on the front and back sides of a silicon substrate and then passivated. The front-side film comprises a first silicon nitride layer, a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a silicon oxide layer, which are sequentially stacked. The refractive index of the first silicon nitride layer is 2.05-2.10, the refractive index of the second silicon nitride layer is 2.50-2.80, the refractive index of the third silicon nitride layer is 2.12-2.20, the refractive index of the fourth silicon nitride layer is 2.10-2.18, the refractive index of the first silicon oxynitride layer is 2.00-2.10, the refractive index of the second silicon oxynitride layer is 2.00-2.05, and the refractive index of the silicon oxide layer is 2.00-2.05. The main gate and sub-gate lines are screen-printed on the front and back sides of the silicon substrate, respectively.

[0005] In one embodiment, the thickness of the first silicon nitride layer is 3-5 nm, the thickness of the second silicon nitride layer is 10-15 nm, the thickness of the third silicon nitride layer is 10-18 nm, the thickness of the fourth silicon nitride layer is 15-25 nm, the thickness of the first silicon oxynitride layer is 5-7 nm, the thickness of the second silicon oxynitride layer is 7-9 nm, and the thickness of the silicon oxide layer is 4-6 nm.

[0006] In one embodiment, the deposition time of the first silicon nitride layer is 25s to 65s, and the nitrogen-silicon ratio is 4:1 to 6.7:1; the deposition time of the second silicon nitride layer is 80s to 180s, and the nitrogen-silicon ratio is 2.08:1 to 2.8:1.

[0007] In one embodiment, the deposition time of the first silicon nitride layer is 45s, and the nitrogen-to-silicon ratio is 6.7:1; the deposition time of the second silicon nitride layer is 130s, and the nitrogen-to-silicon ratio is 2.5:1.

[0008] In one embodiment, the film on the back side comprises three silicon nitride layers stacked sequentially.

[0009] In one embodiment, before forming a silicon dioxide masking film on the back side of the silicon substrate and performing back side phosphorus diffusion, and before performing atomic layer deposition on the front side of the silicon substrate to form an aluminum oxide layer and perform passivation treatment, the method further includes performing PSG removal treatment on the back side of the silicon substrate and front side etching treatment.

[0010] In one embodiment, before depositing a first tunneling oxide layer and a barrier polysilicon layer on the back side of the processed silicon substrate, and before depositing a second tunneling oxide layer and a doped polysilicon layer on the deposited barrier polysilicon layer, the method further includes: sequentially performing cleaning and texturing, front-side boron diffusion, and etching alkaline polishing treatments on the silicon substrate.

[0011] In one embodiment, after screen printing the main gate and sub-gate lines on the front and back sides of the silicon substrate, respectively, the method further includes: performing high-temperature sintering and photo-injection annealing on the silicon substrate after printing the main gate and sub-gate lines.

[0012] In one embodiment, after the silicon substrate with printed main and sub-gate lines is subjected to high-temperature sintering and photo-injection annealing, the method further includes: laser-assisted sintering of the sintered cell, and UV curing lamp irradiation and testing and packaging after MCP.

[0013] The second aspect of this application provides a TOPCon battery, which is prepared using the method described above.

[0014] The aforementioned method for fabricating TOPCon cells with improved UVID and the TOPCon cell itself involve depositing a first tunneling oxide layer and a barrier polycrystalline silicon layer on the back side of a treated silicon substrate, followed by depositing a second tunneling oxide layer and a doped polycrystalline silicon layer on the deposited barrier polycrystalline silicon layer; forming a silicon dioxide masking film on the back side of the silicon substrate and performing backside phosphorus diffusion; performing atomic layer deposition on the front side of the silicon substrate to form an aluminum oxide layer and then passivating it; performing PECVD deposition on both the front and back sides of the silicon substrate to form thin films and then passivating them; and screen printing the main grid and sub-grid lines on the front and back sides of the silicon substrate, respectively. The thin film on the front side comprises a seven-layer structure formed by sequential stacking, and by optimizing the refractive index of the silicon nitride layer and adjusting the formation of Si-H covalent bonds, the absorption capacity of light is reduced, resulting in a significant improvement in UVID and a reduction in the UVID amplitude of the TOPCon cell. Attached Figure Description

[0015] Figure 1 A flowchart of a TOPCon cell fabrication method for improving UVID in one embodiment; Figure 2 This is a schematic diagram of the positive membrane structure in one embodiment; Figure 3 This is a flowchart of a TOPCon cell fabrication method for improving UVID in another embodiment. Detailed Implementation

[0016] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0017] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application.

[0018] When used herein, the singular forms of “a,” “an,” and “the” may also include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprising / including” or “having,” etc., specify the presence of the stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not preclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. Meanwhile, the term “and / or” as used in this specification includes any and all combinations of the associated listed items.

[0019] In current positive film deposition processes, a 4-5 nm silicon nitride separator layer with a refractive index of approximately 2.05% is deposited close to the silicon substrate. This layer has a low hydrogen content, optimizing the formation of unstable Si-H bonds and reducing the risk of breakage. Simultaneously, a 13-16 nm silicon nitride layer with a refractive index of 2.5%-2.8% is deposited on the separator layer surface. High-refractive-index silicon nitride has poor photon transmission, with some photons reflected, reducing ultraviolet light absorption. By sequentially depositing low-refractive-index and high-refractive-index silicon nitride, hydrogen injection and ultraviolet light absorption are reduced, effectively improving the stability of the formed Si-H bonds and lowering the UVID amplitude. The disadvantages of this approach are: the overall high refractive index of the positive film results in poor ultraviolet light absorption around 350 nm, affecting cell efficiency; and reducing the hydrogen content of the bottom layer weakens passivation capabilities, leading to a loss in PID power decay.

[0020] Based on this, the TOPCon cell fabrication method for improving UVID provided in this application involves depositing a first tunneling oxide layer and a barrier polycrystalline silicon layer on the back side of a treated silicon substrate, and then depositing a second tunneling oxide layer and a doped polycrystalline silicon layer on the deposited barrier polycrystalline silicon layer; forming a silicon dioxide masking film on the back side of the silicon substrate and performing backside phosphorus diffusion; performing atomic layer deposition on the front side of the silicon substrate to form an aluminum oxide layer and performing passivation treatment; performing PECVD deposition on both the front and back sides of the silicon substrate to form thin films and performing passivation treatment; and screen printing the main grid and sub-grid lines on the front and back sides of the silicon substrate, respectively. The thin film on the front side comprises a seven-layer structure stacked sequentially, and by optimizing the refractive index structure of the two silicon nitride layers in contact with the silicon substrate, the generation of Si-H covalent bonds is adjusted, reducing the light absorption capacity, thereby significantly improving UVID.

[0021] In one embodiment, such as Figure 1 As shown, a method for fabricating TOPCon cells with improved UVID is provided, comprising: Step S110: Deposit a first tunneling oxide layer and a barrier polysilicon layer on the back side of the treated silicon substrate. Then, deposit a second tunneling oxide layer and a doped polysilicon layer on the deposited barrier polysilicon layer. LPCVD (low-pressure chemical vapor deposition) can be used to deposit the first tunneling oxide layer and the barrier polysilicon layer on the back side of the treated silicon substrate, followed by the deposition of the second tunneling oxide layer and the doped polysilicon layer.

[0022] Before step S110, the method may further include: sequentially cleaning and texturing the silicon substrate, performing front-side boron diffusion, and etching and alkaline polishing treatment.

[0023] First, the silicon substrate is cleaned and texturized to remove organic contaminants and metallic impurities from the silicon wafer surface, as well as the mechanical damage layer generated during the wire cutting process, reducing recombination centers. This process also creates an uneven, textured surface, utilizing the light-trapping effect to increase the absorption of sunlight by the silicon wafer, reducing reflectivity, and simultaneously increasing the surface area of ​​the silicon wafer, thereby increasing the PN junction area. Specifically, the texturizing process involves utilizing the anisotropic corrosion characteristics of silicon in a low-concentration alkaline solution (such as NaOH) under set concentration, temperature, and time conditions to conduct a series of chemical reactions between Si and the alkaline solution (such as NaOH) to form a pyramidal textured surface on the silicon wafer. Then, a PN junction is formed through a front-side boron diffusion process. Specifically, P-type elements (boron) are diffused onto an N-type silicon wafer (phosphorus-doped) to form a PN junction (i.e., the space charge region, forming a P+ layer on the front side and an N+ layer on the back side). The principle of front-side boron diffusion is as follows: under set concentration, temperature, pressure, and time conditions, the boron source (BBr3 or BCl3) is vaporized in a tube furnace and deposited on the silicon wafer surface through a series of chemical reactions to obtain suitable doping concentration, junction depth, and sheet resistance. Finally, alkaline polishing is performed through an etching and alkaline polishing process to obtain the treated silicon substrate.

[0024] Step S120: Form a silicon dioxide masking film on the back side of the silicon substrate and perform back side phosphorus diffusion.

[0025] First, the oxygen flow rate is increased to form a silicon dioxide masking film on the back side of the silicon substrate, followed by backside phosphorus diffusion. The purpose of phosphorus diffusion is to form an N+ layer on the back side. In the presence of oxygen, POCl3 decomposes at high temperature (e.g., 600℃) to generate phosphorus pentachloride (PCl5) and phosphorus pentoxide (P2O5). The generated P2O5 reacts with silicon at the diffusion temperature to generate silicon dioxide (SiO2) and phosphorus atoms. This allows the generated phosphorus to diffuse into the silicon wafer, achieving phosphorus doping. Sufficient oxygen is introduced during phosphorus diffusion so that PCl5 reacts with oxygen to generate P2O5 and Cl2, thus avoiding the adverse effects of insufficient oxygen on the silicon wafer caused by PCl5.

[0026] After step S120 and before step S130, the method further includes performing PSG (phosphosilicate glass) removal treatment on the back side of the silicon substrate and front side etching treatment.

[0027] In the phosphorus diffusion process of solar cells, while phosphorus doping is achieved, silicon dioxide and phosphorus pentoxide (PSG) remain on the silicon wafer surface and need to be removed. This can be done by washing with hydrofluoric acid solution, followed by front-side etching. The front-side etching process includes: front etching tank (with water film) → water washing → alkaline washing → water washing → acid washing → water washing → drying. The purpose of the front etching tank is mainly to etch the front and edges of the silicon wafer with a mixed solution of HF and HNO3 to remove the PSG from the front and edges. The alkaline washing is mainly used to neutralize the residual acid in the front etching tank and remove the porous silicon generated by the reaction in the front etching tank. The acid washing is used to remove the oxide layer and make the silicon wafer surface hydrophobic.

[0028] Step S130: Atomic layer deposition (ALD) is performed on the front side of the silicon substrate to form an alumina layer and then passivation treatment is applied. Atomic layer deposition is a high-precision thin film deposition technique based on chemical vapor deposition (CVD). It is a technique that deposits materials as single-atom films layer by layer onto the substrate surface based on chemical vapor deposition. Two or more precursor chemicals, each containing different elements of the material to be deposited, are introduced onto the substrate surface one at a time. A denser alumina layer is formed on the front side of the silicon substrate using atomic layer deposition, with a deposition thickness ranging from 3-10 nm. By time or spatial intervals, the substrate is alternately exposed to different reaction precursor atmospheres. For example, when the substrate is in the atmosphere of the first precursor, the first precursor is retained on the substrate surface through chemisorption. After the first precursor is saturated with adsorption, it reaches a stable state and will not undergo further chemisorption. When the substrate is exposed to the atmosphere of the second precursor, the second precursor reacts with the first precursor that has been adsorbed on the substrate surface. A reaction occurs between the two precursors to produce corresponding byproducts. The reaction will automatically stop and form the required alumina layer until the first precursor on the surface is completely consumed, after which passivation treatment will be performed.

[0029] Step S140: PECVD (Plasma Enhanced Chemical Vapor Deposition) is performed on the front and back sides of the silicon substrate to form a thin film, followed by passivation treatment.

[0030] Among them, such as Figure 2As shown, an N-type silicon wafer is obtained after PSG removal and front-side etching of the silicon substrate. Then, atomic layer deposition is performed to form an aluminum oxide layer, followed by passivation. Front-side deposition is performed on the aluminum oxide layer, forming a thin film consisting of a first silicon nitride layer, a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a silicon oxide layer, which are then passivated. The refractive index of the first silicon nitride layer is 2.05-2.10, for example, 2.05, 2.08, 2.10, etc. The refractive index of the second silicon nitride layer is 2.50-2.80, for example, 2.50, 2.60, 2.80, etc. The refractive index of the third silicon nitride layer is 2.12-2.20, for example, 2.12, 2.15, 2.20, etc. The refractive index of the fourth silicon nitride layer is 2.10-2.18, for example, 2.10, 2.14, 2.18, etc. The refractive index of the first silicon oxynitride layer is 2.00-2.10, for example, 2.00, 2.05, 2.10, etc. The refractive index of the second silicon oxynitride layer is 2.00-2.05, for example, 2.00, 2.03, 2.05, etc. The refractive index of the silicon oxide layer is 2.00-2.05, for example, 2.00, 2.03, 2.05, etc. Further, the thickness of the first silicon nitride layer is 3-5 nm, for example, 3 nm, 3.5 nm, 4 nm, 4.8 nm, 5 nm, etc.; the thickness of the second silicon nitride layer is 10-15 nm, for example, 10 nm, 12 nm, 14 nm, 15 nm, etc.; the thickness of the third silicon nitride layer is 10-18 nm, for example, 10 nm, 14 nm, 16 nm, 18 nm, etc.; the thickness of the fourth silicon nitride layer is 15-25 nm, for example, 15 nm, 18 nm, 20 nm, 25 nm, etc. The thickness of the first silicon oxynitride layer is 5-7 nm, for example, 5 nm, 6 nm, 7 nm, etc. The thickness of the second silicon oxynitride layer is 7-9 nm, for example, 7 nm, 8 nm, 9 nm, etc. The thickness of the silicon oxide layer is 4-6 nm, for example, 4 nm, 5 nm, 6 nm, etc. The back-side deposited film consists of three silicon nitride layers stacked sequentially, and a back surface passivation treatment is performed after the back-side deposition is completed.

[0031] By optimizing the refractive index of the two silicon nitride layers (first and second silicon nitride layers) in contact with the silicon substrate, the formation of Si-H covalent bonds is adjusted, reducing the light absorption capacity and thus significantly improving UV ID. The specific process parameters for the first and second silicon nitride layers are not unique. The deposition time for the first silicon nitride layer is 25s to 65s, for example, 25s, 30s, 35s, 40s, 45s, 50s, 55s, 60s, 65s, etc., with a nitrogen-to-silicon ratio of 4:1 to 6.7:1, for example, 4:1, 5:1, 5.8:1, 6.7:1, etc. The deposition time for the second silicon nitride layer is 80s to 180s, for example, 80s, 100s, 120s, 140s, 160s, 180s, etc., with a nitrogen-to-silicon ratio of 2.08:1 to 2.8:1, for example, 2.08:1, 2.5:1, 2.8:1, etc. In this embodiment, the deposition time of the first silicon nitride layer is 45s, and the nitrogen-silicon ratio is 6.7:1; the deposition time of the second silicon nitride layer is 130s, and the nitrogen-silicon ratio is 2.5:1.

[0032] It is understandable that for a seven-layer structure deposited on the front side, different deposition times will result in different thicknesses of the resulting structure. By controlling the deposition time of each layer, the thickness of the corresponding structure can be controlled. Similarly, different nitrogen-to-silicon ratios will result in different refractive indices of the resulting structure. By controlling the nitrogen-to-silicon ratio of each layer, the refractive index of the corresponding structure can be controlled. Both the thickness and refractive index of each layer affect the UVID amplitude of the solar cell.

[0033] Step S150: Screen print the main gate and sub-gate lines on the front and back sides of the silicon substrate, respectively. After depositing thin films on the front and back sides of the silicon substrate, screen print the main gate and sub-gate lines on the back side and the main gate and sub-gate lines on the front side, respectively. The printing on both the front and back sides adopts a step-by-step printing method. The specific process flow is as follows: print the main gate lines on the back side → oven → print the sub-gate lines on the back side → oven → print the main gate lines on the front side → oven → print the sub-gate lines on the front side.

[0034] In one embodiment, such as Figure 3 As shown, after step S150, the method further includes step S160: high-temperature sintering and photo-injection annealing of the silicon substrate after the main gate and sub-gate lines have been printed. After the printing of the main gate and sub-gate lines on the front and back sides is completed, the silicon substrate is subjected to high-temperature sintering and photo-injection annealing. The purpose of high-temperature sintering is to dry the paste on the silicon wafer, burn off the organic components of the paste, and form a good ohmic contact between the paste and the silicon wafer. The electrodes are sintered on the PN junction. High-temperature sintering allows the electrodes to penetrate the silicon nitride film and form an alloy. In this case, the front main gate line does not burn through the silicon nitride, reducing the damage of the silicon nitride layer by the metal and improving the on-state voltage.

[0035] Furthermore, following step S160, the method also includes step S170: laser-assisted sintering of the sintered solar cells, followed by UV curing irradiation and testing / packaging after MCP (Multi-Chip Packaging). Laser-assisted sintering is used to better achieve the sintering objective, followed by MCP and UV curing irradiation, and finally, the testing and packaging process.

[0036] In one embodiment, a TOPCon cell is also provided, including a first tunneling oxide layer, a barrier polycrystalline silicon layer, a second tunneling oxide layer, a doped polycrystalline silicon layer, an aluminum oxide layer, a thin film, a main grid, and a sub-grid line, etc. The TOPCon cell is prepared by the above method.

[0037] To better understand the beneficial effects of the above TOPCon battery fabrication method, experimental results are presented below to verify the above scheme. The data from multiple verifications are as follows: Case 1: The deposition time for the first silicon nitride layer was set to 45 seconds, and the nitrogen-silicon ratio was set to a stepwise variation of 6.7:1 / 5.8:1 / 5.1:1 / BL4:1, corresponding to refractive indices of 2.05 / 2.10 / 2.15 / 2.20, respectively. The measured UV60 attenuation values ​​were 2.12% / 2.42% / 2.51% / 2.67%, respectively. It can be seen that the UV attenuation is lowest when the nitrogen-silicon ratio is 6.7:1.

[0038] Case 2: With a nitrogen-to-silicon ratio of 6.7:1 for the first silicon nitride layer and deposition times varying in steps of 25s, 45s, and 65s, the corresponding thicknesses of the first silicon nitride layer were 2.1nm, 3.5nm, and 4.8nm, respectively, and the UV60 degradation values ​​were 2.55%, 2.24%, and 2.09%, respectively. It can be seen that the UV degradation is lowest at 65s, but the efficiency degradation is severe. Therefore, a time of 45s was chosen as the mass production process.

[0039] Case 3: The nitrogen-silicon ratio of the first silicon nitride layer was set to 2.5:1, and the coating time was 45s. The coating time of the second silicon nitride layer was set to 130s. The nitrogen-silicon ratio of the second silicon nitride layer changed stepwise from 2.8:1 to 2.5:1 to 2.08:1. The corresponding refractive indices were 2.5, 2.6, and 2.7, respectively. The UV60 degradation values ​​were 2.37%, 2.24%, and 2.19%, respectively. Considering the efficiency degradation, a nitrogen-silicon ratio of 2.5:1 was selected as the mass production process.

[0040] Case 4: The nitrogen-silicon ratio of the first silicon nitride layer is set to 2.5:1 / 45s, and the nitrogen-silicon ratio of the second silicon nitride layer is set to 2.5:1. The deposition time of the second silicon nitride layer varies in steps of 80 / 130 / 180s. The corresponding thicknesses of the second silicon nitride layer are 8nm / 14nm / 19nm, respectively. The UV60 degradation values ​​are 1.71% / 1.49% / 1.28%, respectively. Considering the efficiency degradation, a time of 130s is selected as the mass production process.

[0041] Case 4 is repeated: The UV60 attenuation values ​​were 1.82% / 1.52% / 1.31%, respectively, which is consistent with the initial test results in Case 4.

[0042] The verification data results for the above cases are shown in Table 1.

[0043] Table 1

[0044] The comparison shows that setting the coating time of the first silicon nitride layer to 45s / silicon-nitrogen ratio of 6.7:1 + the coating time of the second silicon nitride layer to 130s / silicon-nitrogen ratio of 2.5:1 as two processes results in a stable decrease in UV60 attenuation value from 2.6% to 1.5%, with an efficiency loss of 0.1%. This achieves process optimization at the battery end, reduces the UVID amplitude, and can be promoted as a mass production process.

[0045] The technical features of the above embodiments can be combined in any way. For the sake of brevity, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0046] The embodiments described above are merely illustrative of several implementation methods of this application, and while the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the invention patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this application, and these all fall within the protection scope of this application. Therefore, the protection scope of this patent application should be determined by the appended claims.

Claims

1. A method for fabricating TOPCon cells with improved UVID, characterized in that, include: A first tunneling oxide layer and a barrier polysilicon layer are deposited on the back side of the processed silicon substrate. A second tunneling oxide layer and a doped polysilicon layer are then deposited on the deposited barrier polysilicon layer. A silicon dioxide masking film is formed on the back side of the silicon substrate, and back-side phosphorus diffusion is performed; Atomic layer deposition is performed on the front side of the silicon substrate to form an aluminum oxide layer, which is then passivated. Thin films are formed by PECVD deposition on the front and back sides of a silicon substrate and then passivated. The front-side film comprises a first silicon nitride layer, a second silicon nitride layer, a third silicon nitride layer, a fourth silicon nitride layer, a first silicon oxynitride layer, a second silicon oxynitride layer, and a silicon oxide layer, which are sequentially stacked. The refractive index of the first silicon nitride layer is 2.05-2.10, the refractive index of the second silicon nitride layer is 2.50-2.80, the refractive index of the third silicon nitride layer is 2.12-2.20, the refractive index of the fourth silicon nitride layer is 2.10-2.18, the refractive index of the first silicon oxynitride layer is 2.00-2.10, the refractive index of the second silicon oxynitride layer is 2.00-2.05, and the refractive index of the silicon oxide layer is 2.00-2.

05. The main gate and sub-gate lines are screen-printed on the front and back sides of the silicon substrate, respectively.

2. The method according to claim 1, characterized in that, The thickness of the first silicon nitride layer is 3-5 nm, the thickness of the second silicon nitride layer is 10-15 nm, the thickness of the third silicon nitride layer is 10-18 nm, the thickness of the fourth silicon nitride layer is 15-25 nm, the thickness of the first silicon oxynitride layer is 5-7 nm, the thickness of the second silicon oxynitride layer is 7-9 nm, and the thickness of the silicon oxide layer is 4-6 nm.

3. The method according to claim 2, characterized in that, The deposition time of the first silicon nitride layer is 25s to 65s, and the nitrogen-silicon ratio is 4:1 to 6.7:1; the deposition time of the second silicon nitride layer is 80s to 180s, and the nitrogen-silicon ratio is 2.08:1 to 2.8:

1.

4. The method according to claim 3, characterized in that, The deposition time for the first silicon nitride layer is 45s, and the nitrogen-to-silicon ratio is 6.7:1; the deposition time for the second silicon nitride layer is 130s, and the nitrogen-to-silicon ratio is 2.5:

1.

5. The method according to claim 1, characterized in that, The film on the back side consists of three silicon nitride layers stacked sequentially.

6. The method according to any one of claims 1 to 5, characterized in that, Before forming an aluminum oxide layer and performing passivation on the front side of the silicon substrate, after forming a silicon dioxide masking film on the back side and performing back side phosphorus diffusion, the process also includes: performing PSG removal on the back side of the silicon substrate and front side etching.

7. The method according to any one of claims 1 to 5, characterized in that, Before depositing a first tunneling oxide layer and a barrier polysilicon layer on the back side of the processed silicon substrate, and before depositing a second tunneling oxide layer and a doped polysilicon layer on the deposited barrier polysilicon layer, the process further includes: sequentially cleaning and texturing the silicon substrate, performing boron diffusion on the front side, and etching and alkaline polishing.

8. The method according to any one of claims 1 to 5, characterized in that, After screen printing the main gate and sub-gate lines on the front and back sides of the silicon substrate, the process also includes high-temperature sintering and photo-injection annealing of the silicon substrate after printing the main gate and sub-gate lines.

9. The method according to claim 8, characterized in that, After the silicon substrate with printed main and sub-gate lines is subjected to high-temperature sintering and photo-injection annealing, the process also includes: laser-assisted sintering of the sintered cells, and UV curing after MCP, followed by testing and packaging.

10. A TOPCon battery, characterized in that, It is prepared by the method described in any one of claims 1 to 9.

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