A test screening method and system for enhancing the anti-electric interference of a chip

Abstract

The application provides a kind of enhanced chip anti-electric interference test screening method and system, belong to integrated circuit test technical field, including: the establishment of topological network interference model, the model includes the topological connection relationship of chip power supply pin, ground pin and signal pin, and the interference source parameter set according to chip rated voltage range and interference distance;Interference path is constructed, forming three groups of test structures;Obtain current distribution parameters, including determining initial current value, calculating pressure drop value, determining test current value;Perform interference simulation test;When the simulation result meets the preset condition, the distance between each test structure in the topological network interference model is dynamically adjusted, and the optimized test model is formed;According to the optimized test model, chip batch screening is carried out, the precise interference model is constructed by topological network theory, the current distribution parameters are optimized and the test structure is dynamically adjusted, the high-precision test and efficient screening of the anti-electric interference capability of chip are realized.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit testing technology, and in particular to a testing and screening method and system for enhancing chip immunity to electrical interference. Background Technology

[0002] With the continuous improvement of integrated circuit integration and the increasing complexity of application environments, the chip's immunity to electromagnetic interference has become a key factor affecting product reliability. Traditional chip immunity testing methods mainly rely on empirical parameter settings and simple circuit models, which are difficult to accurately simulate complex electromagnetic interference environments, resulting in significant differences between test results and actual application scenarios.

[0003] Currently, chip anti-interference testing mainly suffers from the following problems: First, the testing accuracy is insufficient. Existing methods are mostly based on simplified models, which make it difficult to fully consider the complex circuit topology and interference propagation paths inside the chip. Second, the testing efficiency is low. Conventional methods require a large number of redundant tests, which are time-consuming. Third, the adaptability is poor. Test schemes need to be redesigned for different types of chips, and there is a lack of a unified test framework.

[0004] Therefore, there is an urgent need for a testing method and system that can accurately model the chip circuit topology and efficiently screen the chip's resistance to electrical interference. Summary of the Invention

[0005] The purpose of this invention is to provide a chip anti-interference testing and screening method and system based on topology network theory. By constructing an accurate topology network interference model, optimizing current distribution parameters, and dynamically adjusting the test structure, high-precision testing and efficient screening of chip anti-interference capabilities can be achieved.

[0006] This invention proposes a test and screening method to enhance the immunity of chips to electrical interference, comprising:

[0007] A topology network interference model is established, which includes the topological connection relationship of the chip's power supply pins, ground pins and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance.

[0008] Constructing interference pathways, including:

[0009] Connect the power supply pin of the chip to the first analog ground pin, and connect the ground pin of the chip to the second analog ground pin to form the first test structure;

[0010] Select a set of consecutive locations from all the first analog ground pins, connect the consecutive locations together to form a first interference path, and connect the signal pins together based on the first interference path to form a second set of test structures;

[0011] Select a set of consecutive positions from all the second analog ground pins, connect the consecutive positions together to form a second interference path, and connect the first signal pin to the second interference path based on the second interference path to form a third set of test structures;

[0012] Obtain current distribution parameters, including:

[0013] Based on the theoretical current value of the chip, determine the initial current value of each node in the topology network interference model;

[0014] Obtain the voltage values ​​of each signal pin in the interference model of the topology network, and calculate the voltage drop of the chip based on the voltage values ​​of the signal pins and the voltage values ​​of the power supply pins;

[0015] Based on the voltage drop value, the test current value of each test structure is determined, and the corresponding current value is added to the corresponding position of each test structure in the topology network interference model.

[0016] Perform interference simulation tests to obtain the simulation results of the interference model of the topology network;

[0017] When the simulation results meet the preset conditions, the distance between each test structure in the topology network interference model is dynamically adjusted to form an optimized test model.

[0018] Based on the simulation results of the optimized test model, a batch screening of chips is performed.

[0019] Preferably, the step of establishing the topology network interference model specifically includes:

[0020] The physical structure of the chip is converted into a set of digital nodes, with each pin mapped to a node in the topology network;

[0021] Based on the functional blocks of the chip, the node is divided into a power domain, a ground domain, and a signal domain;

[0022] Based on the chip's design specifications, establish the connections between nodes to form an initial topology graph;

[0023] An interference source is added to the initial topology diagram, and the parameters of the interference source are set according to the rated voltage range of the chip and the interference distance.

[0024] Preferably, the step of constructing the interference path specifically includes:

[0025] Select consecutive locations with the highest connectivity from the first analog ground pin to form the first interference path;

[0026] Cluster analysis is performed on the signal pins to identify sets of nodes sensitive to interference;

[0027] Based on the set of nodes sensitive to interference, the second set of test structures is constructed, and the signal pins are connected together;

[0028] Select consecutive locations with the highest interference propagation efficiency from the second analog ground pins to form the second interference path;

[0029] The first signal pin is connected to the second interference path to form the third set of test structures.

[0030] Preferably, the step of obtaining the current distribution parameters specifically includes:

[0031] The theoretical current value is extracted from the chip's specifications.

[0032] The theoretical current values ​​are used as edge weights of the topology network to construct an initial current distribution model;

[0033] Obtain the voltage values ​​of each signal pin in the interference model of the topology network;

[0034] Calculate the voltage drop of the chip based on the voltage values ​​of the signal pin and the power supply pin;

[0035] Based on the voltage drop value and the connection relationship of the topology network, the current distribution in the network is calculated;

[0036] Assess the uniformity of current distribution and identify anomalies and singular regions in the current distribution;

[0037] Based on the anomalies and singular regions, determine the test current value for each test structure.

[0038] Preferably, the step of performing interference simulation testing specifically includes:

[0039] Set the interference simulation parameters, including interference source type, interference intensity, interference frequency, and duration;

[0040] Perform electromagnetic interference simulation in the aforementioned topology network interference model;

[0041] Obtain the response results of the interference model of the topology network;

[0042] Extract key indicators such as interference response sensitivity, result consistency, coverage integrity, and screening accuracy;

[0043] The key indicators are compared with preset conditions.

[0044] Preferably, the step of dynamically adjusting the topology network interference model specifically includes:

[0045] Analyze the simulation results to identify areas that need optimization;

[0046] Identify key adjustment parameters, including the distance between test structures, connection relationships, and functional domain boundaries;

[0047] Generate a topology adjustment scheme;

[0048] According to the adjustment scheme, the distances between the test structures in the topology network interference model are gradually adjusted;

[0049] Verify the performance of the adjusted model;

[0050] When the performance improvement is less than the preset threshold, confirm the final optimized test model.

[0051] Preferably, the step of performing batch chip screening based on the simulation results of the optimized test model specifically includes:

[0052] Based on the optimized test model, set the batch test parameters;

[0053] Connect multiple chips under test to the test equipment in parallel;

[0054] Interference tests were performed on the multiple chips under test according to the test structure and parameters in the optimized test model.

[0055] Collect test data for each chip, including voltage response, current distribution, and signal integrity;

[0056] Based on preset screening thresholds, the anti-electrical interference performance of each chip is evaluated;

[0057] Chips that meet the requirements for anti-electrical interference performance are marked as qualified, and chips that do not meet the requirements are marked as unqualified.

[0058] Preferably, the preset conditions include:

[0059] Interference response sensitivity is in the range of 5% to 20%;

[0060] The consistency rate of the results was higher than 98%;

[0061] Coverage integrity is higher than 90%;

[0062] The screening accuracy rate is higher than 97%.

[0063] Preferably, the key adjustment parameters also include:

[0064] Node centrality is used to evaluate the importance of a node in a network.

[0065] Clustering coefficient, used to evaluate the degree of clustering of nodes;

[0066] Path complexity is used to evaluate the characteristics of interference propagation paths;

[0067] Network entropy is used to evaluate the determinism and stability of a network topology.

[0068] A test and screening system to enhance chip immunity to electrical interference includes:

[0069] The topology network construction module is used to establish a topology network interference model. The topology network interference model includes the topology connection relationship of the chip's power supply pins, ground pins, and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance.

[0070] An interference path construction module is used to construct interference paths, including: connecting the power supply pin of the chip to a first analog ground pin, and connecting the ground pin of the chip to a second analog ground pin to form a first set of test structures; selecting a set of consecutive positions from all the first analog ground pins, connecting the consecutive positions together to form a first interference path, and connecting signal pins together based on the first interference path to form a second set of test structures; selecting a set of consecutive positions from all the second analog ground pins, connecting the consecutive positions together to form a second interference path, and connecting a first signal pin to the second interference path based on the second interference path to form a third set of test structures;

[0071] The current distribution module is used to acquire current distribution parameters, including: determining the initial current value of each node in the topology network interference model based on the theoretical current value of the chip; acquiring the voltage value of each signal pin in the topology network interference model, and calculating the voltage drop value of the chip based on the voltage values ​​of the signal pins and the voltage values ​​of the power supply pins; determining the test current value of each test structure based on the voltage drop value, and adding the corresponding current value at the corresponding position of each test structure in the topology network interference model;

[0072] The simulation execution module is used to perform interference simulation tests and obtain the simulation results of the interference model of the topology network.

[0073] The topology optimization module is used to dynamically adjust the distance between each test structure in the topology network interference model when the simulation results meet preset conditions, so as to form an optimized test model.

[0074] The chip screening module is used to perform batch chip screening based on the simulation results of the optimized test model.

[0075] The present invention has the following beneficial effects:

[0076] 1. Significantly improved test accuracy: By constructing an accurate interference model through topological network theory, taking into account the complex circuit topology and interference propagation path inside the chip, the test results are closer to the actual application scenario, and the test accuracy is improved by about 40%.

[0077] 2. Significantly improved testing efficiency: The dynamic topology adaptive adjustment mechanism reduces invalid tests by about 50%, significantly improving batch screening efficiency and enabling a testing speed of more than 100 chips per hour.

[0078] 3. High adaptability: Through adaptive adjustment of the topology network, the system can quickly adapt to different types of chip structures, reduce the development cycle of new chip testing schemes, and provide a unified testing framework for different application scenarios.

[0079] 4. High interpretability: The interference propagation mechanism is displayed through topology visualization, which improves the accuracy of fault location and helps guide the optimization and improvement of chip anti-interference design. Attached Figure Description

[0080] Figure 1 This is a flowchart of a test and screening method for enhancing chip immunity to electrical interference provided by an embodiment of the present invention;

[0081] Figure 2 This is a block diagram of the test and screening system for enhancing chip immunity to electrical interference provided in an embodiment of the present invention. Detailed Implementation

[0082] Please refer to Figure 1 - Figure 2 The present invention will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be understood that the specific embodiments described herein are for illustrative and explanatory purposes only and are not intended to limit the scope of the invention.

[0083] like Figure 1 As shown, the present invention provides a test and screening method for enhancing chip immunity to electrical interference, comprising the following steps:

[0084] In a preferred embodiment of the present invention, the process of establishing a topology network interference model includes converting the chip physical structure into a set of digital nodes and mapping the pins to nodes in the topology network; dividing the nodes into power domain, ground domain and signal domain based on the chip functional blocks; establishing the connection relationship between the nodes according to the chip design specifications to form an initial topology graph; adding interference sources to the topology graph and setting the interference source parameters.

[0085] Specifically, when the chip's physical structure is digitized, each pin (power pin, ground pin, and signal pin) is mapped to a node in a topology network. Each node contains the following attributes: node ID, node type, physical location coordinates, and functional attributes. For example, a power pin node can be represented as {ID:"P1",Type:"power_pin",Position:[2.5,3.7],Attributes:{Voltage:3.3V}}.

[0086] During the domain partitioning process, based on the functional blocks of the chip, nodes are divided into three categories: power domain, ground domain, and signal domain. Preferably, the power domain includes all power pins and their directly connected internal nodes; the ground domain includes all ground pins and their directly connected internal nodes; and the signal domain includes all signal pins and related signal processing nodes.

[0087] When establishing connections, the connection method and strength between nodes are determined according to the chip design specifications. In this embodiment, the connection relationship can be represented as a matrix, where the matrix elements represent the strength or characteristics of the connection between nodes. For example, for a network with n nodes, the connection matrix C is an n×n matrix, and the element C[i,j] represents the connection strength between node i and node j. When two nodes are directly connected, C[i,j] takes the reciprocal of the connection resistance; when two nodes are not directly connected, C[i,j] is 0.

[0088] When setting the interference source parameters, the configuration should be based on the chip's rated voltage range and the interference distance. Preferably, for a chip with a rated operating voltage of 3.3V, the interference source voltage can be set to ±10% of the rated voltage, i.e., 3.0V to 3.6V; the interference distance can be set to 2 to 5 times the minimum distance between pins. This range can usually effectively simulate electromagnetic interference in real-world application environments.

[0089] In one embodiment of the present invention, the interference path construction process includes three key steps, forming three sets of test structures.

[0090] First, connect the chip's power supply pins to the first analog ground pin, and connect the chip's ground pins to the second analog ground pin, forming the first test structure. This structure establishes the basic test environment for the chip's power system. For example, for a chip with four power supply pins and four ground pins, all power supply pins can be connected in parallel to the first analog ground, and all ground pins can be connected in parallel to the second analog ground.

[0091] Next, select consecutive locations with the highest connectivity from all the first analog ground pins and connect these locations together to form the first interference path. Preferably, connectivity can be measured by the degree of a node (the number of edges directly connected to it). For example, nodes with a degree value exceeding 50% of the average degree value can be given priority for inclusion in the interference path. Based on the first interference path, connect the signal pins together to form the second set of test structures.

[0092] Finally, consecutive locations with the highest interference propagation efficiency are selected from all the second analog ground pins, and these locations are connected together to form a second interference path. Preferably, the interference propagation efficiency can be determined through path analysis; pins located near the main signal transmission path typically have higher interference propagation efficiency. Based on the second interference path, the first signal pin is connected to the second interference path to form a third set of test structures.

[0093] In practical applications, a typical microcontroller chip may contain approximately 20 first analog ground pins and 20 second analog ground pins. Preferably, 5 to 8 consecutive pins can be selected to form an interference path, which ensures sufficient interference coverage without causing excessive interference that could affect test accuracy.

[0094] This step mainly includes determining the initial current distribution based on the chip's theoretical current value, measuring the voltage value to calculate the voltage drop, and determining the test current value.

[0095] First, theoretical current values ​​are extracted from the chip specifications and used as edge weights in the topology network to construct an initial current distribution model. The theoretical current values ​​vary depending on the type of chip. For example, the operating current of a low-power microcontroller typically ranges from a few milliamps to tens of milliamps, while high-performance processors may reach several amps. In this embodiment, for a typical 3.3V-powered microcontroller, a quiescent operating current of 10mA can be used as a baseline value.

[0096] Next, the voltage values ​​of each signal pin in the topology network interference model are obtained. This process can be completed through simulation or actual measurement. For simulation, the following voltage distribution function can be used:

[0097] ,

[0098] in: The voltage value at node i is expressed in volts (V). This is a reference voltage value, usually the power supply voltage, and the unit is volts (V). Let be the connection weight between node i and node j, representing the connection strength, which is dimensionless; Here is the voltage value at node j, in volts (V). The total number of nodes in the network; The summation variable ranges from 1 to n. This formula calculates node voltages using a weighted average method, with the weights reflecting the degree of influence of connections between nodes.

[0099] Calculate the voltage drop across the chip based on the voltage values ​​at the signal and power supply pins. The formula for calculating the voltage drop is:

[0100] ,

[0101] in: The voltage drop value is expressed in volts (V). This is the voltage value at the power supply pin, in volts (V). This represents the signal pin voltage value, measured in volts (V). The voltage drop reflects the loss of power supply voltage during transmission and is an important parameter for evaluating the electrical performance of a chip.

[0102] Based on the voltage drop and the network topology, the current distribution within the network is calculated. The current distribution can be calculated using the following formula:

[0103] ,

[0104] in: The current flowing from node i to node j is expressed in amperes (A). The voltage difference between node i and node j is expressed in volts (V). The equivalent resistance between node i and node j is expressed in ohms. This formula, based on Ohm's law, is used to calculate the current magnitude on each connection path in a network.

[0105] In a preferred embodiment of the invention, the method further includes evaluating the uniformity of the current distribution and identifying anomalies and singular regions in the current distribution. The uniformity of the current distribution can be calculated using the following formula:

[0106] ,

[0107] Where Balance is the equilibrium index, with a value ranging from 0 to 1. The larger the value, the more balanced the distribution. It is dimensionless. The standard deviation of the current distribution is expressed in amperes (A). This represents the average value of the current distribution, measured in amperes (A). Preferably, a balance value below 0.7 indicates an uneven current distribution requiring adjustment. Standard deviation The square root of the average of the summation of the squares of the differences between the current at each node and the average current is used to obtain the current distribution, which reflects the degree of dispersion of the current distribution.

[0108] Finally, based on the anomalies and singular regions, the test current value for each test structure is determined, and the corresponding current value is added to the corresponding position of each test structure in the topology network interference model. For example, for the detected high current density region, the test current value can be increased by 50% to enhance the test intensity; for the low current density region, the original current value can be maintained or slightly reduced.

[0109] The process of performing interference simulation tests includes setting interference simulation parameters, performing electromagnetic interference simulation, obtaining response results, extracting key indicators, and comparing them with preset conditions.

[0110] First, set the interference simulation parameters, including the interference source type, interference intensity, interference frequency, and duration. In this embodiment, preferred interference source types include pulse interference, sinusoidal interference, and white noise interference. The interference intensity is typically set to ±10% to ±30% of the chip's rated voltage, the interference frequency range can be from DC to 5 times the chip's operating frequency, and the duration can range from microseconds to milliseconds. For example, for a chip with an operating frequency of 100MHz, the interference frequency can be set in the range of DC to 500MHz, and the interference duration can be set to 10μs.

[0111] Next, electromagnetic interference simulation was performed in the topology network interference model. The simulation process used a combination of time-domain and frequency-domain methods to capture the chip's response characteristics under different interference conditions. Time-domain simulation allows observation of the chip's response to transient interference, while frequency-domain simulation helps analyze the chip's sensitivity to interference at different frequencies.

[0112] After obtaining the response results of the topology network interference model, key indicators such as interference response sensitivity, result consistency, coverage integrity, and screening accuracy are extracted. Among these, interference response sensitivity reflects the chip's sensitivity to interference and can be calculated using the following formula:

[0113] ,

[0114] Wherein: Sensitivity is the interference response sensitivity, expressed as a percentage (%); ΔPerformance is the change in chip performance, which can be a change in voltage, current, or functional parameters, with the unit depending on the specific parameter; ΔInterference is the change in interference intensity, usually expressed as a change in voltage or current, with the corresponding unit being volts (V) or amperes (A). Preferably, a sensitivity value in the range of 5% to 20% is suitable; too low a value indicates insensitivity to testing, while too high a value indicates poor anti-interference capability of the chip.

[0115] Consistency of results reflects the stability of results from repeated tests, and can be calculated using the coefficient of variation.

[0116] ,

[0117] Where: Consistency represents the consistency of results, expressed as a percentage (%). The standard deviation of repeated test results is given, and the unit depends on the test parameters. The average of repeated test results, in units of 1 and 2. Same. Preferably, the consistency value should be no less than 95%, indicating that the test results have good repeatability. Standard deviation The square root of the average of the sums of the squares of the differences between multiple test results and the average value is used to reflect the stability of the test results.

[0118] Coverage integrity reflects the degree to which the test covers the chip's functionality, and can be expressed as:

[0119] ,

[0120] Where: Coverage is the coverage integrity, and the unit is percentage (%). This represents the number of functionalities that have been tested, expressed in units. This refers to the total number of function points of the chip, expressed in units. Preferably, the Coverage value should be no less than 90% to ensure comprehensive testing. A function point is the basic unit of a chip's functional characteristics, which can be a functional module, signal path, or specific operation.

[0121] Screening accuracy reflects the accuracy of the screening results and can be expressed as:

[0122] ,

[0123] in The accuracy rate is expressed as a percentage (%). For true examples (chips correctly identified as qualified), the unit is one; True negative examples (chips correctly identified as defective), unit: individual. False positives (chips incorrectly identified as qualified), unit: individual; False negatives (chips incorrectly identified as unqualified), measured in units of one. Preferably, the accuracy value should be no less than 97% to ensure the reliability of the screening results.

[0124] Finally, the key indicators are compared with the preset conditions. These preset conditions typically include interference response sensitivity within the range of 5% to 20%, result consistency higher than 98%, coverage integrity higher than 90%, and screening accuracy higher than 97%. Only when all indicators meet the preset conditions does the process proceed to the next step; otherwise, the model parameters need to be adjusted and the simulation re-executed.

[0125] When the simulation results meet the preset conditions, this invention employs a dynamic adjustment mechanism to optimize the topology network interference model. This process includes analyzing the simulation results, determining key adjustment parameters, generating adjustment schemes, performing incremental adjustments, verifying the adjustment effects, and finally confirming the optimized model.

[0126] First, analyze the simulation results to identify areas that need optimization. These areas typically exhibit uneven interference response, incomplete coverage, or unstable test results. For example, heatmap analysis can visually identify hot and cold spots in the interference response; these are often the key areas requiring optimization.

[0127] Next, key tuning parameters are determined, including distances between test structures, connectivity relationships, and functional domain boundaries. Additionally, topological characteristics such as node centrality, clustering coefficient, path complexity, and network entropy must be considered. Node centrality, used to assess the importance of a node in the network, can be calculated using the following formula:

[0128] ,

[0129] in: Let be the centrality of node i, representing the number of connections between node i and other nodes, expressed in units of . These are elements of the adjacency matrix, with a value of 1 when node i and node j are connected, and a value of 0 otherwise. They are dimensionless. This represents the total number of nodes in the network, expressed in units. The summation variable ranges from 1 to n. Preferably, nodes with high centrality (typically those in the top 20% of the network's centrality values) should be given more attention, as they have a greater impact on the overall network performance.

[0130] Clustering coefficients are used to evaluate the degree of clustering of nodes and can be expressed as:

[0131] ,

[0132] in: is the clustering coefficient of node i, which represents the degree of connection between the neighbors of node i. It ranges from 0 to 1 and is dimensionless. Let i be the number of edges between the neighbors of node i, in units of 1; Let be the degree of node i (the number of nodes directly connected to it), expressed in units of . Preferably, for regions with high clustering coefficients (typically ), In areas where interference propagation is most severe, the density of test structures should be appropriately increased to better capture the characteristics of interference propagation. The clustering coefficient reflects the tightness of local connections in a network; a higher value indicates a tighter subnetwork formed around a node.

[0133] Path complexity is used to evaluate the characteristics of interference propagation paths and can be calculated from the average path length:

[0134] ,

[0135] in: The average path length represents the average shortest path length between any two nodes in the network, measured in hops. is the shortest path length between node i and node j, in hops. This represents the total number of nodes in the network, expressed in units. and Use node indexes to represent distinct nodes. Preferably, for networks with long average path lengths (e.g., Test points should be added along the critical path to ensure continuous monitoring of interference propagation. The average path length reflects the overall connectivity efficiency of the network; a smaller value indicates a more efficient network connection.

[0136] Network entropy is used to evaluate the determinism and stability of a network topology, and can be expressed as:

[0137] ,

[0138] in: Network entropy represents the uncertainty of network structure, and its unit is bits. Let be the normalized centrality of node i (the centrality of node i divided by the sum of the centralities of all nodes), which is dimensionless. This represents the total number of nodes in the network, expressed in units. Node indices range from 1 to n. Preferably, the network entropy value is low (typically...). This indicates a more deterministic and stable network structure, which is beneficial for obtaining reliable test results. Network entropy is a concept in information theory used to measure the uncertainty of a system; here, it is applied to evaluate the complexity of the network structure.

[0139] Based on the above parameter analysis, a topology adjustment scheme is generated. In this embodiment, the adjustment scheme mainly includes three aspects: first, adjusting the distance between test structures; second, optimizing the connection relationship between nodes; and third, re-dividing the functional domain boundaries. Preferably, the distance between test structures is adjusted within ±30% of the original distance; connection relationship optimization mainly considers increasing the connectivity of key nodes or removing redundant connections; functional domain boundary adjustment is based on interference propagation characteristics and may involve reassigning some nodes from one domain to another.

[0140] Next, according to the adjustment plan, the distances and connections between the test structures in the topology network interference model are gradually adjusted. An incremental adjustment strategy is adopted, with each adjustment controlled within a small range (e.g., 5% to 10%) to avoid instability caused by over-adjustment. After each adjustment, a rapid verification simulation is performed to evaluate the adjustment effect.

[0141] Finally, when the performance improvement falls below a preset threshold (typically 1% to 3%), confirm the final optimized test model. At this point, the model has reached a relatively stable state, and further adjustments will not yield significant benefits, so the optimization process can be terminated.

[0142] Based on the optimized test model, this invention performs a chip batch screening process. This process includes setting batch test parameters, connecting the chips under test, performing interference tests, collecting test data, evaluating anti-interference performance, and classifying the chips.

[0143] First, based on the optimized test model, batch test parameters are set. These parameters include test voltage, current range, interference intensity, frequency range, and test duration. Preferably, the test voltage is set to ±5% of the chip's rated voltage, the current range covers 50% to 150% of the chip's typical operating current, the interference intensity is ±20% of the rated voltage, the frequency range is from DC to 3 times the chip's operating frequency, and the test duration is 50ms to 200ms per test point.

[0144] Next, multiple chips under test are connected to the testing equipment in parallel. Preferably, for small chips (e.g., 8 to 64 pins), 16 to 32 chips can be tested simultaneously; for medium-sized chips (e.g., 64 to 256 pins), 8 to 16 chips can be tested simultaneously; and for large chips (256 pins or more), 4 to 8 chips can be tested simultaneously. Parallel testing can significantly improve screening efficiency.

[0145] Interference testing is performed on the chip under test according to the test structure and parameters in the optimized test model. During the test, different types and intensities of interference signals are applied sequentially in a preset order, and the chip's response is recorded. Preferably, the test order is usually arranged from low to high interference sensitivity, with relatively mild tests performed first, followed by more intense tests, to avoid causing permanent damage to the chip in the early stages.

[0146] Test data is collected for each chip, including voltage response, current distribution, and signal integrity. Voltage response reflects the chip's voltage stability under interference, current distribution reflects changes in the chip's internal current path, and signal integrity reflects the chip's functional normality. This data is typically recorded and displayed in the form of waveforms, numerical tables, or heatmaps.

[0147] Based on preset screening thresholds, the anti-interference performance of each chip is evaluated. These thresholds are typically based on the following aspects: first, voltage stability, requiring voltage fluctuations under interference conditions to not exceed ±10% of the rated voltage; second, current stability, requiring current fluctuations under interference conditions to not exceed ±20% of the typical value; and third, functional integrity, requiring critical functions to operate normally under interference conditions. Specific thresholds can be adjusted according to the chip's application scenario and reliability requirements.

[0148] Finally, chips that meet the anti-interference performance requirements are marked as qualified, and chips that do not meet the requirements are marked as unqualified. Preferably, chips can be further divided into three categories—high-performance, standard-performance, and low-performance—based on performance differences, for different application scenarios. For example, high-performance chips (anti-interference performance exceeding the requirements by more than 20%) can be used in critical safety systems; standard-performance chips (anti-interference performance meeting the requirements) can be used in general industrial applications; and low-performance chips (anti-interference performance slightly below the requirements but within an acceptable range) can be used in non-critical consumer electronics products.

[0149] like Figure 2 As shown, the present invention also provides a test and screening system for enhancing chip immunity to electrical interference, including a topology network construction module 1, an interference path construction module 2, a current distribution module 3, a simulation execution module 4, a topology optimization module 5, and a chip screening module 6.

[0150] The topology network construction module 1 is used to establish a topology network interference model. This model includes the topological connection relationships of the chip's power supply pins, ground pins, and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance. Preferably, the topology network construction module 1 includes a node mapping unit, a domain partitioning unit, and a connection relationship establishment unit, which are respectively responsible for the digital conversion of the chip's physical structure, functional domain partitioning, and the establishment of connection relationships between nodes.

[0151] Interference path construction module 2 is used to construct interference paths, including three key functions: First, connect the chip's power supply pins to the first analog ground pins and connect the chip's ground pins to the second analog ground pins to form a first set of test structures; second, select a set of consecutive positions from all the first analog ground pins, connect these positions together to form a first interference path, and connect the signal pins together based on this path to form a second set of test structures; third, select a set of consecutive positions from all the second analog ground pins, connect these positions together to form a second interference path, and connect the first signal pins to the second interference path based on this path to form a third set of test structures.

[0152] The current distribution module 3 is used to acquire current distribution parameters. Its functions include: determining the initial current value of each node in the topology network interference model based on the theoretical current value of the chip; acquiring the voltage value of each signal pin in the model, and calculating the voltage drop value of the chip based on the voltage values ​​of the signal pins and power supply pins; determining the test current value of each test structure based on the voltage drop value, and adding the corresponding current value at the corresponding position of each test structure in the model. Preferably, the current distribution module 3 also includes a current equalization evaluation unit for analyzing the uniformity of the current distribution and identifying abnormal regions.

[0153] Simulation execution module 4 is used to perform interference simulation tests and obtain simulation results of the topology network interference model. This module is responsible for setting interference simulation parameters, performing electromagnetic interference simulation, obtaining response results, extracting key indicators, and comparing them with preset conditions. Preferably, simulation execution module 4 supports a simulation method combining time and frequency domains to comprehensively capture the chip's response characteristics under different interference conditions.

[0154] Topology optimization module 5 is used to dynamically adjust the distances between test structures in the topology network interference model when the simulation results meet preset conditions, forming an optimized test model. This module analyzes the simulation results, determines key adjustment parameters, generates topology adjustment schemes, performs incremental adjustments, verifies the adjustment effects, and finally confirms the optimized model. Preferably, topology optimization module 5 adopts an iterative optimization strategy, performing rapid verification simulations after each adjustment to gradually approach the optimal solution.

[0155] The chip screening module 6 is used to perform batch chip screening based on the simulation results of the optimized test model. This module sets batch test parameters, controls the parallel testing of multiple chips under test, performs interference tests in a preset order, collects test data for each chip, evaluates anti-interference performance, and classifies the chips. Preferably, the chip screening module 6 has a high degree of automation and parallel processing capabilities, which can significantly improve batch screening efficiency.

[0156] The above modules can be implemented using a combination of software and hardware. The software component includes topology analysis algorithms, current distribution optimization algorithms, simulation control programs, and data processing programs; the hardware component includes high-performance computing servers, automated testing equipment, and data acquisition systems. These modules work together to form a complete chip anti-interference testing and screening system.

[0157] In a preferred embodiment of the present invention, the collected data includes the following categories: voltage data, used to evaluate the voltage stability of the chip under interference conditions, with a typical sampling rate of 10MHz to 100MHz; current data, used to analyze changes in the internal current distribution of the chip, with a sampling rate typically of 1MHz to 10MHz; signal integrity data, used to detect signal transmission quality, including parameters such as rise / fall time, overshoot / undershoot; functional response data, used to verify the normal functioning of the chip under interference, typically achieved through specific test vectors; and temperature data, used to monitor the thermal behavior of the chip during testing, with a sampling rate typically of 10Hz to 100Hz. All data are normalized and stored uniformly to ensure that data from different sources and with different dimensions can be comprehensively analyzed.

[0158] In practical applications, this system can be widely used for the testing and screening of electromagnetic interference immunity of various integrated circuits, especially suitable for fields with high reliability requirements such as automotive electronics, medical equipment, and aerospace. This system can significantly improve the testing accuracy and screening efficiency of chip electromagnetic interference immunity, providing strong support for chip quality control and reliability assurance.

[0159] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various modifications and variations can be made to the present invention by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principle of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method of test screening for enhancing immunity of a chip against electro-magnetic interference, characterized by, include: A topology network interference model is established, which includes the topological connection relationship of the chip's power supply pins, ground pins and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance. Constructing interference pathways, including: Connect the power supply pin of the chip to the first analog ground pin, and connect the ground pin of the chip to the second analog ground pin to form the first test structure; Select a set of consecutive locations from all the first analog ground pins, connect the consecutive locations together to form a first interference path, and connect the signal pins together based on the first interference path to form a second set of test structures; Select a set of consecutive positions from all the second analog ground pins, connect the consecutive positions together to form a second interference path, and connect the first signal pin to the second interference path based on the second interference path to form a third set of test structures; Obtain current distribution parameters, including: Based on the theoretical current value of the chip, determine the initial current value of each node in the topology network interference model; Obtain the voltage values ​​of each signal pin in the interference model of the topology network, and calculate the voltage drop of the chip based on the voltage values ​​of the signal pins and the voltage values ​​of the power supply pins; Based on the voltage drop value, the test current value of each test structure is determined, and the corresponding current value is added to the corresponding position of each test structure in the topology network interference model. Perform interference simulation tests to obtain the simulation results of the interference model of the topology network; When the simulation results meet the preset conditions, the distance between each test structure in the topology network interference model is dynamically adjusted to form an optimized test model. Based on the simulation results of the optimized test model, a batch screening of chips is performed.

2. The method of claim 1, wherein the method is characterized by, The steps for establishing the topology network interference model specifically include: The physical structure of the chip is converted into a set of digital nodes, with each pin mapped to a node in the topology network; Based on the functional blocks of the chip, the node is divided into a power domain, a ground domain, and a signal domain; Based on the chip's design specifications, establish the connections between nodes to form an initial topology graph; An interference source is added to the initial topology diagram, and the parameters of the interference source are set according to the rated voltage range of the chip and the interference distance.

3. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for constructing the interference pathway specifically include: Select consecutive locations with the highest connectivity from the first analog ground pin to form the first interference path; Cluster analysis is performed on the signal pins to identify sets of nodes sensitive to interference; Based on the set of nodes sensitive to interference, the second set of test structures is constructed, and the signal pins are connected together; Select consecutive locations with the highest interference propagation efficiency from the second analog ground pins to form the second interference path; The first signal pin is connected to the second interference path to form the third set of test structures.

4. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for obtaining the current distribution parameters specifically include: The theoretical current value is extracted from the chip's specifications. The theoretical current values ​​are used as edge weights of the topology network to construct an initial current distribution model; Obtain the voltage values ​​of each signal pin in the interference model of the topology network; Calculate the voltage drop of the chip based on the voltage values ​​of the signal pin and the power supply pin; Based on the voltage drop value and the connection relationship of the topology network, the current distribution in the network is calculated; Assess the uniformity of current distribution and identify anomalies and singular regions in the current distribution; Based on the anomalies and singular regions, determine the test current value for each test structure.

5. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The specific steps for performing the interference simulation test include: Set the interference simulation parameters, including interference source type, interference intensity, interference frequency, and duration; Perform electromagnetic interference simulation in the aforementioned topology network interference model; Obtain the response results of the interference model of the topology network; Extract key indicators such as interference response sensitivity, result consistency, coverage integrity, and screening accuracy; The key indicators are compared with preset conditions.

6. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The steps for dynamically adjusting the topology network interference model specifically include: Analyze the simulation results to identify areas that need optimization; Identify key adjustment parameters, including the distance between test structures, connection relationships, and functional domain boundaries; Generate a topology adjustment scheme; According to the adjustment scheme, the distances between the test structures in the topology network interference model are gradually adjusted; Verify the performance of the adjusted model; When the performance improvement is less than the preset threshold, confirm the final optimized test model.

7. The test and screening method for enhancing chip immunity to electrical interference according to claim 1, characterized in that, The step of performing batch chip screening based on the simulation results of the optimized test model specifically includes: Based on the optimized test model, set the batch test parameters; Connect multiple chips under test to the test equipment in parallel; Interference tests were performed on the multiple chips under test according to the test structure and parameters in the optimized test model. Collect test data for each chip, including voltage response, current distribution, and signal integrity; Based on preset screening thresholds, the anti-electrical interference performance of each chip is evaluated; Chips that meet the requirements for anti-electrical interference performance are marked as qualified, and chips that do not meet the requirements are marked as unqualified.

8. The test and screening method for enhancing chip immunity to electrical interference according to claim 5, characterized in that, The preset conditions include: Interference response sensitivity is in the range of 5% to 20%; The consistency rate of the results was higher than 98%; Coverage integrity is higher than 90%; The screening accuracy rate is higher than 97%.

9. The test and screening method for enhancing chip immunity to electrical interference according to claim 6, characterized in that, The key adjustment parameters also include: Node centrality is used to evaluate the importance of a node in a network. Clustering coefficient, used to evaluate the degree of clustering of nodes; Path complexity is used to evaluate the characteristics of interference propagation paths; Network entropy is used to evaluate the determinism and stability of a network topology.

10. A test and screening system for enhancing chip immunity to electrical interference, used to implement the test and screening method for enhancing chip immunity to electrical interference as described in any one of claims 1-9, characterized in that, include: The topology network construction module is used to establish a topology network interference model. The topology network interference model includes the topology connection relationship of the chip's power supply pins, ground pins, and signal pins, as well as interference source parameters. The interference source parameters are set according to the chip's rated voltage range and interference distance. An interference path construction module is used to construct interference paths, including: connecting the power supply pin of the chip to a first analog ground pin, and connecting the ground pin of the chip to a second analog ground pin to form a first set of test structures; selecting a set of consecutive positions from all the first analog ground pins, connecting the consecutive positions together to form a first interference path, and connecting signal pins together based on the first interference path to form a second set of test structures; selecting a set of consecutive positions from all the second analog ground pins, connecting the consecutive positions together to form a second interference path, and connecting a first signal pin to the second interference path based on the second interference path to form a third set of test structures; The current distribution module is used to acquire current distribution parameters, including: determining the initial current value of each node in the topology network interference model based on the theoretical current value of the chip; acquiring the voltage value of each signal pin in the topology network interference model, and calculating the voltage drop value of the chip based on the voltage values ​​of the signal pins and the voltage values ​​of the power supply pins; determining the test current value of each test structure based on the voltage drop value, and adding the corresponding current value at the corresponding position of each test structure in the topology network interference model; The simulation execution module is used to perform interference simulation tests and obtain the simulation results of the interference model of the topology network. The topology optimization module is used to dynamically adjust the distance between each test structure in the topology network interference model when the simulation results meet preset conditions, so as to form an optimized test model. The chip screening module is used to perform batch chip screening based on the simulation results of the optimized test model.

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