An instruction processing method, device, terminal device, and program product

Abstract

The application is suitable for the technical field of computer processor design, and provides an instruction processing method and device, terminal equipment and program product. The method comprises the following steps: acquiring instruction information of a to-be-processed instruction set in a processor; generating an index vector corresponding to the to-be-processed instruction set based on an original effective vector; respectively performing one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the to-be-processed instruction set, wherein each row of one-hot code vectors in the one-hot code matrix corresponds to each input instruction; and performing sorting processing on the operation code of each input instruction according to the original effective vector and the one-hot code matrix to obtain processed operation code information, so that the processor executes corresponding operations based on the processed operation code information. The method can meet the demand of high-performance processors to complete instruction processing in a single cycle, has low processing delay, and thus improves the instruction execution efficiency of the processor.

Description

Technical Field

[0001] This application belongs to the field of computer processor design technology, and in particular relates to an instruction processing method, apparatus, terminal device and program product. Background Technology

[0002] With the development of computer technology, processor performance has continuously improved, and instruction processing efficiency has become one of the key factors affecting processor performance. In modern high-performance processors, dispatching multiple instructions simultaneously is an important means to improve the processor's parallel processing capability. However, in practical applications, these simultaneously dispatched instructions may contain invalid instructions, resulting in a sparse instruction stream (i.e., valid instructions are not continuous, with invalid instructions interspersed). Therefore, there is an urgent need for an instruction processing method to effectively sort and compress instructions to improve instruction execution efficiency.

[0003] However, traditional instruction processing methods typically use serial shifting to compress and sort instructions. This method has high latency and cannot meet the requirements of high-performance processors to complete instruction processing in a single cycle, resulting in relatively low instruction execution efficiency. Summary of the Invention

[0004] This application provides an instruction processing method, apparatus, terminal device, and program product that can meet the requirements of high-performance processors to complete instruction processing in a single cycle and improve the instruction execution efficiency of the processor.

[0005] In a first aspect, embodiments of this application provide an instruction processing method, including: Obtain instruction information of the instruction set to be processed in the processor. The instruction information includes the original valid vector corresponding to the instruction set to be processed, and the opcode of each input instruction in the instruction set to be processed. Each element in the original valid vector is used to represent the validity of each input instruction. An index vector corresponding to the instruction set to be processed is generated based on the original valid vector. Each index value in the index vector is used to represent the initial arrangement position of each input instruction. Each index value in the index vector is converted into a one-hot code to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. Based on the original valid vector and the one-hot code matrix, the opcode of each input instruction is sorted to obtain the processed opcode information, so that the processor can execute the corresponding operation based on the processed opcode information.

[0006] In one possible implementation of the first aspect, the processed opcode information includes: the target opcode vector and the target valid vector; Based on the original valid vector and one-hot code matrix, the opcodes of each input instruction are sorted to obtain the processed opcode information, including: Based on the valid elements in the original valid vector and each column vector in the one-hot code matrix, the target opcode vector corresponding to the instruction set to be processed is generated. The target opcode vector is used to represent the opcode of each input instruction arranged consecutively in the execution order. Logical operations are performed on each element of the original valid vector and each column vector of the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector. Each element in the target valid vector is used to characterize the validity of the opcode at the corresponding position in the target opcode vector.

[0007] In one possible implementation of the first aspect, the target opcode vector corresponding to the instruction set to be processed is generated based on the valid elements in the original valid vector and each column vector in the one-hot code matrix, including: For each column vector in the one-hot code matrix, if a valid element is detected in each column vector, the target input instruction corresponding to each column vector is determined based on the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector, and the opcode of the target input instruction is determined as the target opcode corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no valid element in each column vector, the no-operation instruction is used to determine the target input instruction corresponding to each column vector, and the opcode of the no-operation instruction is used to determine the target opcode corresponding to each column vector. Based on the target opcodes corresponding to multiple column vectors, a target opcode vector corresponding to the instruction set to be processed is generated.

[0008] In one possible implementation of the first aspect, logical operations are performed on each element of the original valid vector and each column vector of the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector, including: For each column vector in the one-hot code matrix, perform a logical AND operation between each element in each column vector and each element in the original valid vector to obtain the first operation result for each column vector. For each column vector in the one-hot code matrix, perform a logical OR operation on the first operation results corresponding to each column vector to obtain the second operation result corresponding to each column vector; Based on the second operation results corresponding to multiple column vectors, the target effective vector corresponding to the instruction set to be processed is generated.

[0009] In one possible implementation of the first aspect, generating an index vector corresponding to the instruction set to be processed based on the original valid vector includes: For each element in the original valid vector, count the number of valid elements among all elements preceding each element to obtain the index value of the input instruction corresponding to each element; Based on the index values ​​of the input instructions corresponding to multiple elements, an index vector corresponding to the instruction set to be processed is generated.

[0010] In one possible implementation of the first aspect, a one-hot code transformation is performed on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed, including: Each index value in the index vector is used to shift the given binary value to the left to obtain the one-hot code vector corresponding to each index value. Based on the one-hot code vectors corresponding to multiple index values, a one-hot code matrix corresponding to the instruction set to be processed is generated.

[0011] In one possible implementation of the first aspect, the bit width of the binary value is set to be equal to the number of input instructions in the instruction set to be processed.

[0012] Secondly, embodiments of this application provide an instruction processing apparatus, including: The acquisition module is used to acquire instruction information of the instruction set to be processed in the processor. The instruction information includes the original valid vector corresponding to the instruction set to be processed, and the opcode of each input instruction in the instruction set to be processed. Each element in the original valid vector is used to represent the validity of each input instruction. The first generation module is used to generate an index vector corresponding to the instruction set to be processed based on the original valid vector. Each index value in the index vector is used to represent the initial arrangement position of each input instruction. The second generation module is used to perform one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. The processing module is used to sort the opcodes of each input instruction according to the original valid vector and the one-hot code matrix to obtain the processed opcode information, so that the processor can execute the corresponding operation based on the processed opcode information.

[0013] Thirdly, embodiments of this application provide a terminal device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the method as described in any of the first aspects.

[0014] Fourthly, embodiments of this application provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the method as described in any of the first aspects.

[0015] Fifthly, embodiments of this application provide a computer program product that, when run on a terminal device, causes the terminal device to execute any of the methods described in the first aspect above.

[0016] This application provides an instruction processing method, apparatus, terminal device, and program product. The method includes: acquiring instruction information of an instruction set to be processed in a processor, wherein the instruction information includes an original valid vector corresponding to the instruction set to be processed and an opcode for each input instruction in the instruction set to be processed, and each element in the original valid vector is used to represent the validity of each input instruction; generating an index vector corresponding to the instruction set to be processed based on the original valid vector, wherein each index value in the index vector is used to characterize the initial arrangement position of each input instruction; performing one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed, wherein each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction; and sorting the opcodes of each input instruction according to the original valid vector and the one-hot code matrix to obtain processed opcode information, so that the processor executes the corresponding operation based on the processed opcode information. By utilizing the above technical solution, a one-hot code matrix corresponding to the instruction set to be processed is generated by performing one-hot code conversion on each index value in the index vector generated based on the original valid vector. Furthermore, the opcodes of each input instruction are sorted according to the original valid vector and the one-hot code matrix to obtain the processed opcode information. This can meet the requirement of high-performance processors to complete instruction processing in a single cycle with low processing latency, thereby improving the instruction execution efficiency of the processor. Attached Figure Description

[0017] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0018] Figure 1 This is a flowchart illustrating an instruction processing method provided in an embodiment of this application; Figure 2 This is a flowchart illustrating an instruction processing method provided in another embodiment of this application; Figure 3 This is a schematic diagram of the overall architecture of an instruction processing method provided in another embodiment of this application; Figure 4 This is a structural block diagram of an instruction processing device provided in one embodiment of this application; Figure 5This is a schematic diagram of the structure of a terminal device provided in an embodiment of this application. Detailed Implementation

[0019] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0020] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0021] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0022] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0023] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0024] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0025] It can be assumed that in modern high-performance processors, especially superscalar processors, multiple instructions are typically dispatched to different execution units simultaneously each clock cycle during the instruction dispatch phase. However, due to dependencies or resource conflicts between instructions, invalid instructions may exist among these simultaneously dispatched multiple instructions, resulting in a sparse instruction stream (i.e., valid instructions are not continuous, with invalid instructions interspersed). Subsequent processing stages, such as reordering buffers or execution unit queues, typically expect to receive a continuous, uninterrupted stream of valid instructions to simplify logic design, improve resource utilization, and reduce power consumption. Therefore, there is an urgent need for an instruction processing method to effectively sort and compress instructions to improve instruction execution efficiency.

[0026] However, existing technologies have several limitations when processing sparse, multiplexed instruction streams. First, traditional instruction processing methods typically employ serial shifting to compress and sort instructions, resulting in high latency that fails to meet the demands of high-performance processors requiring instruction processing within a single cycle. Second, some solutions utilize complex multi-level selector networks for instruction compression and sorting, but the circuit area and wiring complexity increase dramatically with the number of instruction streams processed, hindering processor scalability and optimization. Furthermore, existing technologies often struggle to maintain instruction execution order while ensuring efficient processing when handling sparse instruction streams, potentially impacting the execution of programs that depend on instruction order.

[0027] In summary, existing technologies cannot efficiently compress sparse multi-input instructions into compact forward-aligned outputs within a single cycle. Furthermore, their implementation is complex, suffers from high latency, and is difficult to expand, making it hard to meet the instruction processing efficiency and flexibility requirements of modern high-performance processors. Therefore, how to efficiently sort and compress multi-input instructions while ensuring ease of processor expansion is a pressing issue that needs to be addressed.

[0028] Based on this, the embodiments of this application provide an instruction processing method that divides the entire processing process into three logically closely connected stages. Through an index generation mechanism based on a leading valid count, combined with a one-hot code mapping matrix and a parallel selection network, parallel compression sorting of multiple instructions is achieved. The entire compression sorting process is implemented through pure combinational logic circuits, completing the conversion from out-of-order sparse input to ordered compact output in a single cycle, thereby improving the instruction execution efficiency of the processor.

[0029] Figure 1 This is a flowchart illustrating an instruction processing method according to an embodiment of this application. It is intended as an example and not a limitation. This method can be applied to terminal devices, and the specific type of terminal device is not limited in any way, including but not limited to mobile phones, tablets, and other devices. Figure 1As shown, the method includes: S101. Obtain instruction information of the instruction set to be processed in the processor.

[0030] The instruction information includes the original valid vector corresponding to the instruction set to be processed, and the opcode of each input instruction in the instruction set to be processed. Each element in the original valid vector is used to represent the validity of each input instruction.

[0031] For example, the original valid vector can be a binary vector, where an element value of 1 indicates that the input instruction for the corresponding channel is valid, and an element value of 0 indicates that the input instruction for the corresponding channel is invalid. Furthermore, for a 3-channel instruction set, if its original valid vector is [1,0,1], it can indicate that the input instructions for channels 0 and 2 are valid, while the input instruction for channel 1 is invalid. The opcode for each input instruction can be a field within that instruction, used to specify the specific operation or command to be executed.

[0032] S102. Generate the index vector corresponding to the instruction set to be processed based on the original valid vector.

[0033] Each index value in the index vector is used to represent the initial arrangement position of each input instruction.

[0034] In this step, the index value of the input instruction corresponding to each element can be determined through a series of cumulative calculations, so that the final arrangement position of each input instruction can be obtained by adjusting the validity of the input instructions. Alternatively, a pre-trained neural network model can be used to directly obtain the index vector corresponding to the instruction set to be processed by inputting the original valid vector into the neural network model. Or, when the number of input instructions is small, the position of each input instruction in the final compressed output result can be directly calculated by detecting the validity of each input instruction in turn. For example, when the instruction set to be processed includes 3 input instructions and the original valid vector corresponding to the instruction set to be processed is [1,0,1], we can start detecting from the first index value in the index vector. If the index value is "1", we can determine that the corresponding zeroth input instruction is at position 0 in the final compressed output result. Then, if the second index value is "0", the corresponding first input instruction can be configured in the last position (i.e., position 2) in the final compressed output result. Finally, if the third index value is "1", the corresponding second input instruction can be configured in position 1 in the final compressed output result.

[0035] As a feasible implementation method, generating an index vector corresponding to the instruction set to be processed based on the original valid vector includes: for each element in the original valid vector, counting the number of valid elements among all elements preceding each element to obtain the index value of the input instruction corresponding to each element; and generating an index vector corresponding to the instruction set to be processed based on the index values ​​of the input instructions corresponding to multiple elements.

[0036] For example, a valid signal vector with a bit width of N is Vld[N-1:0], where each bit Vld[i] represents the validity of the i-th input instruction ("1" indicates valid, "0" indicates invalid). For the i-th instruction (i ranges from 0 to N-1), its index value Index[i] can be calculated by accumulating the valid signal values ​​of all input instructions with indices j less than i. That is, the value of Index[i] is equal to the number of valid instructions before the i-th instruction, which can be expressed mathematically as: Index[i]=Σ(Vld[j]), where the summation variable j ranges from 0 to i-1.

[0037] Therefore, an index vector Index[N-1:0] can be output, where each element Index[i] indicates the position of the corresponding i-th valid instruction at the output. The index value of an invalid instruction is determined by the number of valid instructions preceding it, but it will be filtered out in subsequent stages.

[0038] Furthermore, each element Index[i] is an M-bit binary number, M=ceil(log2(N)). For example, when N=5, M=3, and ceil() is the floor function.

[0039] More specifically, assuming the valid signal vector is [1,0,1,0,1], indicating that input instructions on channels 0, 2, and 4 are valid, while input instructions on channels 1 and 3 are invalid, then for the first element "1", there are no preceding elements, so the index value of input instruction 0 is 0; for the second element "0", since there is a preceding valid element, the index value of input instruction 1 is 1; similarly, the index value of input instruction 2 is also 1; for the fourth element "0", there are two preceding valid elements, so the index value of input instruction 3 is 2; similarly, the index value of input instruction 4 is also 2. Therefore, the generated index vector is [0,1,1,2,2], which means that instruction 0 should be placed at position 0, instruction 2 should be placed at position 1, and instruction 4 should be placed at position 2.

[0040] In practical applications, this step can be implemented using a parallel prefix sum computation network, which consists of a series of adders that can simultaneously compute the index values ​​of all input instructions, achieving low latency.

[0041] S103. Perform one-hot code conversion on each index value in the index vector to generate the one-hot code matrix corresponding to the instruction set to be processed.

[0042] Each row of the one-hot code matrix corresponds to a one-hot code vector for each input instruction.

[0043] This step converts the index vector calculated in the previous step into a one-hot code matrix, providing a clear gating signal for subsequent data selection. The specific processing may include: for each index value Index[i], converting it into an N-bit wide one-hot code vector OneHotVec[i], and then combining them to obtain the one-hot code matrix corresponding to the instruction set to be processed. The specific method of converting the index values ​​is not limited here. For example, since one-hot code is a binary encoding form, its characteristic is that only one bit is 1 at a time, and the rest are all 0. Therefore, different conversion methods correspond to different parity of each index value. Alternatively, the index values ​​can be analyzed to convert them into one-hot code vectors. For example, for the index value... Its corresponding one-hot code vector can be 00100, while the index value The corresponding one-hot code vector can be 01000.

[0044] As a feasible implementation method, one-hot code conversion is performed on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed. This includes: using each index value in the index vector to shift a set binary value to the left to obtain a one-hot code vector corresponding to each index value; and generating a one-hot code matrix corresponding to the instruction set to be processed based on the one-hot code vectors corresponding to multiple index values.

[0045] In this embodiment, the specific conversion rule for the index value is as follows: First, an N-bit binary number (i.e., a binary value is set) is generated. Only one bit of this binary number is 1, and the rest are 0. Then, the one-hot code conversion of each index value is achieved by shifting the binary number to the left by Index[i] bits, so as to obtain the one-hot code vector corresponding to each index value. Then, an N×N one-hot code matrix OneHotVec is formed. Each row of the one-hot code matrix OneHotVec[i] corresponds to one original input instruction. The position of "1" in the one-hot code matrix indicates which position of the corresponding input instruction in that row is entitled to "contribute" to the output.

[0046] For example, when the set binary value is a constant "1" with a bit width of 5 and the index vector is [0,1,1,2,2], the one-hot code vector corresponding to the 0-th channel input instruction is 00001<<Index[0]=

[00001] ; the one-hot code vector corresponding to the 1st channel input instruction is 00001<<Index[1]=

[00010] ; the one-hot code vector corresponding to the 2nd channel input instruction is 00001<<Index[1]=

[00010] ; the one-hot code vector corresponding to the 3rd channel input instruction is 00001<<Index[2]=

[00100] ; the one-hot code vector corresponding to the 4th channel input instruction is 00001<<Index[2]=

[00100] , so the one-hot code matrix OneHotVec can be formed as .

[0047] In practical applications, this step can essentially be implemented by a parallel decoder array to decode M-bit index values into N-bit one-hot codes, with regular circuit and easy implementation.

[0048] Optionally, for facilitating subsequent sorting processing of the operation codes of each channel input instruction according to the original valid vector and the one-hot code matrix, the set bit width of the binary value can be equal to the number of input instructions in the instruction set to be processed.

[0049] S104: According to the original valid vector and the one-hot code matrix, perform sorting processing on the operation codes of each channel input instruction to obtain processed operation code information, so that the processor performs corresponding operations based on the processed operation code information.

[0050] This step can realize parallel selection of each compressed output result from all input instructions by sorting the operation codes of each channel input instruction. The specific process can be, for example, rearranging the operation codes of each channel input instruction according to the positions and validity indicated by the one-hot code matrix to obtain a sorted operation code sequence, or the processed operation code information can also be obtained by performing certain logical operations on elements in the original valid vector and the one-hot code matrix, which will not be further elaborated in this embodiment, as long as the processed operation code information can be obtained.

[0051] The instruction processing method provided in this embodiment generates a one-hot code matrix corresponding to the instruction set to be processed by performing one-hot code conversion on each index value in the index vector generated based on the original valid vector, and performs sorting processing on the operation codes of each channel input instruction according to the original valid vector and the one-hot code matrix to obtain processed operation code information, which can meet the requirement of a high-performance processor to complete instruction processing in a single cycle with low processing delay, thereby improving the instruction execution efficiency of the processor.

[0052] Figure 2 This is a flowchart illustrating an instruction processing method according to another embodiment of this application. In this embodiment, the processed opcode information includes a target opcode vector and a target valid vector. The opcodes of each input instruction are sorted according to the original valid vector and the one-hot code matrix. The resulting processed opcode information is further optimized as follows: A target opcode vector corresponding to the instruction set to be processed is generated based on the valid elements in the original valid vector and each column vector in the one-hot code matrix. The target opcode vector represents the opcodes of each input instruction arranged sequentially in execution order. Logical operations are performed on each element in the original valid vector and each column vector in the one-hot code matrix to generate a target valid vector corresponding to the target opcode vector. Each element in the target valid vector represents the validity of the opcode at the corresponding position in the target opcode vector. Figure 2 As shown, the method includes: S201. Obtain instruction information of the instruction set to be processed in the processor.

[0053] S202. Generate the index vector corresponding to the instruction set to be processed based on the original valid vector.

[0054] S203. Perform one-hot code conversion on each index value in the index vector to generate the one-hot code matrix corresponding to the instruction set to be processed.

[0055] S204. Based on the valid elements in the original valid vector and each column vector in the one-hot code matrix, generate the target opcode vector corresponding to the instruction set to be processed.

[0056] The target opcode vector is used to represent the opcode of each input instruction arranged sequentially in the execution order.

[0057] In this embodiment, the opcode PackedOp[k] for each bit after compression and sorting can be generated by an N-to-1 multiplexer. The selection signal of the multiplexer is specifically determined by the valid elements in the original valid vector and each column vector in the one-hot code matrix. For example, it can be composed of the operation result of OneHotVec[j][k] & Vld[j] for all j. Due to the characteristics of one-hot codes, at any given time, at most one instruction j will satisfy (OneHotVec[j][k] & Vld[j]) as true. Therefore, this step is logically equivalent to a data selector that selects the only correct instruction opcode from all input instructions and assigns it to PackedOp[k].

[0058] As a feasible implementation method, based on the valid elements in the original valid vector and each column vector in the one-hot code matrix, a target opcode vector corresponding to the instruction set to be processed is generated, including: For each column vector in the one-hot code matrix, if a valid element is detected in each column vector, the target input instruction corresponding to each column vector is determined based on the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector, and the opcode of the target input instruction is determined as the target opcode corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no valid element in each column vector, the no-operation instruction is used to determine the target input instruction corresponding to each column vector, and the opcode of the no-operation instruction is used to determine the target opcode corresponding to each column vector. Based on the target opcodes corresponding to multiple column vectors, a target opcode vector corresponding to the instruction set to be processed is generated.

[0059] Specifically, the target input instruction corresponding to each column vector can be determined in different ways based on whether there are valid elements in the column vectors of the one-hot code matrix. The opcode of the determined target input instruction is then identified as the target opcode for each column vector. Furthermore, the target opcodes can be compressed and sorted sequentially according to the column identifiers to form the target opcode vector corresponding to the instruction set to be processed. For example, if a column vector contains a valid element, the row identifier of the valid element and the element identifier of the valid element in the original valid vector can be checked for a common identifier. If a common identifier exists, the input instruction corresponding to that common identifier is identified as the target input instruction for that column vector. If no common identifier exists, or if there are no valid elements in the column vector, a no-operation instruction is identified as the target input instruction for that column vector. A no-operation instruction can be a command in the computer instruction system that does not perform an actual operation but occupies an instruction position. In this embodiment, a no-operation instruction can be understood as an invalid input instruction.

[0060] For example, when the input instruction is an opcode vector of Opcode[N-1:0], for k=0 (the first position after compression and sorting), that is, for the first column vector

[00001] in the one-hot code matrix, the row identifier of the valid element is j=0, and the element identifiers of the valid elements in the original valid vector [1,0,1,0,1] are j=0, j=2, j=4. That is, only OneHotVec[0][0]==1 and Vld[0]==1. At this time, the opcode of the 0th input instruction can be placed in the first position of the target opcode vector.

[0061] For k=1 (the second position after compression and sorting): that is, for the second column vector

[01100] in the one-hot code matrix, the row identifiers of the valid elements are j=1 and j=2, and the element identifiers of the valid elements in the original valid vector [1,0,1,0,1] are j=0, j=2 and j=4. That is, OneHotVec[1][1] and [2][1] are both 1, but only the second input instruction (j=2) is valid. Therefore, the opcode of the second input instruction is finally selected and placed in the second position of the target opcode vector.

[0062] For k=2 (the third position after compression and sorting): For the third column vector

[00011] in the one-hot code matrix, the row identifiers of the valid elements are j=3 and j=4. At the same time, the element identifiers of the valid elements in the original valid vector [1,0,1,0,1] are j=0, j=2, and j=4. That is, OneHotVec[3][2] and [4][2] are 1, but only the fourth input instruction (j=4) is valid. Therefore, the opcode of the fourth input instruction is finally selected and placed in the third position of the target opcode vector.

[0063] For k=3 and 4: Since there are no valid elements in the third and fourth column vectors of the one-hot code matrix, the opcode of the no-operation instruction can be placed in the fourth and fifth bits of the target opcode vector. For example, the opcode of the no-operation instruction can be 0.

[0064] In summary, the target opcode vector PackedOp=[Op0,Op2,Op4,0,0] represents the opcode of each of the input instructions arranged sequentially in the execution order.

[0065] S205. Perform logical operations on each element of the original valid vector and each column vector in the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector.

[0066] Each element in the target valid vector is used to characterize the validity of the opcode at the corresponding position in the target opcode vector.

[0067] In this embodiment, after compression and sorting, each valid signal PackedVld[k] can be obtained by performing a logical OR operation on all signals that satisfy the condition (OneHotVec[j][k]&Vld[j]) as true. This means that as long as any instruction j is mapped to position k and is valid, then PackedVld[k] is valid.

[0068] As a feasible implementation method, logical operations are performed on each element of the original effective vector and each column vector of the one-hot code matrix to generate the target effective vector corresponding to the target opcode vector, including: For each column vector in the one-hot code matrix, perform a logical AND operation between each element in each column vector and each element in the original valid vector to obtain the first operation result for each column vector. For each column vector in the one-hot code matrix, perform a logical OR operation on the first operation results corresponding to each column vector to obtain the second operation result corresponding to each column vector; Based on the second operation results corresponding to multiple column vectors, the target effective vector corresponding to the instruction set to be processed is generated.

[0069] Specifically, the target effective vector can be obtained by performing a bitwise AND operation on each element of the one-hot code matrix with the corresponding element of the original effective vector to obtain the first operation result, and then performing a bitwise OR operation on each of the first operation results to obtain the second operation result for each column, thus forming the target effective vector PackedVld. For example, each element of the target effective vector can be calculated as follows: PackedVld[0]=OneHotVec[0][0]&Vld[0]+OneHotVec[1][0]&Vld[1]+OneHotVec[2][0]&Vld[2]+OneHotVec[3][0]&Vld[3]+OneHotVec[4][0]&Vld[4]=1.

[0070] PackedVld[1]=OneHotVec[0][1]&Vld[0]+OneHotVec[1][1]&Vld[1]+OneHotVec[2][1]&Vld[2]+OneHotVec[3][1]&Vld[3]+OneHotVec[4][1]&Vld[4]=1.

[0071] PackedVld[2]=OneHotVec[0][2]&Vld[0]+OneHotVec[1][2]&Vld[1]+OneHotVec[2][2]&Vld[2]+OneHotVec[3][2]&Vld[3]+OneHotVec[4][2]&Vld[4]=1.

[0072] PackedVld[3]=OneHotVec[0][3]&Vld[0]+OneHotVec[1][3]&Vld[1]+OneHotVec[2][3]&Vld[2]+OneHotVec[3][3]&Vld[3]+OneHotVec[4][3]&Vld[4]=0.

[0073] PackedVld[4]=OneHotVec[0][4]&Vld[0]+OneHotVec[1][4]&Vld[1]+OneHotVec[2][4]&Vld[2]+OneHotVec[3][4]&Vld[3]+OneHotVec[4][4]&Vld[4]=0.

[0074] In summary, the target valid vector PackedVld=[1,1,1,0,0] is used to characterize the validity of the opcode at the corresponding position in the target opcode vector, that is, the first three positions are valid.

[0075] As can be seen, the compressed target valid vector PackedVld[N-1:0] is characterized by all valid bits "1" being consecutively arranged in the lower bits (forward aligned), and invalid bits "0" in the higher bits; the compressed target opcode vector PackedOp[N-1:0] contains the opcode of the k-th valid instruction in the original input. Based on this, when a column vector of the one-hot code matrix contains a valid element (value 1), and the element in the original valid vector corresponding to that valid element is also valid (value 1), the element at the corresponding position in the target valid vector is valid (value 1). This ensures that only truly valid opcodes are marked as valid in the target opcode vector.

[0076] This embodiment provides an instruction processing method that effectively generates a compact and ordered target opcode vector by filtering each column vector in the one-hot code matrix bit by bit with the original valid vector. The validity of each opcode is identified by the target valid vector, providing a clear data structure for subsequent instruction execution, further improving the efficiency of instruction processing and simplifying subsequent processing logic.

[0077] Figure 3 This is a schematic diagram of the overall architecture of an instruction processing method provided in another embodiment of this application, as shown below. Figure 3As shown, the input data can include the opcodes of N input instructions and the original valid vectors. The specific instruction processing can consist of three core stages in sequence. The hardware device can correspondingly include three main logic modules: a parallel position index calculation module, a one-hot code mapping matrix generation module, and a parallel multiplexing output module. The parallel position index calculation module is used to calculate the index vector of each input instruction in the final compressed sorting result. Specifically, it can calculate how many valid instructions precede each input instruction, and this number is the compressed position index of the input instruction. The one-hot code mapping matrix generation module is used to convert the index vector calculated in the first stage into a one-hot code matrix, providing a clear selection signal for subsequent data selection. For example, each index value in the index vector can be converted into a one-hot code vector to generate a one-hot code matrix. For example, the index value 2 at position 2 can be converted into a one-hot code vector

[00100] .

[0078] The parallel multiplexing output module is used to select the compressed output result of each path from all input instructions in parallel based on the one-hot code matrix. For example, the one-hot code matrix and the original valid vector can be filtered bit by bit, and the output is a compact and ordered instruction group (target opcode vector; target valid vector). Subsequent processing stages can then perform corresponding operations on the opcodes of corresponding bits in the target valid vector based on the validity of each bit. The target opcode vector can be determined based on the row identifier of the valid elements in each column vector and the element identifier of the valid elements in the original valid vector. The target valid vector can be determined by performing a logical AND operation between the elements of each column in the one-hot code matrix and the corresponding elements in the original valid vector, followed by a logical OR operation.

[0079] As can be seen from the above description, the instruction processing method provided in this embodiment can dynamically compress and sort multiple potentially out-of-order valid input instructions into a continuous and compact forward-aligned format, eliminating gaps between invalid instructions. This solves the problems of existing technologies being unable to efficiently compress sparse multiple input instructions into a compact forward-aligned output in a single cycle, and having complex circuitry, high latency, and difficulty in expansion.

[0080] Specifically, the beneficial effects of the instruction processing method provided in this embodiment are as follows: 1. High performance and low latency: The entire compression sorting process is implemented through pure combinational logic circuits and can be completed within one clock cycle, making it suitable for high-frequency operations in processor pipelines and significantly reducing instruction dispatch latency.

[0081] 2. True parallel processing: Unlike serial shifting methods, all three stages in this embodiment adopt a parallel computing structure, with each instruction being processed simultaneously. The path delay is relatively balanced and does not change with the effective mode of the input instruction.

[0082] 3. Regular structure and easy expansion: The structures of the three hardware devices mentioned above are all very regular (adder array, decoder array, selector array). When the number of channels N to be processed increases, the scale of each array can be expanded proportionally, which has strong scalability.

[0083] 4. Strong functional correctness: The index generation algorithm based on the leading valid count mathematically guarantees that the order of compressed instructions is completely consistent with the order of appearance of valid instructions in the original input, thus achieving lossless compression and sorting.

[0084] 5. Simplified subsequent design: The compact forward-aligned output format generated in this embodiment greatly simplifies the design of subsequent processing units (such as execution unit queues, renaming logic, etc.).

[0085] Corresponding to the instruction processing method in the above embodiments, Figure 4 This is a structural block diagram of an instruction processing device provided in one embodiment of this application. For ease of explanation, only the parts related to the embodiment of this application are shown.

[0086] Reference Figure 4 The device includes: The acquisition module 301 is used to acquire instruction information of the instruction set to be processed in the processor. The instruction information includes the original valid vector corresponding to the instruction set to be processed and the opcode of each input instruction in the instruction set to be processed. Each element in the original valid vector is used to represent the validity of each input instruction. The first generation module 302 is used to generate an index vector corresponding to the instruction set to be processed based on the original valid vector. Each index value in the index vector is used to represent the initial arrangement position of each input instruction. The second generation module 303 is used to perform one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. The processing module 304 is used to sort the opcodes of each input instruction according to the original valid vector and the one-hot code matrix to obtain the processed opcode information, so that the processor can execute the corresponding operation based on the processed opcode information.

[0087] This embodiment provides an instruction processing device that acquires instruction information of a set of instructions to be processed in a processor through an acquisition module. The instruction information includes the original valid vector corresponding to the set of instructions to be processed and the opcode of each input instruction in the set of instructions to be processed. Each element in the original valid vector represents the validity of each input instruction. A first generation module generates an index vector corresponding to the set of instructions to be processed based on the original valid vector. Each index value in the index vector represents the initial arrangement position of each input instruction. A second generation module performs one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the set of instructions to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. A processing module sorts the opcodes of each input instruction according to the original valid vector and the one-hot code matrix to obtain processed opcode information, so that the processor can execute the corresponding operation based on the processed opcode information. Using this device, a one-hot code matrix corresponding to the instruction set to be processed is generated by performing one-hot code conversion on each index value in the index vector generated based on the original valid vector. Then, the opcode of each input instruction is sorted according to the original valid vector and the one-hot code matrix to obtain the processed opcode information. This can meet the requirements of high-performance processors to complete instruction processing in a single cycle with low processing latency, thereby improving the instruction execution efficiency of the processor.

[0088] Optionally, the processed opcode information includes: the target opcode vector and the target valid vector; The processing module includes: The first vector generation unit is used to generate a target opcode vector corresponding to the instruction set to be processed based on the valid elements in the original valid vector and each column vector in the one-hot code matrix. The target opcode vector is used to represent the opcode of each input instruction arranged in the execution order. The second vector generation unit is used to perform logical operations on each element in the original valid vector and each column vector in the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector. Each element in the target valid vector is used to characterize the validity of the opcode at the corresponding position in the target opcode vector.

[0089] Optionally, the first vector generation unit is specifically used for: For each column vector in the one-hot code matrix, if a valid element is detected in each column vector, the target input instruction corresponding to each column vector is determined based on the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector, and the opcode of the target input instruction is determined as the target opcode corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no valid element in each column vector, the no-operation instruction is used to determine the target input instruction corresponding to each column vector, and the opcode of the no-operation instruction is used to determine the target opcode corresponding to each column vector. Based on the target opcodes corresponding to multiple column vectors, a target opcode vector corresponding to the instruction set to be processed is generated.

[0090] Optionally, the second vector generation unit is specifically used for: For each column vector in the one-hot code matrix, perform a logical AND operation between each element in each column vector and each element in the original valid vector to obtain the first operation result for each column vector. For each column vector in the one-hot code matrix, perform a logical OR operation on the first operation results corresponding to each column vector to obtain the second operation result corresponding to each column vector; Based on the second operation results corresponding to multiple column vectors, the target effective vector corresponding to the instruction set to be processed is generated.

[0091] Optionally, the first generation module is specifically used for: For each element in the original valid vector, count the number of valid elements among all elements preceding each element to obtain the index value of the input instruction corresponding to each element; Based on the index values ​​of the input instructions corresponding to multiple elements, an index vector corresponding to the instruction set to be processed is generated.

[0092] Optionally, the second generation module is specifically used for: Each index value in the index vector is used to shift the given binary value to the left to obtain the one-hot code vector corresponding to each index value. Based on the one-hot code vectors corresponding to multiple index values, a one-hot code matrix corresponding to the instruction set to be processed is generated.

[0093] Optionally, the bit width of the binary value can be set to be equal to the number of input instructions in the instruction set to be processed.

[0094] It should be noted that the information interaction and execution process between the above-mentioned devices / units are based on the same concept as the method embodiments of this application. For details on their specific functions and technical effects, please refer to the method embodiments section, and they will not be repeated here.

[0095] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of functional units and modules is merely an example. In practical applications, the above functions can be assigned to different functional units and modules as needed, that is, the internal structure of the device can be divided into different functional units or modules to complete all or part of the functions described above. The functional units and modules in the embodiments can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit. Furthermore, the specific names of the functional units and modules are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the units and modules in the above system can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0096] Figure 5 This is a schematic diagram of the structure of a terminal device provided in one embodiment of this application, as shown below. Figure 5 As shown, the terminal device 500 of this embodiment includes: at least one processor 502 ( Figure 5 (Only one is shown) a processor, a memory 501, and a computer program 503 stored in the memory 501 and executable on at least one processor 502. When the processor 502 executes the computer program 503, it implements the steps in the control method embodiments of any of the above-described application programs.

[0097] Terminal device 500 can be a computing device such as a desktop computer, laptop, handheld computer, or cloud server. This terminal device may include, but is not limited to, a processor 502 and a memory 501. Those skilled in the art will understand that... Figure 5 This is merely an example of terminal device 500 and does not constitute a limitation on terminal device 500. It may include more or fewer components than shown in the figure, or combine certain components, or different components, such as input / output devices, network access devices, etc.

[0098] The processor 502 may be a Central Processing Unit (CPU), or it may be other general-purpose processors, digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or any conventional processor.

[0099] In some embodiments, memory 501 may be an internal storage unit of terminal device 500, such as a hard disk or memory of terminal device 500. In other embodiments, memory 501 may be an external storage device of terminal device 500, such as a plug-in hard disk, smart media card (SMC), secure digital (SD) card, flash card, etc., equipped on terminal device 500. Furthermore, memory 501 may include both internal and external storage units of terminal device 500. Memory 501 is used to store operating system, applications, boot loader, data, and other programs, such as program code for computer programs. Memory 501 can also be used to temporarily store data that has been output or will be output.

[0100] This application also provides a computer-readable storage medium storing a computer program, which, when executed by processor 502, can implement the steps in the above-described method embodiments.

[0101] This application provides a computer program product that, when run on a terminal device, enables the terminal device to implement the steps described in the various method embodiments.

[0102] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a computer-readable storage medium, and when executed by the processor 502, it can implement the steps of the various method embodiments described above. The computer program includes computer program code, which can be in the form of source code, object code, executable files, or certain intermediate forms. The computer-readable storage medium can include at least: any entity or device capable of carrying computer program code to a device / terminal device, a recording medium, a computer memory, a read-only memory (ROM), a random access memory (RAM), an electrical carrier signal, a telecommunication signal, and a software distribution medium. Examples include USB flash drives, portable hard drives, magnetic disks, or optical disks.

[0103] In the above embodiments, the descriptions of each embodiment have different focuses. For parts that are not described in detail or recorded in a certain embodiment, please refer to the relevant descriptions of other embodiments.

[0104] Those skilled in the art will recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0105] In the embodiments provided in this application, it should be understood that the disclosed apparatus / terminal devices and methods can be implemented in other ways. For example, the apparatus / terminal device embodiments described above are merely illustrative. For instance, the division of modules or units is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between devices or units may be electrical, mechanical, or other forms.

[0106] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0107] The above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. An instruction processing method, characterized in that, include: Obtain instruction information of the instruction set to be processed in the processor, wherein the instruction information includes the original valid vector corresponding to the instruction set to be processed, and the opcode of each input instruction in the instruction set to be processed, and each element in the original valid vector is used to represent the validity of each input instruction. Based on the original valid vector, an index vector corresponding to the instruction set to be processed is generated, and each index value in the index vector is used to represent the initial arrangement position of each input instruction. Each index value in the index vector is converted into a one-hot code to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. Based on the original valid vector and the one-hot code matrix, the opcode of each input instruction is sorted to obtain processed opcode information, so that the processor can perform the corresponding operation based on the processed opcode information. The step of performing one-hot code transformation on each index value in the index vector to generate the one-hot code matrix corresponding to the instruction set to be processed includes: Each index value in the index vector is used to shift the set binary value to the left to obtain the one-hot code vector corresponding to each index value. Based on the one-hot code vectors corresponding to the multiple index values, generate the one-hot code matrix corresponding to the instruction set to be processed; The processed opcode information includes: the target opcode vector and the target valid vector; The step of sorting the opcodes of each input instruction based on the original valid vector and the one-hot code matrix to obtain processed opcode information includes: Based on the valid elements in the original valid vector and each column vector in the one-hot code matrix, a target opcode vector corresponding to the instruction set to be processed is generated. The target opcode vector is used to represent the opcode of each input instruction arranged consecutively in the execution order. Logical operations are performed on each element of the original valid vector and each column vector of the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector. Each element of the target valid vector is used to characterize the validity of the opcode at the corresponding position in the target opcode vector.

2. The instruction processing method as described in claim 1, characterized in that, The step of generating the target opcode vector corresponding to the instruction set to be processed based on the valid elements in the original valid vector and each column vector in the one-hot code matrix includes: For each column vector in the one-hot code matrix, if a valid element is detected in each column vector, the target input instruction corresponding to each column vector is determined according to the row identifier of the valid element in each column vector and the element identifier of the valid element in the original valid vector, and the opcode of the target input instruction is determined as the target opcode corresponding to each column vector. For each column vector in the one-hot code matrix, if it is detected that there is no valid element in each column vector, then the no-operation instruction is used to determine the target input instruction corresponding to each column vector, and the opcode of the no-operation instruction is used to determine the target opcode corresponding to each column vector. Based on the target opcodes corresponding to the multiple column vectors, a target opcode vector corresponding to the instruction set to be processed is generated.

3. The instruction processing method as described in claim 1, characterized in that, The step of performing logical operations on each element of the original valid vector and each column vector of the one-hot code matrix to generate the target valid vector corresponding to the target opcode vector includes: For each column vector in the one-hot code matrix, perform a logical AND operation between each element of each column vector and each element of the original valid vector to obtain the first operation result corresponding to each column vector; For each column vector in the one-hot code matrix, perform a logical OR operation on each of the first operation results corresponding to each column vector to obtain the second operation result corresponding to each column vector; Based on the second operation results corresponding to the multiple column vectors, a target effective vector corresponding to the instruction set to be processed is generated.

4. The instruction processing method according to any one of claims 1-3, characterized in that, The step of generating the index vector corresponding to the instruction set to be processed based on the original valid vector includes: For each element in the original valid vector, count the number of valid elements among all elements preceding each element to obtain the index value of the input instruction corresponding to each element; Based on the index values ​​of the input instructions corresponding to the multiple elements, an index vector corresponding to the instruction set to be processed is generated.

5. The instruction processing method as described in claim 1, characterized in that, The bit width of the set binary value is equal to the number of input instructions in the instruction set to be processed.

6. An instruction processing device, characterized in that, include: The acquisition module is used to acquire instruction information of the instruction set to be processed in the processor. The instruction information includes the original valid vector corresponding to the instruction set to be processed and the opcode of each input instruction in the instruction set to be processed. Each element in the original valid vector is used to represent the validity of each input instruction. The first generation module is used to generate an index vector corresponding to the instruction set to be processed based on the original valid vector, wherein each index value in the index vector is used to characterize the initial arrangement position of each input instruction. The second generation module is used to perform one-hot code conversion on each index value in the index vector to generate a one-hot code matrix corresponding to the instruction set to be processed. Each row of the one-hot code vector in the one-hot code matrix corresponds to each input instruction. The processing module is used to sort the opcodes of each input instruction according to the original valid vector and the one-hot code matrix to obtain processed opcode information, so that the processor can perform the corresponding operation based on the processed opcode information; Specifically, the second generation module is used for: Each index value in the index vector is used to shift the set binary value to the left to obtain the one-hot code vector corresponding to each index value. Based on the one-hot code vectors corresponding to the multiple index values, generate the one-hot code matrix corresponding to the instruction set to be processed; The processed opcode information includes: the target opcode vector and the target valid vector; The processing module includes: The first vector generation unit is used to generate a target opcode vector corresponding to the instruction set to be processed based on the valid elements in the original valid vector and each column vector in the one-hot code matrix. The target opcode vector is used to represent the opcode of each input instruction arranged consecutively in the execution order. The second vector generation unit is used to perform logical operations on each element of the original valid vector and each column vector of the one-hot code matrix to generate a target valid vector corresponding to the target opcode vector. Each element of the target valid vector is used to characterize the validity of the opcode at the corresponding position in the target opcode vector.

7. A terminal device, comprising a processor, a memory, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it causes the terminal device to implement the method as described in any one of claims 1-5.

8. A computer program product, characterized in that, When the computer program product is run on a terminal device, it causes the terminal device to perform the method as described in any one of claims 1-5.

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