An embedded system two-stage fusion starting method, device, equipment and medium

Abstract

The application discloses a two-stage fusion starting method, device and equipment for an embedded system and a medium. The method comprises the following steps: performing basic environment configuration through an SPL layer, selecting a BL1 starting medium and checking a BL1 image, and jumping to the BL1 layer after the checking is passed; initializing system resources and an interrupt mechanism through the BL1 layer, building a multitask running environment, and creating and concurrently executing a target task based on the multitask running environment. The image position can be accurately located and the integrity of the image can be ensured through the checking of the image, and starting abnormity can be prevented. Hardware support can be provided for multitask running and interrupt response through the initialization of the system resources and the interrupt mechanism, and the response capability of the system to hardware events can be improved. The multitask running environment can be built, the single-task linear execution limit can be broken, parallel processing can be supported, and the starting efficiency can be improved. The target task can be concurrently executed, the serial waiting time can be reduced, the task and the interrupt can be accurately associated, and resource waste can be avoided.

Description

Technical Field

[0001] This invention relates to the field of embedded systems, and in particular to a two-level fusion startup method, apparatus, device and medium for embedded systems. Background Technology

[0002] In the field of embedded systems, especially in lightweight chips based on the ARM Cortex-M3 architecture, the design of the boot process directly affects the system's boot efficiency, reliability, and maintainability. Embedded systems typically undergo a multi-stage boot process, starting with the lowest-level Bootrom, gradually loading higher-level bootloaders, and finally launching the operating system or application.

[0003] In the current technology, there are three types of solutions for BL1 booting on the Cortex-M3 platform: First, trusted firmware (ArmTrusted Firmware, ATF), which supports multi-core and secure switching, but has a large amount of code, complex dependencies, and high RAM consumption, making it unsuitable for scenarios with limited resources; second, U-Boot SPL independent booting, which supports multiple platforms, but lacks task scheduling and interrupt handling, cannot perform concurrent operations, and is difficult to extend peripheral drivers and scheduling mechanisms; third, FreeRTOS directly serves as the bootloader, which can perform multi-task scheduling, but the boot chain is imperfect and lacks image loading and security management capabilities. Summary of the Invention

[0004] This invention provides a two-level fusion startup method, apparatus, device, and medium for embedded systems. It realizes a startup process with multi-task and interrupt linkage through a two-level fusion startup architecture, solving the technical problems of low startup efficiency, poor maintainability, and untimely interrupt response in resource-constrained embedded platforms.

[0005] According to one aspect of the present invention, a two-level fused boot method for embedded systems is provided, applied to a fused boot architecture, comprising: a secondary program loader SPL layer and a first-stage boot loader BL1 layer. The method includes: configuring the basic environment through the SPL layer, selecting the BL1 boot medium and verifying the BL1 image, and jumping to the BL1 layer after successful verification; initializing system resources and interrupt mechanisms through the BL1 layer, building a multi-task runtime environment, and creating and concurrently executing target tasks based on the multi-task runtime environment.

[0006] Optionally, basic environment configuration can be performed through the SPL layer, including: obtaining configuration parameters through the SPL layer, generating stack environment and memory allocation space, wherein the configuration parameters include total memory capacity, stack space starting address and memory allocation partition ratio; obtaining clock initialization parameters, and generating system clock configuration that meets hardware requirements.

[0007] Optionally, selecting the BL1 boot medium and verifying the BL1 image includes: selecting the target boot method for BL1, initializing the boot medium corresponding to the target boot method; reading the BL1 image from the boot medium; and performing integrity verification on the BL1 image using cyclic redundancy check technology.

[0008] Optionally, the system resources and interrupt mechanism are initialized through the BL1 layer, including: reading the resource configuration information of the current hardware platform and generating a system resource initialization configuration adapted to the current hardware platform; obtaining the configuration rules of the interrupt controller and resetting the interrupt vector table to a specified address that the BL1 layer can recognize based on the configuration rules.

[0009] Optionally, the target tasks include peripheral driver initialization tasks, storage media detection tasks, image loading tasks, and security state switching / power domain management tasks.

[0010] Optionally, the method also includes: through the BL1 layer, after the target task is completed, selecting the next level startup mode and initializing the next level startup medium corresponding to the next level startup mode; loading and verifying the next level image based on the next level startup medium, and starting the next level image after the verification is successful.

[0011] Optionally, the method further includes: registering a corresponding interrupt response association for each target task when creating each target task through the BL1 layer. The interrupt response association includes peripheral interrupt associated with the peripheral driver initialization task, storage interrupt associated with the storage medium detection task, data transmission interrupt associated with the image loading task, and power interrupt associated with the security state switching / power domain management task. When the interrupt triggering condition is met, the corresponding target task is triggered to perform interrupt processing based on the interrupt response association through the BL1 layer.

[0012] According to another aspect of the present invention, a two-level fused boot device for embedded systems is provided, applied to a fused boot architecture, comprising: a secondary program loader SPL layer and a first-stage boot loader BL1 layer, the device comprising:

[0013] The BL1 layer verification and startup module is used to configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After the verification is successful, it jumps to the BL1 layer.

[0014] The multi-task execution module is used to initialize system resources and interrupt mechanisms through the BL1 layer, build a multi-task runtime environment, and create and concurrently execute target tasks based on the multi-task runtime environment.

[0015] According to another aspect of the present invention, an electronic device is provided, the electronic device comprising:

[0016] At least one processor;

[0017] and a memory communicatively connected to the at least one processor;

[0018] The memory stores a computer program that can be executed by the at least one processor, and the computer program is executed by the at least one processor to enable the at least one processor to execute a two-level fusion startup method for an embedded system as described in any embodiment of the present invention.

[0019] According to another aspect of the present invention, a computer-readable storage medium is provided, the computer-readable storage medium storing computer instructions, the computer instructions being configured to cause a processor to execute and implement a two-level fusion startup method for an embedded system as described in any embodiment of the present invention.

[0020] The technical solution of this invention, by verifying the image, can accurately locate the image position and ensure its integrity, preventing startup anomalies. The BL1 layer initializes system resources and interrupt mechanisms, providing hardware support for multi-task operation and interrupt response, improving the system's responsiveness to hardware events. By building a multi-task runtime environment, the linear execution limitation of a single task can be broken, providing support for parallel processing to improve startup efficiency. Concurrent execution of target tasks can reduce serial waiting time, achieving precise association between tasks and interrupts, thus accelerating startup speed and ensuring real-time response to hardware events, avoiding resource waste.

[0021] It should be understood that the description in this section is not intended to identify key or essential features of the embodiments of the present invention, nor is it intended to limit the scope of the invention. Other features of the invention will become readily apparent from the following description. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a flowchart of a two-level fusion startup method for an embedded system provided according to Embodiment 1 of the present invention;

[0024] Figure 2 This is a flowchart of another two-level fusion startup method for embedded systems provided in Embodiment 2 of the present invention;

[0025] Figure 3 This is a schematic diagram of a two-level fusion startup process for an embedded system according to Embodiment 2 of the present invention;

[0026] Figure 4 This is a schematic diagram of the structure of a two-level fusion startup device for an embedded system according to Embodiment 3 of the present invention;

[0027] Figure 5 This is a schematic diagram of the structure of an electronic device that implements a two-level fusion startup method for an embedded system according to an embodiment of the present invention. Detailed Implementation

[0028] To enable those skilled in the art to better understand the present invention, the technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of the present invention.

[0029] It should be noted that the terms "first," "second," etc., in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms "comprising" and "having," and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0030] Example 1

[0031] Figure 1 This document provides a flowchart of a two-level fused boot method for embedded systems, as described in Embodiment 1 of the present invention. This embodiment is applicable to resource-constrained embedded platform boot scenarios. The method can be executed by a two-level fused boot device for embedded systems, which can be implemented in hardware and / or software. It is applied to a fused boot architecture, including a secondary program loader SPL layer and a first-stage boot loader BL1 layer, as shown below. Figure 1 As shown, the method includes:

[0032] S110. Configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After successful verification, jump to the BL1 layer.

[0033] The Second Program Loader (SPL) is an early program layer in the embedded system boot process, a lightweight boot loading module. It is responsible for basic environment configuration, selecting and verifying subsequent boot images, and other preliminary preparations. The Boot Loader Stage 1 (BL1) is the boot layer following the SPL layer. It initializes system resources, builds a multi-tasking environment, and executes target tasks, propelling the system boot process to the next stage. The integrated boot architecture is an embedded system boot architecture that integrates the functions of different boot layers, such as the SPL and BL1 layers. In this architecture, the SPL and BL1 layers work together. After completing basic preparations, the SPL layer jumps to the BL1 layer. The BL1 layer utilizes multi-tasking mechanisms to optimize the boot process, achieving efficient booting of the embedded system. The BL1 image is the program image file of the BL1 layer, stored in the corresponding boot medium. The SPL layer reads and verifies it to ensure its integrity and correctness. Only after successful verification will the SPL layer execute the image, thus starting the BL1 layer.

[0034] Optionally, basic environment configuration can be performed through the SPL layer, including: obtaining configuration parameters through the SPL layer, generating stack environment and memory allocation space, wherein the configuration parameters include total memory capacity, stack space starting address and memory allocation partition ratio; obtaining clock initialization parameters, and generating system clock configuration that meets hardware requirements.

[0035] Specifically, the SPL layer first reads preset configuration parameters, which are predefined based on the hardware resource characteristics of the Cortex-M3 platform. These parameters include total memory capacity, stack space start address, and memory allocation partition ratio. The total memory capacity corresponds to the actual available memory of the Cortex-M3 chip. By reading the total memory capacity, the SPL layer can clearly define the overall boundaries of memory resources, preventing subsequent operations from exceeding the hardware memory range. The stack space start address needs to be set in conjunction with the stack growth direction of the Cortex-M3. Typically, a region with a higher memory address is chosen as the starting point. For example, if the total memory address range is 0x20000000-0x2000FFFF, the stack start address might be set to 0x2000FFFF, while reserving sufficient stack depth to ensure that stack overflow does not occur during the execution of the SPL layer's own code. The memory allocation partition ratio is used to divide the memory into regions for subsequent dynamic memory needs. For example, the remaining memory can be divided into a temporary data storage area and an image preloading area in a 6:4 ratio. The former is used for temporary data caching during the execution of the SPL layer, and the latter is used to temporarily store the BL1 image to be verified. By dividing the memory allocation partition ratio, memory resource contention can be avoided, ensuring that the memory usage of different functional modules is independent and improving configuration stability. After obtaining the configuration parameters, the SPL layer will write to the Cortex-M3's memory control register through hardware initialization instructions to complete the address mapping and permission configuration of the stack space. At the same time, it will call a lightweight memory allocation function to divide the memory into partitions, ultimately generating a stack environment and memory allocation space that can be directly used by the SPL layer and subsequent pre-jump operations.

[0036] It is known that the peripherals and core of the Cortex-M3 platform rely on a stable clock signal for operation. Different hardware modules have different clock frequency requirements; for example, Flash erase / write requires a 24MHz clock, while the core supports a maximum of 72MHz. Therefore, the SPL layer needs to obtain clock initialization parameters, including clock source selection, division ratio, and phase-locked loop (PLL) configuration parameters. After obtaining the clock initialization parameters, the SPL layer completes the clock configuration by operating the Cortex-M3's clock control register. This involves first enabling the selected clock source and waiting for it to stabilize; then configuring the PLL parameters to multiply the frequency; setting the corresponding division register according to the bus division requirements; and finally distributing the configured clock signal to the core and various peripheral modules. By initializing the clock, it ensures that each hardware module receives a clock frequency that matches its operating characteristics, preventing performance degradation due to insufficient clock frequency and preventing malfunctions caused by excessively high frequencies exceeding the hardware's capacity. Ultimately, this generates a stable system clock configuration that meets the hardware requirements of the entire system.

[0037] Optionally, selecting the BL1 boot medium and verifying the BL1 image includes: selecting the target boot method for BL1, initializing the boot medium corresponding to the target boot method; reading the BL1 image from the boot medium; and performing integrity verification on the BL1 image using cyclic redundancy check technology.

[0038] It should be noted that embedded systems on the Cortex-M3 platform typically support multiple boot media, such as on-chip Flash, Serial Peripheral Interface (SPI) Flash, SD card, and UART serial port. Each boot media has different hardware interfaces and data transmission protocols. The SPL layer must first determine the target boot method for BL1 based on the system's preset boot priority, such as defaulting to booting from on-chip Flash and switching when a valid identifier for the external SPI Flash is detected; or based on the hardware pin configuration, i.e., selecting the boot method based on the pin level status. After selecting the target boot method, the SPL layer needs to initialize the corresponding boot media. Taking external SPI Flash as an example, the SPL layer will configure the Cortex-M3's SPI peripheral registers to set the SPI communication clock frequency, data bit length, and transmission mode, while simultaneously sending SPI Flash initialization commands. After confirming that the SPI Flash can respond normally, the media initialization is completed.

[0039] The BL1 image typically has a fixed storage address and a preset image size in the boot medium. The SPL layer retrieves the image data using the appropriate reading method based on the characteristics of the target boot medium. If the target boot medium is on-chip Flash, the Cortex-M3 supports direct access via address mapping. The SPL layer can directly read byte data within a specified address range through pointer operations and store it in the previously allocated image preload area. If the target boot medium is external SPI Flash, a page read command must be sent via the SPI bus, specifying the starting address of the BL1 image. Subsequently, the image data returned by the Flash is received byte by byte through the SPI_DR register and stored in the image preload area as well.

[0040] Specifically, during BL1 image generation, the Cyclic Redundancy Check (CRC) value of its complete data is pre-calculated and stored at the end of the image file or a designated check address on the medium, such as the last 4 bytes of the BL1 image storage area. After reading the BL1 image, the SPL layer first extracts the stored preset CRC check value, and then performs CRC calculation on the BL1 image data in the image pre-loading area in memory to generate a real-time CRC check value. The SPL layer then compares the real-time calculated CRC value with the preset CRC value. If they match, it means that no data loss or tampering occurred during the storage and transmission of the BL1 image, the verification passes, and the process can proceed to the BL1 layer. If they do not match, the image is considered corrupted, and the boot process terminates. This integrity check prevents subsequent boot crashes caused by a corrupted BL1 image, ensuring the security and reliability of the boot process.

[0041] S120. Initialize system resources and interrupt mechanisms through BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

[0042] In this context, a multi-tasking runtime environment refers to an execution environment in an embedded system capable of running multiple tasks simultaneously. In a specific implementation, the BL1 layer can be built on FreeRTOS, enabling the system to execute multiple tasks concurrently, thus improving system concurrency and responsiveness. The target task refers to the specific task created and executed within the BL1 layer's multi-tasking runtime environment.

[0043] Optionally, the system resources and interrupt mechanism are initialized through the BL1 layer, including: reading the resource configuration information of the current hardware platform and generating a system resource initialization configuration adapted to the current hardware platform; obtaining the configuration rules of the interrupt controller and resetting the interrupt vector table to a specified address that the BL1 layer can recognize based on the configuration rules.

[0044] Specifically, in embedded systems based on the Cortex-M3 platform, resource distribution varies across different hardware solutions. For example, the number and base addresses of on-chip peripherals, GPIO pin function definitions, and power domain partitioning may all differ. The BL1 layer first obtains resource configuration information through hardware resource probing or reading a pre-defined configuration table. For standardized hardware platforms, the BL1 layer reads a resource configuration table pre-stored in ROM or a specified memory address. For flexibly configurable platforms, the BL1 layer identifies the types and quantities of mounted peripherals using probing instructions. After obtaining the resource configuration information, the BL1 layer generates a system resource initialization configuration adapted to the current hardware platform for the core system resources. This system resource initialization configuration can include peripheral clock enabling, peripheral basic parameter configuration, and GPIO pin multiplexing configuration. Taking the UART peripheral as an example, the BL1 layer configures its baud rate, data bits, stop bits, and parity bits by writing to the UART control register's baud rate register, ensuring that the peripheral can be directly used if there is a need for UART data transmission in subsequent multitasking.

[0045] It should be noted that the Cortex-M3 core integrates a Nested Vectored Interrupt Controller (NVIC), which is responsible for managing all interrupt requests in the system. The interrupt vector table is the basis for the NVIC to identify the interrupt source and locate the interrupt service routine address. The interrupt vector table is essentially an array that stores the entry address of the interrupt service routine. By default, it is stored at the starting address of the BootROM. However, since the BL1 layer runs in SRAM or a specific Flash area, the interrupt vector table needs to be redirected to an address range that it can access and manage.

[0046] Specifically, the BL1 layer obtains the NVIC's configuration rules, which include the address alignment requirements for the interrupt vector table, the vector table offset register configuration rules, and the interrupt priority grouping rules. After obtaining the configuration rules, the BL1 layer performs an interrupt vector table reset operation: First, it creates the BL1 interrupt vector table in the BL1 layer's memory area. This table contains the entry addresses of the interrupt service routines required by the BL1 layer. Then, it configures the NVIC's Vector Table Offset Register (VTOR) by writing the base address of the BL1 interrupt vector table to the VTOR. At this point, the NVIC stops reading the vector table from the default BootROM address and instead obtains it from the new address. Necessary interrupt sources are enabled. For example, if FreeRTOS's task scheduling relies on SysTick timer interrupts, the BL1 layer configures the SysTick timer's reload value and sets the SysTick interrupt enable bit to 1 through the interrupt enable register, ensuring that task scheduling interrupts can be responded to. By resetting the interrupt vector table, interrupt management authority is transferred from the SPL layer to the BL1 layer. At the same time, it ensures that multiple tasks in the BL1 layer can quickly respond to interrupts through the NVIC, avoiding interrupts that cannot be handled or system crashes caused by incorrect interrupt service routine addresses, and providing reliable interrupt support for concurrent execution of multiple tasks.

[0047] Optionally, the target tasks include peripheral driver initialization tasks, storage media detection tasks, image loading tasks, and security state switching / power domain management tasks.

[0048] The peripheral driver initialization task is a fundamental task executed by the BL1 layer based on the FreeRTOS multi-tasking environment. Its goal is to build a usable hardware peripheral foundation for subsequent tasks such as storage media detection and image loading. Specifically, it initializes and configures key peripherals necessary for BL2 startup. This includes manipulating the corresponding control registers of the peripherals, setting communication parameters, and configuring the GPIO pin multiplexing functions associated with the peripherals. The storage media detection task identifies the storage media information where the BL2 image resides, providing a clear loading target for subsequent image loading tasks. This ensures accurate loading and avoids blind loading that could lead to startup failure. The image loading task is responsible for safely and efficiently reading the BL2 image from the storage media into a specified memory area. Before execution, it is necessary to clarify the media parameters passed by the storage media detection task and the BL2 image parameters preset by the SPL layer. During the loading process, the image data is read segment by segment according to the sector / block size of the media through the corresponding peripherals. Simultaneously, the task records the number of bytes loaded in real time. When the loaded amount reaches the preset image size, a loading completion event is triggered, notifying subsequent processes to prepare to jump to BL2. The secure state switching / power domain management task ensures the security and hardware stability of the boot process, adapting to the security architecture and low-power requirements of the Cortex-M3 platform. Regarding secure state switching, if the system supports secure / unsecure dual-state operation, the task first reads the preset security configuration table, marks the address space of secure peripherals as secure domains by manipulating the Cortex-M3's security control registers, and then executes the secure state switching instruction to switch the CPU from the unsecured state at the SPL layer to the secure state at the BL1 layer. This ensures that sensitive operations such as image loading and encryption verification are performed in a secure environment, preventing malicious code tampering. Regarding power domain management, based on the peripheral usage requirements during the boot phase, the task disables the power domains corresponding to inactive peripherals and reduces system power consumption by manipulating the power control registers. Simultaneously, it monitors the voltage stability of the kernel power domain in real time. If voltage fluctuations are detected, a power protection event is immediately triggered, pausing tasks such as image loading until the voltage stabilizes, ensuring stable hardware operation.

[0049] Optionally, the method further includes: registering a corresponding interrupt response association for each target task when creating each target task through the BL1 layer. The interrupt response association includes peripheral interrupt associated with the peripheral driver initialization task, storage interrupt associated with the storage medium detection task, data transmission interrupt associated with the image loading task, and power interrupt associated with the security state switching / power domain management task. When the interrupt triggering condition is met, the corresponding target task is triggered to perform interrupt processing based on the interrupt response association through the BL1 layer.

[0050] It should be noted that after creating the four target tasks of peripheral driver initialization, storage media detection, image loading, and security state switching / power domain management, the BL1 layer will register the associated relationships one by one according to the corresponding logic of the task function and hardware interrupt source.

[0051] Specifically, peripheral driver initialization tasks are associated with peripheral interrupts, storage media detection tasks are associated with storage interrupts, image loading tasks are associated with data transfer interrupts, and security state / power domain management tasks are associated with power interrupts. This binding can be achieved by configuring peripheral interrupt enable registers and the FreeRTOS interrupt safety API. When a hardware event triggers an interrupt, the NVIC calls the corresponding Interrupt Service Routine (ISR) based on the BL1 interrupt vector table. After the ISR verifies its validity, it synchronizes the event to the associated task via FreeRTOS task notification / queue. The kernel schedules the task from blocked to ready state to execute interrupt handling, reducing CPU polling overhead and ensuring real-time event response.

[0052] The technical solution of this invention, by verifying the image, can accurately locate the image position and ensure its integrity, preventing startup anomalies. Initializing system resources and interrupt mechanisms through the BL1 layer provides hardware support for multi-task operation and interrupt response, improving the system's responsiveness to hardware events. Building a multi-task runtime environment breaks the linear execution limitation of single tasks, providing support for parallel processing to improve startup efficiency. Concurrent execution of target tasks reduces serial waiting time, achieving precise association between tasks and interrupts, thus accelerating startup speed and ensuring real-time response to hardware events, avoiding resource waste.

[0053] Example 2

[0054] Figure 2 This is a flowchart of a two-level fusion startup method for an embedded system provided in Embodiment 2 of the present invention. This embodiment adds a specific process for starting the next-level image based on Embodiment 1. The specific content of steps S210-S220 is largely the same as steps S110-S120 in Embodiment 1, therefore it will not be described again in this embodiment. Figure 2 As shown, the method includes:

[0055] S210. Configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After successful verification, jump to the BL1 layer.

[0056] Optionally, basic environment configuration can be performed through the SPL layer, including: obtaining configuration parameters through the SPL layer, generating stack environment and memory allocation space, wherein the configuration parameters include total memory capacity, stack space starting address and memory allocation partition ratio; obtaining clock initialization parameters, and generating system clock configuration that meets hardware requirements.

[0057] Optionally, selecting the BL1 boot medium and verifying the BL1 image includes: selecting the target boot method for BL1, initializing the boot medium corresponding to the target boot method; reading the BL1 image from the boot medium; and performing integrity verification on the BL1 image using cyclic redundancy check technology.

[0058] S220. Initialize system resources and interrupt mechanisms through BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

[0059] Optionally, the system resources and interrupt mechanism are initialized through the BL1 layer, including: reading the resource configuration information of the current hardware platform and generating a system resource initialization configuration adapted to the current hardware platform; obtaining the configuration rules of the interrupt controller and resetting the interrupt vector table to a specified address that the BL1 layer can recognize based on the configuration rules.

[0060] Optionally, the target tasks include peripheral driver initialization tasks, storage media detection tasks, image loading tasks, and security state switching / power domain management tasks.

[0061] Optionally, the method further includes: registering a corresponding interrupt response association for each target task when creating each target task through the BL1 layer. The interrupt response association includes peripheral interrupt associated with the peripheral driver initialization task, storage interrupt associated with the storage medium detection task, data transmission interrupt associated with the image loading task, and power interrupt associated with the security state switching / power domain management task. When the interrupt triggering condition is met, the corresponding target task is triggered to perform interrupt processing based on the interrupt response association through the BL1 layer.

[0062] S230. Through the BL1 layer, after the target task is completed, select the next level of startup mode and initialize the next level of startup medium corresponding to the next level of startup mode.

[0063] Specifically, at the BL1 layer, after all target tasks such as peripheral driver initialization, storage media detection, image loading, and security / power domain management are completed, the next-level boot mode selection operation is executed first. The selection is based on the system's preset boot priority or hardware pin status. For example, if a BL2 image identifier is detected in the external SPI Flash, SPI Flash is selected as the next-level boot mode; if not detected, other media are switched according to priority. After determining the boot mode, the corresponding next-level boot media needs to be initialized. Taking SPI Flash as an example, the BL1 layer will further optimize the media-specific configuration based on the SPI peripheral basic parameters configured in the previous peripheral driver initialization task. For example, the SPI clock frequency is adjusted to the highest speed supported by the Flash to improve read efficiency, and the Flash chip select pin is configured to remain stably enabled.

[0064] S240: Load and verify the next-level image based on the next-level boot media. After successful verification, start the next-level image.

[0065] Specifically, when loading the next-level image, the BL1 layer calls the corresponding read logic based on the media type. For example, when loading from SPI Flash, it sends a sector read command via the SPI peripheral, specifying the starting address of the BL2 image's storage in the Flash, and reads the image data segment by segment into the preset loading area. After loading, integrity verification is performed using the same CRC technique as the BL1 image verification. That is, the preset CRC check value stored at the end of the next-level image is extracted first, and then the CRC value of the image data loaded into memory is calculated in real time. When the two are consistent, it indicates that the image is not corrupted. After the verification passes, the BL1 layer executes a jump instruction, transferring CPU execution to the next-level image, completing the downward connection of the boot process.

[0066] Specific application scenarios: Figure 3 This is a schematic diagram of a two-level fusion startup process of an embedded system provided in Embodiment 2 of the present invention. Figure 3The document demonstrates a two-level fused boot process for an embedded system based on the ARM Cortex-M3 architecture, divided into two stages: Bootrom level (SPL layer) and FreeRTOS level (BL1 layer). Upon power-up, the Bootrom level process begins. The first step involves basic environment configuration, including stack and malloc space allocation for temporary memory resources; clock initialization is also performed, configuring the system clock according to hardware characteristics to ensure stable hardware module operation. Next, the BL1 boot mode is selected, determining the storage medium for the BL1 image based on the system's preset priority or hardware pin status, and then initializing the corresponding boot mode medium. The BL1 image is then read from the selected boot medium, and its integrity is verified using cyclic redundancy check (CRC) technology. Upon successful verification, execution jumps to the BL1 layer. Entering the FreeRTOS level process, the interrupt vector table is first reset and redirected to memory addresses manageable by the BL1 layer, enabling the NVIC to recognize BL1 layer interrupt service routines; simultaneously, system resources and interrupts are initialized, peripheral resources are configured, and critical interrupts are enabled. Finally, the next boot mode is determined, and the corresponding boot medium is initialized. Next, the next-level image is read from and verified from the boot medium, using CRC technology to ensure its validity. Then, a multi-tasking runtime environment is built based on FreeRTOS, creating target tasks such as peripheral driver initialization and storage media detection. Simultaneously, interrupt response associations are registered for each task. When an interrupt is triggered, the BL1 layer triggers the corresponding task to execute interrupt handling based on the association. Finally, after the next-level image passes verification, execution jumps to that image, completing the downward connection of the boot process. This process, through a two-level architecture combining basic preparation at the SPL layer and multi-tasking optimization at the BL1 layer, solves the boot efficiency problem of resource-constrained embedded platforms. Furthermore, the multi-tasking and interrupt linkage mechanism improves the maintainability and responsiveness of the boot process.

[0067] The technical solution of this invention, through the BL1 layer selecting the next-level boot method after the target task is executed, can accurately determine the storage medium direction for subsequent boots, avoiding boot path confusion and providing clear guidance for the next-level boot. By initializing the next-level boot medium corresponding to the next-level boot method, hardware differences between different media can be eliminated, a stable image reading link can be established, and subsequent image loading operations can be carried out normally. By loading the next-level image based on the next-level boot medium, the image can be reliably read from the storage medium to the specified memory area, providing the program foundation for the next-level boot. After successful verification, the next-level image is started, which can achieve a smooth connection of the boot process, ensure the normal execution of the next-level program, and promote the complete advancement of the boot chain.

[0068] Example 3

[0069] Figure 4This is a schematic diagram of a two-level fused boot device for an embedded system provided in Embodiment 3 of the present invention. It is applied to a fused boot architecture, comprising a secondary program loader SPL layer and a first-stage boot loader BL1 layer, as shown below. Figure 4 As shown, the device includes:

[0070] The BL1 layer verification and startup module 310 is used to configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After the verification is successful, it jumps to the BL1 layer.

[0071] The multi-task execution module 320 is used to initialize system resources and interrupt mechanisms through the BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment.

[0072] Optionally, the BL1 layer verification and startup module 310 specifically includes: a basic environment configuration unit, used to: obtain configuration parameters through the SPL layer, generate a stack environment and memory allocation space, wherein the configuration parameters include total memory capacity, stack space starting address and memory allocation partition ratio; obtain clock initialization parameters, and generate a system clock configuration that meets hardware requirements.

[0073] Optionally, the BL1 layer verification and startup module 310 specifically includes: a BL1 image verification unit, used for: selecting the target startup method of BL1, initializing the startup medium corresponding to the target startup method; reading the BL1 image from the startup medium; and performing integrity verification on the BL1 image using cyclic redundancy check technology.

[0074] Optionally, the multi-task execution module 320 is specifically used for: reading the resource configuration information of the current hardware platform and generating a system resource initialization configuration adapted to the current hardware platform; obtaining the configuration rules of the interrupt controller and resetting the interrupt vector table to a specified address that can be recognized by the BL1 layer based on the configuration rules.

[0075] Optionally, the device further includes: a next-level image startup module, used to: select the next-level startup method and initialize the next-level startup medium corresponding to the next-level startup method after the target task is completed through the BL1 layer; load and verify the next-level image based on the next-level startup medium, and start the next-level image after the verification is successful.

[0076] Optionally, the device further includes an interrupt handling module, used to: register a corresponding interrupt response association for each task when creating each target task through the BL1 layer, wherein the interrupt response association includes peripheral interrupt associated with the peripheral driver initialization task, storage interrupt associated with the storage medium detection task, data transmission interrupt associated with the image loading task, and power interrupt associated with the security state switching / power domain management task; when the interrupt triggering condition is met, the corresponding target task is triggered to perform interrupt handling through the BL1 layer based on the interrupt response association.

[0077] The technical solution of this invention, by verifying the image, can accurately locate the image position and ensure its integrity, preventing startup anomalies. Initializing system resources and interrupt mechanisms through the BL1 layer provides hardware support for multi-task operation and interrupt response, improving the system's responsiveness to hardware events. Building a multi-task runtime environment breaks the linear execution limitation of single tasks, providing support for parallel processing to improve startup efficiency. Concurrent execution of target tasks reduces serial waiting time, achieving precise association between tasks and interrupts, thus accelerating startup speed and ensuring real-time response to hardware events, avoiding resource waste.

[0078] The embedded system two-level fusion startup device provided in this embodiment of the invention can execute the embedded system two-level fusion startup method provided in any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

[0079] Example 4

[0080] Figure 5 A schematic diagram of an electronic device 10 that can be used to implement embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital assistants, cellular phones, smartphones, wearable devices (e.g., helmets, glasses, watches, etc.), and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the invention described and / or claimed herein.

[0081] like Figure 5As shown, the electronic device 10 includes at least one processor 11 and a memory, such as a read-only memory (ROM) 12 or a random access memory (RAM) 13, communicatively connected to the at least one processor 11. The memory stores computer programs executable by the at least one processor. The processor 11 can perform various appropriate actions and processes based on the computer program stored in the ROM 12 or loaded into the RAM 13 from storage unit 18. The RAM 13 can also store various programs and data required for the operation of the electronic device 10. The processor 11, ROM 12, and RAM 13 are interconnected via a bus 14. An input / output (I / O) interface 15 is also connected to the bus 14.

[0082] Multiple components in electronic device 10 are connected to I / O interface 15, including: input unit 16, such as keyboard, mouse, etc.; output unit 17, such as various types of displays, speakers, etc.; storage unit 18, such as disk, optical disk, etc.; and communication unit 19, such as network card, modem, wireless transceiver, etc. Communication unit 19 allows electronic device 10 to exchange information / data with other devices through computer networks such as the Internet and / or various telecommunications networks.

[0083] Processor 11 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. Processor 11 performs the various methods and processes described above, such as a two-level fusion boot method for embedded systems.

[0084] In some embodiments, an embedded system two-level fusion boot method may be implemented as a computer program tangibly contained in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program may be loaded and / or installed on electronic device 10 via ROM 12 and / or communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the embedded system two-level fusion boot method described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform an embedded system two-level fusion boot method by any other suitable means (e.g., by means of firmware).

[0085] Various embodiments of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), systems-on-a-chip (SoCs), payload-programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments may include implementations in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which may be a dedicated or general-purpose programmable processor, capable of receiving data and instructions from a storage system, at least one input device, and at least one output device, and transmitting data and instructions to the storage system, the at least one input device, and the at least one output device.

[0086] Computer programs used to implement the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when executed by the processor, the computer programs cause the functions / operations specified in the flowcharts and / or block diagrams to be performed. The computer programs may be executed entirely on a machine, partially on a machine, or as a standalone software package, partially on a machine and partially on a remote machine, or entirely on a remote machine or server.

[0087] In the context of this invention, a computer-readable storage medium can be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, apparatus, or device. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination thereof. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. More specific examples of machine-readable storage media include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fibers, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination thereof.

[0088] To provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user provides input to the electronic device. Other types of devices can also be used to provide interaction with the user; for example, feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including sound input, voice input, or tactile input).

[0089] The systems and technologies described herein can be implemented in computing systems that include backend components (e.g., as data servers), or middleware components (e.g., application servers), or frontend components (e.g., user computers with graphical user interfaces or web browsers through which users can interact with implementations of the systems and technologies described herein), or any combination of such backend, middleware, or frontend components. The components of the system can be interconnected via digital data communication of any form or medium (e.g., communication networks). Examples of communication networks include local area networks (LANs), wide area networks (WANs), blockchain networks, and the Internet.

[0090] A computing system can include clients and servers. Clients and servers are generally located far apart and typically interact through communication networks. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or cloud host, which is a hosting product within the cloud computing service system to address the shortcomings of traditional physical hosts and VPS services, such as high management difficulty and weak business scalability.

[0091] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps described in this invention can be executed in parallel, sequentially, or in different orders, as long as the desired result of the technical solution of this invention can be achieved, and this is not limited herein.

[0092] The specific embodiments described above do not constitute a limitation on the scope of protection of this invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of this invention should be included within the scope of protection of this invention.

Claims

1. A two-stage fusion booting method for embedded systems, characterized in that, Applied to a converged boot architecture, including: a secondary program loader (SPL) layer and a first-stage boot loader (BL1) layer, the method includes: Configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After the verification is successful, jump to the BL1 layer. By initializing system resources and interrupt mechanisms through the BL1 layer, a multi-task runtime environment is built, and target tasks are created and executed concurrently based on the multi-task runtime environment; The initialization of system resources and interrupt mechanisms through the BL1 layer includes: Read the resource configuration information of the current hardware platform and generate a system resource initialization configuration adapted to the current hardware platform; Obtain the configuration rules of the interrupt controller, and reset the interrupt vector table to a specified address that can be recognized by the BL1 layer based on the configuration rules.

2. The method of claim 1, wherein, The basic environment configuration via the SPL layer includes: The configuration parameters are obtained through the SPL layer to generate the stack environment and memory allocation space. The configuration parameters include the total memory capacity, the starting address of the stack space, and the memory allocation partition ratio. Obtain the clock initialization parameters and generate a system clock configuration that meets the hardware requirements.

3. The method of claim 1, wherein, The process of selecting the BL1 boot media and verifying the BL1 image includes: Select the target boot method for BL1 and initialize the boot media corresponding to the target boot method; Read the BL1 image from the boot medium; The integrity of the BL1 image is verified using cyclic redundancy check technology.

4. The method of claim 1, wherein, The target tasks include peripheral driver initialization, storage media detection, image loading, and security state switching / power domain management.

5. The method of claim 3, wherein, The method further includes: Through the BL1 layer, after the target task is completed, the next level of startup mode is selected and the next level of startup medium corresponding to the next level of startup mode is initialized. The next-level image is loaded and verified based on the next-level boot media. After the verification is successful, the next-level image is started.

6. The method of claim 4, wherein, The method further includes: When creating each target task, the BL1 layer registers a corresponding interrupt response association for each task. The interrupt response association includes peripheral interrupt associated with peripheral driver initialization task, storage interrupt associated with storage medium detection task, data transmission interrupt associated with image loading task, and power interrupt associated with security state switching / power domain management task. When the interrupt triggering conditions are met, the corresponding target task is triggered to perform interrupt processing based on the interrupt response association relationship through the BL1 layer.

7. An embedded system two-stage fusion booting apparatus, characterized by, Applied to a converged boot architecture, including: a secondary program loader SPL layer and a first-stage boot loader BL1 layer, the device includes: The BL1 layer verification and startup module is used to configure the basic environment through the SPL layer, select the BL1 boot media and verify the BL1 image. After the verification is successful, it jumps to the BL1 layer. The multi-task execution module is used to initialize system resources and interrupt mechanisms through the BL1 layer, build a multi-task running environment, and create and concurrently execute target tasks based on the multi-task running environment. The multi-task execution module is specifically used for: reading the resource configuration information of the current hardware platform and generating a system resource initialization configuration adapted to the current hardware platform; obtaining the configuration rules of the interrupt controller and resetting the interrupt vector table to a specified address that can be recognized by the BL1 layer based on the configuration rules.

8. An electronic device, characterized in that, The electronic device includes: At least one processor; and a memory communicatively connected to the at least one processor; The memory stores a computer program that can be executed by the at least one processor, the computer program being executed by the at least one processor to enable the at least one processor to perform the method of any one of claims 1-6.

9. A computer storage medium, characterized in that, The computer storage medium stores computer instructions that are used to cause a processor to execute the method of any one of claims 1-6.

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